Re: [PATCH v2 17/26] ARM: dts: qcom: apq8064: add simple CPUFreq support

[Konrad Dybcio <konrad.dybcio@linaro.org>]

On 25.06.2023 22:25, Dmitry Baryshkov wrote:
> Declare CPU frequency-scaling properties. Each CPU has its own clock,
> how
however?

> all CPUs have the same OPP table. Voltage scaling is not (yet)
> enabled with this patch. It will be enabled later.
Risky business.

> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 170 +++++++++++++++++++++++
>  1 file changed, 170 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> index ac07170c702f..e4d2fd48d843 100644
> --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
> @@ -2,11 +2,13 @@
>  /dts-v1/;
>  
>  #include <dt-bindings/clock/qcom,gcc-msm8960.h>
> +#include <dt-bindings/clock/qcom,krait-cc.h>
>  #include <dt-bindings/clock/qcom,lcc-msm8960.h>
>  #include <dt-bindings/reset/qcom,gcc-msm8960.h>
>  #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
>  #include <dt-bindings/clock/qcom,rpmcc.h>
>  #include <dt-bindings/soc/qcom,gsbi.h>
> +#include <dt-bindings/soc/qcom,krait-l2-cache.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  / {
> @@ -45,6 +47,12 @@ CPU0: cpu@0 {
>  			qcom,acc = <&acc0>;
>  			qcom,saw = <&saw0>;
>  			cpu-idle-states = <&CPU_SPC>;
> +			clocks = <&kraitcc KRAIT_CPU_0>;
> +			clock-names = "cpu";
> +			clock-latency = <100000>;
> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		CPU1: cpu@1 {
> @@ -56,6 +64,12 @@ CPU1: cpu@1 {
>  			qcom,acc = <&acc1>;
>  			qcom,saw = <&saw1>;
>  			cpu-idle-states = <&CPU_SPC>;
> +			clocks = <&kraitcc KRAIT_CPU_1>;
> +			clock-names = "cpu";
> +			clock-latency = <100000>;
> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		CPU2: cpu@2 {
> @@ -67,6 +81,12 @@ CPU2: cpu@2 {
>  			qcom,acc = <&acc2>;
>  			qcom,saw = <&saw2>;
>  			cpu-idle-states = <&CPU_SPC>;
> +			clocks = <&kraitcc KRAIT_CPU_2>;
> +			clock-names = "cpu";
> +			clock-latency = <100000>;
> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		CPU3: cpu@3 {
> @@ -78,6 +98,12 @@ CPU3: cpu@3 {
>  			qcom,acc = <&acc3>;
>  			qcom,saw = <&saw3>;
>  			cpu-idle-states = <&CPU_SPC>;
> +			clocks = <&kraitcc KRAIT_CPU_3>;
> +			clock-names = "cpu";
> +			clock-latency = <100000>;
> +			interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
>  		};
>  
>  		L2: l2-cache {
> @@ -196,6 +222,121 @@ CPU_SPC: spc {
>  		};
>  	};
>  
> +        cpu_opp_table: opp-table-cpu {
> +		compatible = "operating-points-v2-krait-cpu";
> +		nvmem-cells = <&speedbin_efuse>;
> +
> +		/*
> +		 * Voltage thresholds are <target min max>
> +		 */
What voltage thresholds?

> +		opp-384000000 {
> +			opp-hz = /bits/ 64 <384000000>;
> +			opp-peak-kBps = <384000>;
> +			opp-supported-hw = <0x4007>;
> +			/*
> +			 * higher latency as it requires switching between
> +			 * clock sources
> +			 */
> +			clock-latency-ns = <244144>;
> +		};
> +
> +		opp-486000000 {
> +			opp-hz = /bits/ 64 <486000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-594000000 {
> +			opp-hz = /bits/ 64 <594000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-702000000 {
> +			opp-hz = /bits/ 64 <702000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-810000000 {
> +			opp-hz = /bits/ 64 <810000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-918000000 {
> +			opp-hz = /bits/ 64 <918000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1026000000 {
> +			opp-hz = /bits/ 64 <1026000000>;
> +			opp-peak-kBps = <648000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1134000000 {
> +			opp-hz = /bits/ 64 <1134000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1242000000 {
> +			opp-hz = /bits/ 64 <1242000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1350000000 {
> +			opp-hz = /bits/ 64 <1350000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1458000000 {
> +			opp-hz = /bits/ 64 <1458000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4007>;
> +		};
> +
> +		opp-1512000000 {
> +			opp-hz = /bits/ 64 <1512000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x4001>;
> +		};
> +
> +		opp-1566000000 {
> +			opp-hz = /bits/ 64 <1566000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x06>;
> +		};
> +
> +		opp-1674000000 {
> +			opp-hz = /bits/ 64 <1674000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x06>;
> +		};
> +
> +		opp-1728000000 {
> +			opp-hz = /bits/ 64 <1728000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x02>;
> +		};
> +
> +		opp-1782000000 {
> +			opp-hz = /bits/ 64 <1782000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x04>;
> +		};
> +
> +		opp-1890000000 {
> +			opp-hz = /bits/ 64 <1890000000>;
> +			opp-peak-kBps = <1134000>;
> +			opp-supported-hw = <0x04>;
> +		};
> +	};
> +
>  	memory@0 {
>  		device_type = "memory";
>  		reg = <0x0 0x0>;
> @@ -312,6 +453,32 @@ sleep_clk: sleep_clk {
>  		};
>  	};
>  
> +	kraitcc: clock-controller {
> +		compatible = "qcom,krait-cc-v1";
Are we sure we don't wanna rework this compatible? Check the comment in
drivers/clk/qcom/krait-cc.c : krait_add_sec_mux()


> +		clocks = <&gcc PLL9>, /* hfpll0 */
> +			 <&gcc PLL10>, /* hfpll1 */
> +			 <&gcc PLL16>, /* hfpll2 */
> +			 <&gcc PLL17>, /* hfpll3 */
> +			 <&gcc PLL12>, /* hfpll_l2 */
> +			 <&acc0>,
> +			 <&acc1>,
> +			 <&acc2>,
> +			 <&acc3>,
> +			 <&l2cc>;
> +		clock-names = "hfpll0",
> +			      "hfpll1",
> +			      "hfpll2",
> +			      "hfpll3",
> +			      "hfpll_l2",
> +			      "acpu0_aux",
> +			      "acpu1_aux",
> +			      "acpu2_aux",
> +			      "acpu3_aux",
> +			      "acpu_l2_aux";
> +		#clock-cells = <1>;
> +		#interconnect-cells = <1>;
> +	};
> +
>  	sfpb_mutex: hwmutex {
>  		compatible = "qcom,sfpb-mutex";
>  		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
> @@ -933,6 +1100,9 @@ qfprom: qfprom@700000 {
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> +			speedbin_efuse: speedbin@c0 {
> +				reg = <0x0c0 0x4>;
> +			};
Newline between properties and subnodes & between individual subnodes,
please

Konrad
>  			tsens_calib: calib@404 {
>  				reg = <0x404 0x10>;
>  			};