From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f67.google.com (mail-lf1-f67.google.com [209.85.167.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE00284E0A for ; Wed, 12 Jun 2024 21:23:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.67 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718227392; cv=none; b=nPGzqMRU7MXcXvNWdfR+cF8/0GFmOoKVH0D6rfSIWv5fafPs/0vngxmGridwB9SQERmMn/GCh+b3wbopyYGG+mSvksN1O9asXi0w+/64BxSc6UxbQ2UIVqD9+Z5bdK+cY8IN2CB2PTbqb8VVwsif8r9Wrntfr2p7e0qab4waFT0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718227392; c=relaxed/simple; bh=2T6gZ7EEse7y1Sv1WZ9KMDR0fG0OjHjw17gxaTFfib0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=bFz3DfRseu95my5YBiFbawV4I64vyaN9Zj1l8tIaOeH/sMoZo3pUOIosWCq0S9L1vdvJ9A6apeLjpbgLdJv+/Dp3uASDg76apRLYV3wlx3gEiqIItOZV940x05PqSuOxDDrQaUqW+VWKc5CqGSSAx6/nW6JEyAqGlZB9SM2wjcI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ACnKSU4q; arc=none smtp.client-ip=209.85.167.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ACnKSU4q" Received: by mail-lf1-f67.google.com with SMTP id 2adb3069b0e04-52c8260a9a9so56551e87.0 for ; Wed, 12 Jun 2024 14:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1718227389; x=1718832189; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=jowrInf5O80KtTvVyPQmOW7J8r+ZDPgzfIXrxnvdHXo=; b=ACnKSU4q0Bk1sEugeLy4W8opJ/VxcqkOXnoCLdF8Yi3lKfLUhv/gxp+Ilvx6yBegsd 1Ek2fOcqB0B0Nd+aQi1Tm/mhQTCO0HEtjjaHo+BmRFRj7xJmfjyj8VbvjQ6TC9FvPUl9 wcpzxkMqzxEGKQkR267YK6SJ0eyBJbsVVmfq4GK7cBICMKxuGrkk4lFHfPC39t4TLAaM otjV8PUQHLpB1+BIMTOY7coszja6qiJY72zr23uE2yeyKrRPe9HvOqMie3+l8EG8P4KP BIYlUx8ci1T2blQNc58PervEBlXrj2fg3t2RUQvqRy/wrFaP2Tkf9edkGLU9lq8sEh+Y wKOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718227389; x=1718832189; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jowrInf5O80KtTvVyPQmOW7J8r+ZDPgzfIXrxnvdHXo=; b=tnUP0ApEMBTIlJsTcKPApVgcK49TAW7EChtIkbXLGXJQfILQ+eBCyrohSLe1uXrsj7 nVy5zn9LwpLUrzvwhDJusYBFbmnLUl8jC0wE3uBLINTmvG96WoCMdxz4afWneJg0bgKs wUS+Gini4UC1a/JRmpReaYytA0yA8UJI0gGS5aZHfWfTELljgsmzQlhHD0orJELcHdiz soaHJmxxqEVpXPz3qFooefrUNzQHWco6TCMtWno7n8YdyxT5WBi9vDR2bXa7UADxdnNF lKBmz4fUMU2m7L0dDWrATTYtVspsL8FyPEUARbuPsuIYAo1u19qC95Y3Y9jYw6mwqzRk wYjw== X-Forwarded-Encrypted: i=1; AJvYcCV5gD+rg0yk7zqMwFEG/iS2lT6op0f75QliAS5vWlbW6R6/LqpElNJNIlzhAoFKeSNQ2Wbvn4BhnNwpjcUd2pbIw1RQj0ycKUXVOg== X-Gm-Message-State: AOJu0YyijYxGExN/wigxcPp+KxZdmvTRtLjdgcyRrBQ2fKi72YRHQfeN CykxhxXOLuc3p66BOx9N8M5t378lNTIjsZHaNw+/ik3IHLgsJ3A9IC01IXjPvuw= X-Google-Smtp-Source: AGHT+IHkk2lAXNm9+BSIbdQPTDnRwExlmJx8FGNX6T88IDk+5uIBJ09Vd4kpOGd505sPIGXbtc1bfA== X-Received: by 2002:a05:6512:3288:b0:52b:bde6:2dba with SMTP id 2adb3069b0e04-52c9a42b427mr1788782e87.6.1718227389131; Wed, 12 Jun 2024 14:23:09 -0700 (PDT) Received: from [192.168.1.3] (88-112-131-206.elisa-laajakaista.fi. [88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52c9daaf31fsm349089e87.104.2024.06.12.14.23.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Jun 2024 14:23:08 -0700 (PDT) Message-ID: <0f13ab6b-dff1-4b26-9707-704ae2e2b535@linaro.org> Date: Thu, 13 Jun 2024 00:22:42 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 8/8] arm64: dts: qcom: sm8650: Add video and camera clock controllers Content-Language: en-US To: Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Satya Priya Kakitapalli , Ajit Pandey , Imran Shaik References: <20240602114439.1611-1-quic_jkona@quicinc.com> <20240602114439.1611-9-quic_jkona@quicinc.com> From: Vladimir Zapolskiy In-Reply-To: <20240602114439.1611-9-quic_jkona@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Jagadeesh. On 6/2/24 14:44, Jagadeesh Kona wrote: > Add device nodes for video and camera clock controllers on Qualcomm > SM8650 platform. > > Signed-off-by: Jagadeesh Kona > Reviewed-by: Vladimir Zapolskiy > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 336c54242778..d964762b0532 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -4,10 +4,12 @@ > */ > > #include > +#include > #include > #include > #include > #include > +#include > #include > #include > #include > @@ -3315,6 +3317,30 @@ opp-202000000 { > }; > }; > > + videocc: clock-controller@aaf0000 { > + compatible = "qcom,sm8650-videocc"; > + reg = <0 0x0aaf0000 0 0x10000>; > + clocks = <&bi_tcxo_div2>, > + <&gcc GCC_VIDEO_AHB_CLK>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + camcc: clock-controller@ade0000 { > + compatible = "qcom,sm8650-camcc"; > + reg = <0 0x0ade0000 0 0x20000>; > + clocks = <&gcc GCC_CAMERA_AHB_CLK>, > + <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; When you test the change on a particular board, do you get here any build time warning messages like this one? clock-controller@ade0000: 'required-opps' is a required property from schema $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml# I believe it's a valid warning, which has to be fixes, and as it says it corresponds to the required property exactly. > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > mdss: display-subsystem@ae00000 { > compatible = "qcom,sm8650-mdss"; > reg = <0 0x0ae00000 0 0x1000>; -- Best wishes, Vladimir