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[82.149.1.233]) by smtp.gmail.com with ESMTPSA id w4-20020adfec44000000b00317614b6a5dsm11125160wrn.50.2023.07.30.15.30.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jul 2023 15:30:42 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: linux-spi@vger.kernel.org, Maksim Kiselev Cc: Maksim Kiselev , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , Samuel Holland , Mark Brown , Cristian Ciocaltea , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port Date: Mon, 31 Jul 2023 00:30:39 +0200 Message-ID: <10311404.nUPlyArG6x@jernej-laptop> In-Reply-To: <20230624131632.2972546-4-bigunclemax@gmail.com> References: <20230624131632.2972546-1-bigunclemax@gmail.com> <20230624131632.2972546-4-bigunclemax@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a): > Add pinmux node that describes pins on PC port which required for > QSPI mode. > > Signed-off-by: Maksim Kiselev > --- > arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index > 1bb1e5cae602..9f754dd03d85 100644 > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins { > pins = "PB6", "PB7"; > function = "uart3"; > }; > + > + /omit-if-no-ref/ > + qspi0_pc_pins: qspi0-pc-pins { > + pins = "PC2", "PC3", "PC4", "PC5", "PC6", > + "PC7"; > + function = "spi0"; > + }; Sorry for late review, but it seems I'm missing something. D1 manual says those are pins for ordinary SPI, with HOLD and WP signals. Can they be repurposed for quad SPI? Best regards, Jernej > }; > > ccu: clock-controller@2001000 {