devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Conor.Dooley@microchip.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, Daire.McNamara@microchip.com,
	Shravan.Chippa@microchip.com
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, Cyril.Jean@microchip.com,
	Lewis.Hanly@microchip.com, Praveen.Kumar@microchip.com,
	wg@aries-embedded.de, Hugh.Breslin@microchip.com,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp
Date: Tue, 30 Aug 2022 19:55:47 +0300	[thread overview]
Message-ID: <1065bc99-d73a-9d19-7f09-26cd862fe0c7@linaro.org> (raw)
In-Reply-To: <27b8aa9e-9173-b40e-8f9c-a53fa5ba36c8@microchip.com>

On 30/08/2022 18:25, Conor.Dooley@microchip.com wrote:
> On 30/08/2022 15:37, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 30/08/2022 13:17, Conor Dooley wrote:
>>> Add compatibles for both configurations of the Aries Embedded
>>> M100PFSEVP SOM + EVK platform.
>>>
>>> Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>>  Documentation/devicetree/bindings/riscv/microchip.yaml | 3 +++
>>>  1 file changed, 3 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
>>> index 485981fbfb4b..04ebd48caaa7 100644
>>> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml
>>> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
>>> @@ -27,9 +27,12 @@ properties:
>>>
>>>        - items:
>>>            - enum:
>>> +              - aries,m100pfsevp-emmc
>>> +              - aries,m100pfsevp-sdcard
>>
>> Usually sd card is pluggable, so what is the actual difference here? For
>> example this one:
>> https://shop.aries-embedded.de/evaluation-kit/m/m100pfsevp/445/m100pfsevp-250baab
>> has eMMC and SD card...
> 
> Yeah, both are there but it is muxed by the bootloader using a GPIO. For
> icicle this is done by a mux in the FPGA fabric instead. T

Ah, this is still just one MMC controller - either as eMMC or as SD-card?

> w dts were
> needed so that the gpio-hog could be set correctly. Out of curiosity, I can
> have the same compatible in multiple devicetrees right? In that case, it
> would just be "aries,m100pfsevp" here and I could put that in both?
> Would make things easier..

Depends, but I would say for this case rather not. The compatible should
identify the board. If the boards are different, one compatible should
not identify both of them. Imagine U-Boot (or something else) trying to
match the DTS.

Best regards,
Krzysztof

  reply	other threads:[~2022-08-30 16:55 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-30 10:17 [PATCH v2 0/9] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-08-30 10:17 ` [PATCH v2 1/9] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-08-30 10:17 ` [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp Conor Dooley
2022-08-30 14:37   ` Krzysztof Kozlowski
2022-08-30 15:25     ` Conor.Dooley
2022-08-30 16:55       ` Krzysztof Kozlowski [this message]
2022-08-30 16:59         ` Conor.Dooley
2022-08-30 17:30           ` Krzysztof Kozlowski
2022-08-30 17:35             ` Conor.Dooley
2022-08-30 17:47               ` Krzysztof Kozlowski
2022-08-30 17:55                 ` Conor.Dooley
2022-08-30 10:17 ` [PATCH v2 3/9] dt-bindings: riscv: microchip: document the sev kit Conor Dooley
2022-08-30 10:17 ` [PATCH v2 4/9] riscv: dts: microchip: add pci dma ranges for the icicle kit Conor Dooley
2022-08-30 10:18 ` [PATCH v2 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Conor Dooley
2022-08-30 10:18 ` [PATCH v2 6/9] riscv: dts: microchip: icicle: update pci address properties Conor Dooley
2022-08-30 10:44   ` Ben Dooks
2022-08-30 12:06     ` Conor.Dooley
2022-08-30 10:18 ` [PATCH v2 7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Conor Dooley
2022-08-30 10:18 ` [PATCH v2 8/9] riscv: dts: microchip: add sevkit device tree Conor Dooley
2022-08-30 10:18 ` [PATCH v2 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Conor Dooley

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1065bc99-d73a-9d19-7f09-26cd862fe0c7@linaro.org \
    --to=krzysztof.kozlowski@linaro.org \
    --cc=Conor.Dooley@microchip.com \
    --cc=Cyril.Jean@microchip.com \
    --cc=Daire.McNamara@microchip.com \
    --cc=Hugh.Breslin@microchip.com \
    --cc=Lewis.Hanly@microchip.com \
    --cc=Praveen.Kumar@microchip.com \
    --cc=Shravan.Chippa@microchip.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=devicetree@vger.kernel.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    --cc=wg@aries-embedded.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).