* [PATCH 1/4] bus: uniphier-system-bus: add UniPhier System Bus Controller driver
2015-11-24 9:39 [PATCH 0/4] arm,arm64: uniphier: add a new driver, device tree updates Masahiro Yamada
@ 2015-11-24 9:39 ` Masahiro Yamada
2015-11-24 11:50 ` Mark Rutland
2015-11-24 9:39 ` [PATCH 2/4] ARM: dts: uniphier: add better-matching compatible string to extbus nodes Masahiro Yamada
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Masahiro Yamada @ 2015-11-24 9:39 UTC (permalink / raw)
To: arm
Cc: Masahiro Yamada, devicetree, Kumar Gala, linux-kernel,
Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland,
linux-arm-kernel
The UniPhier System Bus is an external bus where on-board devices are
connected to the UniPhier SoC. This driver parses the "ranges"
property of the System Bus and set up the registers of the System Bus
Controller for the correct bus routing.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
.../bindings/arm/uniphier/uniphier-system-bus.txt | 70 +++++
MAINTAINERS | 1 +
drivers/bus/Kconfig | 9 +
drivers/bus/Makefile | 1 +
drivers/bus/uniphier-system-bus.c | 284 +++++++++++++++++++++
5 files changed, 365 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/uniphier/uniphier-system-bus.txt
create mode 100644 drivers/bus/uniphier-system-bus.c
diff --git a/Documentation/devicetree/bindings/arm/uniphier/uniphier-system-bus.txt b/Documentation/devicetree/bindings/arm/uniphier/uniphier-system-bus.txt
new file mode 100644
index 0000000..a50db0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/uniphier/uniphier-system-bus.txt
@@ -0,0 +1,70 @@
+UniPhier System Bus
+-------------------
+
+The UniPhier System Bus is an external bus where on-board devices are connected
+to the UniPhier SoC. It it a simple parallel bus with address, data, and some
+control signals. It supports up to 8 banks (chip selects).
+
+Required properties for System Bus:
+- compatible: should be "socionext,uniphier-system-bus", "simple-bus".
+- #address-cells: should be equal to or grater than 2. The first cell is the
+ bank number (chip select). The rest is the base address within the bank that
+ should be mapped onto the parent bus (usually AMBA).
+
+Optional properties for System Bus:
+- #size-cells: should be the same as that of the parent bus, if exists. The
+ value of the parent bus is assumed, if not specified.
+
+
+UniPhier System Bus Controller
+------------------------------
+
+The UniPhier System Bus Controller is a hardware block with registers that
+controls the System Bus accessing; how each bank is mapped onto the parent bus,
+various timing parameters of the bus access, etc.
+
+Required properties for System Bus Controller:
+- compatible: should be "socionext,uniphier-system-bus-controller".
+- reg: offsets and lengths of the register sets for the device. It should
+ contain 2 regions: base & control register, misc register, in this order.
+
+
+Example
+-------
+ system_bus: system-bus {
+ compatible = "socionext,uniphier-system-bus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0x00000000 0x42000000 0x02000000
+ 5 0x00000000 0x48000000 0x01000000>;
+
+ eth: ethernet@1,01f00000 {
+ compatible = "smsc,lan9115";
+ reg = <1 0x01f00000 0x1000>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ };
+
+ serial: uart@5,00200000 {
+ compatible = "ns16550a";
+ reg = <5 0x00200000 0x20>;
+ clock-frequency = <12288000>;
+ reg-shift = <1>;
+ };
+ };
+
+ system-bus-controller@58c00000 {
+ compatible = "socionext,uniphier-system-bus-controller";
+ reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
+ system-bus = <&system_bus>;
+ };
+
+In this example, the range 0x00000000-0x02000000 of bank 1 (CS1) is mapped to
+the range 0x42000000-0x44000000 of the parent bus.
+Likewise, the range 0x00000000-0x01000000 of bank 5 (CS5) is mapped to the
+range 0x48000000-0x49000000 of the parent bus.
+
+The Ethernet device is connected at the address 0x01f00000 of CS1, and visible
+at the address 0x43f00000 in the parent bus. The UART device is connected at
+the address 0x00200000 of CS5, and visible at the address 0x48200000 in the
+parent bus.
diff --git a/MAINTAINERS b/MAINTAINERS
index 050d0e7..e849a38 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1642,6 +1642,7 @@ F: arch/arm/boot/dts/uniphier*
F: arch/arm/include/asm/hardware/cache-uniphier.h
F: arch/arm/mach-uniphier/
F: arch/arm/mm/cache-uniphier.c
+F: drivers/bus/uniphier-system-bus.c
F: drivers/i2c/busses/i2c-uniphier*
F: drivers/pinctrl/uniphier/
F: drivers/tty/serial/8250/8250_uniphier.c
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 116b363..5a772fc 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -131,6 +131,15 @@ config SUNXI_RSB
with various RSB based devices, such as AXP223, AXP8XX PMICs,
and AC100/AC200 ICs.
+config UNIPHIER_SYSTEM_BUS
+ tristate "UniPhier System Bus Controller"
+ depends on ARCH_UNIPHIER
+ default y
+ help
+ Driver to set up the System Bus Controller on UniPhier SoCs.
+ This is needed to use on-board devices connected to the System Bus
+ (external bus) of UniPhier SoCs.
+
config VEXPRESS_CONFIG
bool "Versatile Express configuration bus"
default y if ARCH_VEXPRESS
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index fcb9f97..ccff007 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
+obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
diff --git a/drivers/bus/uniphier-system-bus.c b/drivers/bus/uniphier-system-bus.c
new file mode 100644
index 0000000..40cbf9e
--- /dev/null
+++ b/drivers/bus/uniphier-system-bus.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/log2.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/sort.h>
+
+#define UNIPHIER_SBC_NR_BANKS 8 /* number of banks (chip select) */
+
+#define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */
+#define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */
+#define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */
+#define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */
+#define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */
+#define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */
+#define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */
+
+#define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
+
+struct uniphier_sbc_bank {
+ u32 base;
+ u32 end;
+};
+
+struct uniphier_sbc_priv {
+ struct device *dev;
+ void __iomem *membase;
+ struct uniphier_sbc_bank bank[UNIPHIER_SBC_NR_BANKS];
+};
+
+static void uniphier_sbc_set_reg(struct uniphier_sbc_priv *priv)
+{
+ void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE;
+ u32 base, end, mask, val;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
+ base = priv->bank[i].base;
+ end = priv->bank[i].end;
+
+ if (base == end)
+ continue;
+
+ mask = base ^ (end - 1);
+
+ val = base & 0xfffe0000;
+ val |= (~mask >> 16) & 0xfffe;
+ val |= UNIPHIER_SBC_BASE_BE;
+
+ dev_dbg(priv->dev, "SBC_BASE[%d] = 0x%08x\n", i, val);
+
+ writel(val, base_reg + UNIPHIER_SBC_STRIDE * i);
+ }
+}
+
+static void uniphier_sbc_check_boot_swap(struct uniphier_sbc_priv *priv)
+{
+ void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE;
+ int is_swapped;
+
+ is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE);
+
+ dev_dbg(priv->dev, "Boot Swap: %s\n", is_swapped ? "on" : "off");
+
+ if (is_swapped)
+ swap(priv->bank[0], priv->bank[1]);
+}
+
+static int uniphier_sbc_get_cells(struct device_node *np, int *child_addrc,
+ int *addrc, int *sizec)
+{
+ u32 cells;
+ int ret;
+
+ *addrc = of_n_addr_cells(np);
+ *sizec = of_n_size_cells(np);
+
+ ret = of_property_read_u32(np, "#address-cells", &cells);
+ if (ret)
+ return ret;
+
+ *child_addrc = cells;
+ if (*child_addrc <= 1)
+ return -EINVAL;
+
+ ret = of_property_read_u32(np, "#size-cells", &cells);
+ if (!ret && cells != *sizec)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int uniphier_sbc_add_bank(struct uniphier_sbc_priv *priv, int bank,
+ u64 child_addr, u64 addr, u64 size)
+{
+ u64 end, mask;
+
+ dev_dbg(priv->dev,
+ "range found: bank = %d, caddr = %08llx, addr = %08llx, size = %08llx\n",
+ bank, child_addr, addr, size);
+
+ if (bank >= ARRAY_SIZE(priv->bank)) {
+ dev_err(priv->dev, "unsupported bank number %d\n", bank);
+ return -EINVAL;
+ }
+
+ if (priv->bank[bank].base || priv->bank[bank].end) {
+ dev_err(priv->dev,
+ "range for bank %d has already been specified\n", bank);
+ return -EINVAL;
+ }
+
+ if (addr > U32_MAX) {
+ dev_err(priv->dev, "base address %llx is too high\n", addr);
+ return -EINVAL;
+ }
+
+ end = addr + size;
+
+ if (child_addr > addr) {
+ dev_err(priv->dev,
+ "base %llx cannot be mapped to %llx of parent\n",
+ child_addr, addr);
+ return -EINVAL;
+ }
+ addr -= child_addr;
+
+ addr = round_down(addr, 0x00020000);
+ end = round_up(end, 0x00020000);
+
+ if (end > U32_MAX) {
+ dev_err(priv->dev, "end address %llx is too high\n", end);
+ return -EINVAL;
+ }
+ mask = addr ^ (end - 1);
+ mask = roundup_pow_of_two(mask);
+
+ addr = round_down(addr, mask);
+ end = round_up(end, mask);
+
+ priv->bank[bank].base = addr;
+ priv->bank[bank].end = end;
+
+ dev_dbg(priv->dev, "range added: bank = %d, addr = %08x, end = %08x\n",
+ bank, priv->bank[bank].base, priv->bank[bank].end);
+
+ return 0;
+}
+
+static int uniphier_sbc_sort_cmp(const void *a, const void *b)
+{
+ return ((struct uniphier_sbc_bank *)a)->base
+ - ((struct uniphier_sbc_bank *)b)->base;
+}
+
+static int uniphier_sbc_check_overlap(struct uniphier_sbc_priv tmp)
+{
+ int i;
+
+ sort(&tmp.bank, ARRAY_SIZE(tmp.bank), sizeof(tmp.bank[0]),
+ uniphier_sbc_sort_cmp, NULL);
+
+ for (i = 0; i < ARRAY_SIZE(tmp.bank) - 1; i++)
+ if (tmp.bank[i].end > tmp.bank[i + 1].base) {
+ dev_err(tmp.dev,
+ "region overlap between %08x-%08x and %08x-%08x\n",
+ tmp.bank[i].base, tmp.bank[i].end,
+ tmp.bank[i + 1].base, tmp.bank[i + 1].end);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int uniphier_sbc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct uniphier_sbc_priv *priv;
+ struct resource *regs;
+ struct device_node *bus_np;
+ int child_addrc, addrc, sizec, bank;
+ u64 child_addr, addr, size;
+ const __be32 *ranges;
+ int rlen, rone, ret;
+
+ bus_np = of_find_compatible_node(NULL, NULL,
+ "socionext,uniphier-system-bus");
+ if (!bus_np)
+ return 0;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->membase = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(priv->membase)) {
+ ret = PTR_ERR(priv->membase);
+ goto out;
+ }
+
+ priv->dev = dev;
+
+ ret = uniphier_sbc_get_cells(bus_np, &child_addrc, &addrc, &sizec);
+ if (ret) {
+ dev_err(dev, "wrong #address-cells or #size-cells for bus\n");
+ goto out;
+ }
+
+ ranges = of_get_property(bus_np, "ranges", &rlen);
+ if (!ranges) {
+ ret = -ENOENT;
+ goto out;
+ }
+
+ rlen /= sizeof(*ranges);
+ rone = child_addrc + addrc + sizec;
+
+ for (; rlen >= rone; rlen -= rone, ranges += rone) {
+ bank = be32_to_cpup(ranges);
+ child_addr = of_read_number(ranges + 1, child_addrc - 1);
+ addr = of_translate_address(bus_np, ranges + child_addrc);
+ if (addr == OF_BAD_ADDR) {
+ ret = -EINVAL;
+ goto out;
+ }
+ size = of_read_number(ranges + child_addrc + addrc, sizec);
+
+ ret = uniphier_sbc_add_bank(priv, bank, child_addr, addr, size);
+ if (ret)
+ goto out;
+ }
+
+ ret = uniphier_sbc_check_overlap(*priv);
+ if (ret)
+ goto out;
+
+ uniphier_sbc_check_boot_swap(priv);
+
+ uniphier_sbc_set_reg(priv);
+
+out:
+ of_node_put(bus_np);
+
+ return ret;
+}
+
+
+
+static const struct of_device_id uniphier_sbc_match[] = {
+ { .compatible = "socionext,uniphier-system-bus-controller" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, uniphier_sbc_match);
+
+static struct platform_driver uniphier_sbc_driver = {
+ .probe = uniphier_sbc_probe,
+ .driver = {
+ .name = "system-bus-controller",
+ .of_match_table = uniphier_sbc_match,
+ },
+};
+module_platform_driver(uniphier_sbc_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier System Bus Controller driver");
+MODULE_LICENSE("GPL");
--
1.9.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 1/4] bus: uniphier-system-bus: add UniPhier System Bus Controller driver
2015-11-24 9:39 ` [PATCH 1/4] bus: uniphier-system-bus: add UniPhier System Bus Controller driver Masahiro Yamada
@ 2015-11-24 11:50 ` Mark Rutland
2015-11-24 16:54 ` Masahiro Yamada
0 siblings, 1 reply; 12+ messages in thread
From: Mark Rutland @ 2015-11-24 11:50 UTC (permalink / raw)
To: Masahiro Yamada
Cc: arm, devicetree, Kumar Gala, linux-kernel, Ian Campbell,
Rob Herring, Pawel Moll, linux-arm-kernel
On Tue, Nov 24, 2015 at 06:39:19PM +0900, Masahiro Yamada wrote:
> The UniPhier System Bus is an external bus where on-board devices are
> connected to the UniPhier SoC. This driver parses the "ranges"
> property of the System Bus and set up the registers of the System Bus
> Controller for the correct bus routing.
Could you elaborate on why you need to do that?
What needs to be configured specifically?
[...]
> +The UniPhier System Bus is an external bus where on-board devices are connected
> +to the UniPhier SoC. It it a simple parallel bus with address, data, and some
> +control signals. It supports up to 8 banks (chip selects).
> +
> +Required properties for System Bus:
> +- compatible: should be "socionext,uniphier-system-bus", "simple-bus".
If the kernel has to perform setup of the bus, then it is not a
"simple-bus".
Configure the bus, then probe children. Don't use simple-bus jsut to get
probing.
> +- #address-cells: should be equal to or grater than 2. The first cell is the
s/grater/greater/
> + bank number (chip select). The rest is the base address within the bank that
> + should be mapped onto the parent bus (usually AMBA).
> +
> +Optional properties for System Bus:
> +- #size-cells: should be the same as that of the parent bus, if exists. The
> + value of the parent bus is assumed, if not specified.
This should be just as required as #address-cells, for consistency.
> +
> +
> +UniPhier System Bus Controller
> +------------------------------
> +
> +The UniPhier System Bus Controller is a hardware block with registers that
> +controls the System Bus accessing; how each bank is mapped onto the parent bus,
> +various timing parameters of the bus access, etc.
> +
> +Required properties for System Bus Controller:
> +- compatible: should be "socionext,uniphier-system-bus-controller".
> +- reg: offsets and lengths of the register sets for the device. It should
> + contain 2 regions: base & control register, misc register, in this order.
The example also has a system-bus phandle.
Is the "misc register" part of the bus controller, or is it a shared
system controller?
> +Example
> +-------
> + system_bus: system-bus {
> + compatible = "socionext,uniphier-system-bus", "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <1 0x00000000 0x42000000 0x02000000
> + 5 0x00000000 0x48000000 0x01000000>;
> +
> + eth: ethernet@1,01f00000 {
> + compatible = "smsc,lan9115";
> + reg = <1 0x01f00000 0x1000>;
> + phy-mode = "mii";
> + reg-io-width = <4>;
> + };
> +
> + serial: uart@5,00200000 {
> + compatible = "ns16550a";
> + reg = <5 0x00200000 0x20>;
> + clock-frequency = <12288000>;
> + reg-shift = <1>;
> + };
> + };
> +
> + system-bus-controller@58c00000 {
> + compatible = "socionext,uniphier-system-bus-controller";
> + reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
> + system-bus = <&system_bus>;
> + };
Assuming that the controller and bus are 1-1 related, make this a single
node. e.g.
system-bus {
compatible = "socionext,uniphier-system-bus";
reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0x00000000 0x42000000 0x02000000>,
<5 0x00000000 0x48000000 0x01000000>;
...
child nodes here
...
};
[...]
> +static int uniphier_sbc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct uniphier_sbc_priv *priv;
> + struct resource *regs;
> + struct device_node *bus_np;
> + int child_addrc, addrc, sizec, bank;
> + u64 child_addr, addr, size;
> + const __be32 *ranges;
> + int rlen, rone, ret;
> +
> + bus_np = of_find_compatible_node(NULL, NULL,
> + "socionext,uniphier-system-bus");
This is broken if you ever have multiple instances.
Either use a single node, or if there is a more complex relationship
between busses and their controllers, describe that explicitly with
phandles.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/4] bus: uniphier-system-bus: add UniPhier System Bus Controller driver
2015-11-24 11:50 ` Mark Rutland
@ 2015-11-24 16:54 ` Masahiro Yamada
[not found] ` <CAK7LNAR_6qwVK9fNEAX-L_v1Z5cdGMU33bP75Rdtu5bdmid-3Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: Masahiro Yamada @ 2015-11-24 16:54 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree, Pawel Moll, Ian Campbell, Linux Kernel Mailing List,
Rob Herring, arm, Kumar Gala, linux-arm-kernel
Hi Mark,
2015-11-24 20:50 GMT+09:00 Mark Rutland <mark.rutland@arm.com>:
> On Tue, Nov 24, 2015 at 06:39:19PM +0900, Masahiro Yamada wrote:
>> The UniPhier System Bus is an external bus where on-board devices are
>> connected to the UniPhier SoC. This driver parses the "ranges"
>> property of the System Bus and set up the registers of the System Bus
>> Controller for the correct bus routing.
>
> Could you elaborate on why you need to do that?
In order to have access to the System Bus (external bus),
the System Bus Controller must be set up.
> What needs to be configured specifically?
The base address and the size of each bank (each chip select)
must be set to the registers of the controller.
> [...]
>
>> +The UniPhier System Bus is an external bus where on-board devices are connected
>> +to the UniPhier SoC. It it a simple parallel bus with address, data, and some
>> +control signals. It supports up to 8 banks (chip selects).
>> +
>> +Required properties for System Bus:
>> +- compatible: should be "socionext,uniphier-system-bus", "simple-bus".
>
> If the kernel has to perform setup of the bus, then it is not a
> "simple-bus".
>
> Configure the bus, then probe children. Don't use simple-bus jsut to get
> probing.
OK, I will fix in v2.
>> +- #address-cells: should be equal to or grater than 2. The first cell is the
>
> s/grater/greater/
OK, thanks.
>> + bank number (chip select). The rest is the base address within the bank that
>> + should be mapped onto the parent bus (usually AMBA).
>> +
>> +Optional properties for System Bus:
>> +- #size-cells: should be the same as that of the parent bus, if exists. The
>> + value of the parent bus is assumed, if not specified.
>
> This should be just as required as #address-cells, for consistency.
Will fix.
>> +
>> +
>> +UniPhier System Bus Controller
>> +------------------------------
>> +
>> +The UniPhier System Bus Controller is a hardware block with registers that
>> +controls the System Bus accessing; how each bank is mapped onto the parent bus,
>> +various timing parameters of the bus access, etc.
>> +
>> +Required properties for System Bus Controller:
>> +- compatible: should be "socionext,uniphier-system-bus-controller".
>> +- reg: offsets and lengths of the register sets for the device. It should
>> + contain 2 regions: base & control register, misc register, in this order.
>
> The example also has a system-bus phandle.
Actually, I was wondering which is better to describe the relation between
the bus and the controller, phandle or compatible string..
> Is the "misc register" part of the bus controller, or is it a shared
> system controller?
It is a part of the bus controller, but used for another purpose.
(i.e. partly this is syscon. I know this is strange, but it is
what the hardware developers designed.)
>> +Example
>> +-------
>> + system_bus: system-bus {
>> + compatible = "socionext,uniphier-system-bus", "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + ranges = <1 0x00000000 0x42000000 0x02000000
>> + 5 0x00000000 0x48000000 0x01000000>;
>> +
>> + eth: ethernet@1,01f00000 {
>> + compatible = "smsc,lan9115";
>> + reg = <1 0x01f00000 0x1000>;
>> + phy-mode = "mii";
>> + reg-io-width = <4>;
>> + };
>> +
>> + serial: uart@5,00200000 {
>> + compatible = "ns16550a";
>> + reg = <5 0x00200000 0x20>;
>> + clock-frequency = <12288000>;
>> + reg-shift = <1>;
>> + };
>> + };
>> +
>> + system-bus-controller@58c00000 {
>> + compatible = "socionext,uniphier-system-bus-controller";
>> + reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
>> + system-bus = <&system_bus>;
>> + };
>
> Assuming that the controller and bus are 1-1 related, make this a single
> node. e.g.
>
> system-bus {
> compatible = "socionext,uniphier-system-bus";
> reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
> #address-cells = <2>;
> #size-cells = <1>;
> ranges = <1 0x00000000 0x42000000 0x02000000>,
> <5 0x00000000 0x48000000 0x01000000>;
>
> ...
> child nodes here
> ...
>
> };
Hmm, make sense. But, I prefer to reflect the hardware structure.
The range of System Bus is <0x40000000 0x10000000>.
The register of the System Bus Controller is
<0x58c00000 0x400> (and <0x59800000 0x2000>)
The bus and its controller is different.
> [...]
>
>> +static int uniphier_sbc_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct uniphier_sbc_priv *priv;
>> + struct resource *regs;
>> + struct device_node *bus_np;
>> + int child_addrc, addrc, sizec, bank;
>> + u64 child_addr, addr, size;
>> + const __be32 *ranges;
>> + int rlen, rone, ret;
>> +
>> + bus_np = of_find_compatible_node(NULL, NULL,
>> + "socionext,uniphier-system-bus");
>
> This is broken if you ever have multiple instances.
>
> Either use a single node, or if there is a more complex relationship
> between busses and their controllers, describe that explicitly with
> phandles.
Probably, I will stick to phandle in v2.
Thanks,
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/4] ARM: dts: uniphier: add better-matching compatible string to extbus nodes
2015-11-24 9:39 [PATCH 0/4] arm,arm64: uniphier: add a new driver, device tree updates Masahiro Yamada
2015-11-24 9:39 ` [PATCH 1/4] bus: uniphier-system-bus: add UniPhier System Bus Controller driver Masahiro Yamada
@ 2015-11-24 9:39 ` Masahiro Yamada
2015-11-24 9:39 ` [PATCH 3/4] ARM: dts: uniphier: rename nodes from extbus to system-bus Masahiro Yamada
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Masahiro Yamada @ 2015-11-24 9:39 UTC (permalink / raw)
To: arm
Cc: Masahiro Yamada, Russell King, devicetree, Kumar Gala,
linux-kernel, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland,
linux-arm-kernel
This is needed to use the UniPhier System Controller driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-ph1-ld4.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-ph1-pro4.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-ph1-pro5.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-ph1-sld3.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-ph1-sld8.dtsi | 3 ++-
arch/arm/boot/dts/uniphier-proxstream2.dtsi | 3 ++-
6 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
index af49381..c2913fe 100644
--- a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
@@ -87,7 +87,8 @@
interrupt-parent = <&intc>;
extbus: extbus {
- compatible = "simple-bus";
+ compatible = "socionext,uniphier-system-bus",
+ "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
index 254642f..d110df7 100644
--- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
@@ -95,7 +95,8 @@
interrupt-parent = <&intc>;
extbus: extbus {
- compatible = "simple-bus";
+ compatible = "socionext,uniphier-system-bus",
+ "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
index 11eb762..0f1db60 100644
--- a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
@@ -95,7 +95,8 @@
interrupt-parent = <&intc>;
extbus: extbus {
- compatible = "simple-bus";
+ compatible = "socionext,uniphier-system-bus",
+ "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
index 691a17d..888bb2e 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
@@ -95,7 +95,8 @@
interrupt-parent = <&intc>;
extbus: extbus {
- compatible = "simple-bus";
+ compatible = "socionext,uniphier-system-bus",
+ "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
index e88559b..b10c4bd 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
@@ -87,7 +87,8 @@
interrupt-parent = <&intc>;
extbus: extbus {
- compatible = "simple-bus";
+ compatible = "socionext,uniphier-system-bus",
+ "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index 259f1a9..9186f8c9 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -109,7 +109,8 @@
interrupt-parent = <&intc>;
extbus: extbus {
- compatible = "simple-bus";
+ compatible = "socionext,uniphier-system-bus",
+ "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/4] ARM: dts: uniphier: rename nodes from extbus to system-bus
2015-11-24 9:39 [PATCH 0/4] arm,arm64: uniphier: add a new driver, device tree updates Masahiro Yamada
2015-11-24 9:39 ` [PATCH 1/4] bus: uniphier-system-bus: add UniPhier System Bus Controller driver Masahiro Yamada
2015-11-24 9:39 ` [PATCH 2/4] ARM: dts: uniphier: add better-matching compatible string to extbus nodes Masahiro Yamada
@ 2015-11-24 9:39 ` Masahiro Yamada
2015-11-24 9:39 ` [PATCH 4/4] arm64: dts: uniphier: add PH1-LD10 SoC/board support Masahiro Yamada
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Masahiro Yamada @ 2015-11-24 9:39 UTC (permalink / raw)
To: arm
Cc: Masahiro Yamada, Russell King, devicetree, Kumar Gala,
linux-kernel, Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland,
linux-arm-kernel
The officially documented name for this hardware is System Bus, so
follow that naming. It also corresponds to the compatible string.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts | 2 +-
arch/arm/boot/dts/uniphier-ph1-ld4.dtsi | 2 +-
arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts | 2 +-
arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts | 2 +-
arch/arm/boot/dts/uniphier-ph1-pro4.dtsi | 2 +-
arch/arm/boot/dts/uniphier-ph1-pro5.dtsi | 2 +-
arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts | 2 +-
arch/arm/boot/dts/uniphier-ph1-sld3.dtsi | 2 +-
arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts | 2 +-
arch/arm/boot/dts/uniphier-ph1-sld8.dtsi | 2 +-
arch/arm/boot/dts/uniphier-proxstream2.dtsi | 2 +-
arch/arm/boot/dts/uniphier-support-card.dtsi | 2 +-
12 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts
index f1e9d40..c625b4d 100644
--- a/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts
@@ -72,7 +72,7 @@
};
};
-&extbus {
+&system_bus {
ranges = <1 0x00000000 0x42000000 0x02000000>;
};
diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
index c2913fe..0e2ba55 100644
--- a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
@@ -86,7 +86,7 @@
ranges;
interrupt-parent = <&intc>;
- extbus: extbus {
+ system_bus: system-bus {
compatible = "socionext,uniphier-system-bus",
"simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts
index 5baa9fc..3ac89fb 100644
--- a/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts
@@ -74,7 +74,7 @@
};
};
-&extbus {
+&system_bus {
ranges = <1 0x00000000 0x42000000 0x02000000>;
};
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts
index 2462668..0c82353 100644
--- a/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts
@@ -74,7 +74,7 @@
};
};
-&extbus {
+&system_bus {
ranges = <1 0x00000000 0x42000000 0x02000000>;
};
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
index d110df7..09f78fa 100644
--- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
@@ -94,7 +94,7 @@
ranges;
interrupt-parent = <&intc>;
- extbus: extbus {
+ system_bus: system-bus {
compatible = "socionext,uniphier-system-bus",
"simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
index 0f1db60..f5aa24c 100644
--- a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
@@ -94,7 +94,7 @@
ranges;
interrupt-parent = <&intc>;
- extbus: extbus {
+ system_bus: system-bus {
compatible = "socionext,uniphier-system-bus",
"simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts
index b7a03215..29e8123 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts
@@ -73,7 +73,7 @@
};
};
-&extbus {
+&system_bus {
ranges = <1 0x00000000 0x42000000 0x02000000>;
};
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
index 888bb2e..d830ea9 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
@@ -94,7 +94,7 @@
ranges;
interrupt-parent = <&intc>;
- extbus: extbus {
+ system_bus: system-bus {
compatible = "socionext,uniphier-system-bus",
"simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts
index fc7250c..eb605d6 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts
@@ -72,7 +72,7 @@
};
};
-&extbus {
+&system_bus {
ranges = <1 0x00000000 0x42000000 0x02000000>;
};
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
index b10c4bd..711a3f7 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
@@ -86,7 +86,7 @@
ranges;
interrupt-parent = <&intc>;
- extbus: extbus {
+ system_bus: system-bus {
compatible = "socionext,uniphier-system-bus",
"simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index 9186f8c9..ff4977c 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -108,7 +108,7 @@
ranges;
interrupt-parent = <&intc>;
- extbus: extbus {
+ system_bus: system-bus {
compatible = "socionext,uniphier-system-bus",
"simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi
index da271e3..e8c9b49 100644
--- a/arch/arm/boot/dts/uniphier-support-card.dtsi
+++ b/arch/arm/boot/dts/uniphier-support-card.dtsi
@@ -42,7 +42,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-&extbus {
+&system_bus {
support_card: support_card {
compatible = "simple-bus";
#address-cells = <1>;
--
1.9.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 4/4] arm64: dts: uniphier: add PH1-LD10 SoC/board support
2015-11-24 9:39 [PATCH 0/4] arm,arm64: uniphier: add a new driver, device tree updates Masahiro Yamada
` (2 preceding siblings ...)
2015-11-24 9:39 ` [PATCH 3/4] ARM: dts: uniphier: rename nodes from extbus to system-bus Masahiro Yamada
@ 2015-11-24 9:39 ` Masahiro Yamada
2015-11-26 2:30 ` [PATCH 0/4] arm, arm64: uniphier: add a new driver, device tree updates Masahiro Yamada
2015-12-12 0:12 ` [PATCH 0/4] arm,arm64: " Arnd Bergmann
5 siblings, 0 replies; 12+ messages in thread
From: Masahiro Yamada @ 2015-11-24 9:39 UTC (permalink / raw)
To: arm
Cc: Masahiro Yamada, devicetree, Kumar Gala, linux-kernel,
Ian Campbell, Rob Herring, Pawel Moll, Will Deacon, Mark Rutland,
Catalin Marinas, linux-arm-kernel
This is the first ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/socionext/Makefile | 4 +
.../boot/dts/socionext/uniphier-ph1-ld10-ref.dts | 95 +++++++
.../boot/dts/socionext/uniphier-ph1-ld10.dtsi | 286 +++++++++++++++++++++
.../arm64/boot/dts/socionext/uniphier-pinctrl.dtsi | 1 +
.../boot/dts/socionext/uniphier-support-card.dtsi | 1 +
7 files changed, 389 insertions(+)
create mode 100644 arch/arm64/boot/dts/socionext/Makefile
create mode 100644 arch/arm64/boot/dts/socionext/uniphier-ph1-ld10-ref.dts
create mode 100644 arch/arm64/boot/dts/socionext/uniphier-ph1-ld10.dtsi
create mode 120000 arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi
create mode 120000 arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index e849a38..096b2b0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1642,6 +1642,7 @@ F: arch/arm/boot/dts/uniphier*
F: arch/arm/include/asm/hardware/cache-uniphier.h
F: arch/arm/mach-uniphier/
F: arch/arm/mm/cache-uniphier.c
+F: arch/arm64/boot/dts/socionext/
F: drivers/bus/uniphier-system-bus.c
F: drivers/i2c/busses/i2c-uniphier*
F: drivers/pinctrl/uniphier/
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index eb3c42d..6672a96 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -11,6 +11,7 @@ dts-dirs += marvell
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += rockchip
+dts-dirs += socionext
dts-dirs += sprd
dts-dirs += xilinx
diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile
new file mode 100644
index 0000000..8d72771
--- /dev/null
+++ b/arch/arm64/boot/dts/socionext/Makefile
@@ -0,0 +1,4 @@
+dtb-$(CONFIG_ARCH_UNIPHIER) += uniphier-ph1-ld10-ref.dtb
+
+always := $(dtb-y)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10-ref.dts
new file mode 100644
index 0000000..7b36be4
--- /dev/null
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10-ref.dts
@@ -0,0 +1,95 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD10 Reference Board
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-ld10.dtsi"
+/include/ "uniphier-support-card.dtsi"
+
+/ {
+ model = "UniPhier PH1-LD10 Reference Board";
+ compatible = "socionext,ph1-ld10-ref", "socionext,ph1-ld10";
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0xc0000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&system_bus {
+ ranges = <1 0x00000000 0x42000000 0x02000000>;
+};
+
+&support_card {
+ ranges = <0x00000000 1 0x01f00000 0x00100000>;
+};
+
+ðsc {
+ interrupts = <0 48 4>;
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10.dtsi
new file mode 100644
index 0000000..b899e54
--- /dev/null
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10.dtsi
@@ -0,0 +1,286 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD10 SoC
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+ compatible = "socionext,ph1-ld10";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x80000100>;
+ };
+ };
+
+ clocks {
+ uart_clk: uart_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <58820000>;
+ };
+
+ i2c_clk: i2c_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xf01>,
+ <1 14 0xf01>,
+ <1 11 0xf01>,
+ <1 10 0xf01>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ system_bus: system-bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ interrupts = <0 33 4>;
+ clocks = <&uart_clk>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ interrupts = <0 35 4>;
+ clocks = <&uart_clk>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ interrupts = <0 37 4>;
+ clocks = <&uart_clk>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ interrupts = <0 177 4>;
+ clocks = <&uart_clk>;
+ };
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ interrupts = <0 41 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ interrupts = <0 42 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ interrupts = <0 43 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ interrupts = <0 44 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
+
+ system-bus-controller@58c00000 {
+ compatible = "socionext,uniphier-system-bus-controller";
+ reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
+ system-bus = <&system_bus>;
+ };
+
+ pinctrl: pinctrl@5f801000 {
+ compatible = "socionext,ph1-ld10-pinctrl", "syscon";
+ reg = <0x5f801000 0xe00>;
+ };
+
+ gic: interrupt-controller@5fe00000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x5fe00000 0x10000>, /* GICD */
+ <0x5fe80000 0x80000>; /* GICR */
+ interrupts = <1 9 4>;
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi
new file mode 120000
index 0000000..f42fb6f
--- /dev/null
+++ b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi
@@ -0,0 +1 @@
+../../../../arm/boot/dts/uniphier-pinctrl.dtsi
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi
new file mode 120000
index 0000000..1246db9
--- /dev/null
+++ b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi
@@ -0,0 +1 @@
+../../../../arm/boot/dts/uniphier-support-card.dtsi
\ No newline at end of file
--
1.9.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 0/4] arm, arm64: uniphier: add a new driver, device tree updates
2015-11-24 9:39 [PATCH 0/4] arm,arm64: uniphier: add a new driver, device tree updates Masahiro Yamada
` (3 preceding siblings ...)
2015-11-24 9:39 ` [PATCH 4/4] arm64: dts: uniphier: add PH1-LD10 SoC/board support Masahiro Yamada
@ 2015-11-26 2:30 ` Masahiro Yamada
2015-12-12 0:12 ` [PATCH 0/4] arm,arm64: " Arnd Bergmann
5 siblings, 0 replies; 12+ messages in thread
From: Masahiro Yamada @ 2015-11-26 2:30 UTC (permalink / raw)
To: arm
Cc: Mark Rutland, devicetree, Russell King, Pawel Moll, Ian Campbell,
Catalin Marinas, Will Deacon, Linux Kernel Mailing List,
Masahiro Yamada, Rob Herring, Kumar Gala, linux-arm-kernel
2015-11-24 18:39 GMT+09:00 Masahiro Yamada <yamada.masahiro@socionext.com>:
> Hi Arnd, Olof,
>
> Here is another series for UniPhier SoC family:
>
> - 1/4: add a new driver. The UniPhier System Bus is an external bus
> where on-board devices are connected to the SoC.
> (please check if the binding specification is OK.)
>
> - 2/4: device tree updates to use the driver added by 1/4
>
> - 3/4: trivial rename of device node names
>
> - 4/4: initial commit for ARMv8 SoC/Board device trees
>
> Please apply 2/4, 3/4/, 4/4 into the same branch because 4/4 depends on 2/4 and 3/4.
> (4/4 creates symbolic links to ARM device trees.)
It looks like 1/4 will take longer, so want to postpone it for now.
I will resend 4/4 as a single patch.
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 0/4] arm,arm64: uniphier: add a new driver, device tree updates
2015-11-24 9:39 [PATCH 0/4] arm,arm64: uniphier: add a new driver, device tree updates Masahiro Yamada
` (4 preceding siblings ...)
2015-11-26 2:30 ` [PATCH 0/4] arm, arm64: uniphier: add a new driver, device tree updates Masahiro Yamada
@ 2015-12-12 0:12 ` Arnd Bergmann
2015-12-12 6:57 ` Masahiro Yamada
5 siblings, 1 reply; 12+ messages in thread
From: Arnd Bergmann @ 2015-12-12 0:12 UTC (permalink / raw)
To: Masahiro Yamada
Cc: arm, devicetree, Kumar Gala, linux-kernel, Ian Campbell,
Rob Herring, Pawel Moll, Will Deacon, Mark Rutland, Russell King,
Catalin Marinas, linux-arm-kernel
On Tuesday 24 November 2015 18:39:18 Masahiro Yamada wrote:
>
> Here is another series for UniPhier SoC family:
>
> - 1/4: add a new driver. The UniPhier System Bus is an external bus
> where on-board devices are connected to the SoC.
> (please check if the binding specification is OK.)
>
> - 2/4: device tree updates to use the driver added by 1/4
>
> - 3/4: trivial rename of device node names
>
> - 4/4: initial commit for ARMv8 SoC/Board device trees
>
> Please apply 2/4, 3/4/, 4/4 into the same branch because 4/4 depends on 2/4 and 3/4.
> (4/4 creates symbolic links to ARM device trees.)
I'm a bit confused how this relates to the newer version ("[PATCH v5] bus:
uniphier-system-bus: add UniPhier System Bus driver"). The new version
only has one patch instead of four, so I'm not sure if the patches 2, 3
and 4 of this series still apply.
Can you clarify, or send the entire series again?
Arnd
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 0/4] arm,arm64: uniphier: add a new driver, device tree updates
2015-12-12 0:12 ` [PATCH 0/4] arm,arm64: " Arnd Bergmann
@ 2015-12-12 6:57 ` Masahiro Yamada
0 siblings, 0 replies; 12+ messages in thread
From: Masahiro Yamada @ 2015-12-12 6:57 UTC (permalink / raw)
To: Arnd Bergmann
Cc: arm, devicetree, Kumar Gala, Linux Kernel Mailing List,
Ian Campbell, Rob Herring, Pawel Moll, Will Deacon, Mark Rutland,
Russell King, Catalin Marinas, linux-arm-kernel
Hi Arnd,
Sorry for confusing you.
2015-12-12 9:12 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
> On Tuesday 24 November 2015 18:39:18 Masahiro Yamada wrote:
>>
>> Here is another series for UniPhier SoC family:
>>
>> - 1/4: add a new driver. The UniPhier System Bus is an external bus
>> where on-board devices are connected to the SoC.
>> (please check if the binding specification is OK.)
>>
>> - 2/4: device tree updates to use the driver added by 1/4
>>
>> - 3/4: trivial rename of device node names
>>
>> - 4/4: initial commit for ARMv8 SoC/Board device trees
>>
>> Please apply 2/4, 3/4/, 4/4 into the same branch because 4/4 depends on 2/4 and 3/4.
>> (4/4 creates symbolic links to ARM device trees.)
>
> I'm a bit confused how this relates to the newer version ("[PATCH v5] bus:
> uniphier-system-bus: add UniPhier System Bus driver"). The new version
> only has one patch instead of four, so I'm not sure if the patches 2, 3
> and 4 of this series still apply.
>
> Can you clarify, or send the entire series again?
>
> Arnd
I'd like to retract this series.
Please just disregard it.
Instead, please review this one:
https://patchwork.kernel.org/patch/7714151/
Thanks!
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 12+ messages in thread