[PATCH 00/12] arm64: dts: hi3660: add device nodes

[PATCH 00/12] arm64: dts: hi3660: add device nodes

[Guodong Xu]

This patchset adds various devices nodes for hi3660 and hikey960.

HiKey960 is one of 96boards. For details information about it, please
refer to [1].

[1] https://github.com/96boards/documentation/tree/master/ConsumerEdition/HiKey960

Chen Feng (2):
  arm64: dts: hi3660: Add uarts nodes
  arm64: dts: hi3660: Add pl031 rtc node

Chen Jun (1):
  arm64: dts: hi3660: add power key dts node

Guodong Xu (4):
  dt-bindings: arm: hisilicon: add bindings for HiKey960 board
  arm64: dts: hisilicon: update compatible string for hikey960
  arm64: dts: hikey960: add WL1837 Bluetooth device node
  arm64: dts: hikey960: add LED nodes

Wang Xiaoyin (3):
  arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig
  arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC
  arm64: dts: hi3660: add spi device nodes

Zhangfei Gao (2):
  arm64: dts: hi3660: add resources for clock and reset
  arm64: dts: Add I2C nodes for Hi3660

 .../bindings/arm/hisilicon/hisilicon.txt           |   4 +
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts  | 122 +++-
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi          | 616 +++++++++++++++-
 .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 779 +++++++++++++++++++--
 4 files changed, 1448 insertions(+), 73 deletions(-)

-- 
2.10.2

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[PATCH 02/12] arm64: dts: hisilicon: update compatible string for hikey960

[Guodong Xu]

Update compatible string for hikey960. HiKey960 is a develpment board built
with SoC Hi3660.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 186251f..64875a5 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -12,7 +12,7 @@
 
 / {
 	model = "HiKey960";
-	compatible = "hisilicon,hi3660";
+	compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
 
 	aliases {
 		serial5 = &uart5;       /* console UART */
-- 
2.10.2

Re: [PATCH 02/12] arm64: dts: hisilicon: update compatible string for hikey960

[Rob Herring]

On Wed, May 17, 2017 at 04:37:35PM +0800, Guodong Xu wrote:
> Update compatible string for hikey960. HiKey960 is a develpment board built
> with SoC Hi3660.
> 
> Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> 
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[PATCH 03/12] arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig

[Guodong Xu]

From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>

This commit adds more pinmux and pinctrl information for devices
on HiKey960, including i2c, spi, cam, uart, ufs, pcie, csi, pwr_key,
isp, sd/sdio, i2s, and usb.

Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
 .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 779 +++++++++++++++++++--
 1 file changed, 719 insertions(+), 60 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi
index 719c4bc..b52a687 100644
--- a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi
@@ -24,6 +24,27 @@
 				&range 0 7 0
 				&range 8 116 0>;
 
+			pmu_pmx_func: pmu_pmx_func {
+				pinctrl-single,pins = <
+					0x008 MUX_M1 /* PMU1_SSI */
+					0x00c MUX_M1 /* PMU2_SSI */
+					0x010 MUX_M1 /* PMU_CLKOUT */
+					0x100 MUX_M1 /* PMU_HKADC_SSI */
+				>;
+			};
+
+			csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {
+				pinctrl-single,pins = <
+					0x044 MUX_M0 /* CSI0_PWD_N */
+				>;
+			};
+
+			csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {
+				pinctrl-single,pins = <
+					0x04c MUX_M0 /* CSI1_PWD_N */
+				>;
+			};
+
 			isp0_pmx_func: isp0_pmx_func {
 				pinctrl-single,pins = <
 					0x058 MUX_M1 /* ISP_CLK0 */
@@ -40,6 +61,12 @@
 				>;
 			};
 
+			pwr_key_pmx_func: pwr_key_pmx_func {
+				pinctrl-single,pins = <
+					0x080 MUX_M0 /* GPIO_034 */
+				>;
+			};
+
 			i2c3_pmx_func: i2c3_pmx_func {
 				pinctrl-single,pins = <
 					0x02c MUX_M1 /* I2C3_SCL */
@@ -67,21 +94,10 @@
 				>;
 			};
 
-			spi1_pmx_func: spi1_pmx_func {
-				pinctrl-single,pins = <
-					0x034 MUX_M1 /* SPI1_CLK */
-					0x038 MUX_M1 /* SPI1_DI */
-					0x03c MUX_M1 /* SPI1_DO */
-					0x040 MUX_M1 /* SPI1_CS_N */
-				>;
-			};
-
 			uart0_pmx_func: uart0_pmx_func {
 				pinctrl-single,pins = <
 					0x0cc MUX_M2 /* UART0_RXD */
 					0x0d0 MUX_M2 /* UART0_TXD */
-					0x0d4 MUX_M2 /* UART0_RXD_M */
-					0x0d8 MUX_M2 /* UART0_TXD_M */
 				>;
 			};
 
@@ -138,6 +154,18 @@
 					0x0d8 MUX_M1 /* UART6_TXD */
 				>;
 			};
+
+			cam0_rst_pmx_func: cam0_rst_pmx_func {
+				pinctrl-single,pins = <
+					0x0c8 MUX_M0 /* CAM0_RST */
+				>;
+			};
+
+			cam1_rst_pmx_func: cam1_rst_pmx_func {
+				pinctrl-single,pins = <
+					0x124 MUX_M0 /* CAM1_RST */
+				>;
+			};
 		};
 
 		/* [IOMG_MMC0_000, IOMG_MMC0_005] */
@@ -174,6 +202,13 @@
 			/* pin base, nr pins & gpio function */
 			pinctrl-single,gpio-range = <&range 0 12 0>;
 
+			ufs_pmx_func: ufs_pmx_func {
+				pinctrl-single,pins = <
+					0x000 MUX_M1 /* UFS_REF_CLK */
+					0x004 MUX_M1 /* UFS_RST_N */
+				>;
+			};
+
 			spi3_pmx_func: spi3_pmx_func {
 				pinctrl-single,pins = <
 					0x008 MUX_M1 /* SPI3_CLK */
@@ -248,17 +283,17 @@
 				>;
 			};
 
-			i2c2_pmx_func: i2c2_pmx_func {
+			i2c7_pmx_func: i2c7_pmx_func {
 				pinctrl-single,pins = <
-					0x024 MUX_M1 /* I2C2_SCL */
-					0x028 MUX_M1 /* I2C2_SDA */
+					0x024 MUX_M3 /* I2C7_SCL */
+					0x028 MUX_M3 /* I2C7_SDA */
 				>;
 			};
 
-			i2c7_pmx_func: i2c7_pmx_func {
+			pcie_pmx_func: pcie_pmx_func {
 				pinctrl-single,pins = <
-					0x024 MUX_M3 /* I2C7_SCL */
-					0x028 MUX_M3 /* I2C7_SDA */
+					0x084 MUX_M1 /* PCIE_CLKREQ_N */
+					0x088 MUX_M1 /* PCIE_WAKE_N */
 				>;
 			};
 
@@ -271,15 +306,6 @@
 				>;
 			};
 
-			spi4_pmx_func: spi4_pmx_func {
-				pinctrl-single,pins = <
-					0x08c MUX_M4 /* SPI4_CLK */
-					0x090 MUX_M4 /* SPI4_DI */
-					0x094 MUX_M4 /* SPI4_DO */
-					0x098 MUX_M4 /* SPI4_CS0_N */
-				>;
-			};
-
 			i2s0_pmx_func: i2s0_pmx_func {
 				pinctrl-single,pins = <
 					0x034 MUX_M1 /* I2S0_DI */
@@ -290,17 +316,20 @@
 			};
 		};
 
-		pmx5: pinmux@ff3fd800 {
+		pmx5: pinmux@e896c800 {
 			compatible = "pinconf-single";
-			reg = <0x0 0xff3fd800 0x0 0x18>;
+			reg = <0x0 0xe896c800 0x0 0x200>;
 			#pinctrl-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			pinctrl-single,register-width = <32>;
 
-			sdio_clk_cfg_func: sdio_clk_cfg_func {
+			pmu_cfg_func: pmu_cfg_func {
 				pinctrl-single,pins = <
-					0x000 0x0 /* SDIO_CLK */
+					0x010 0x0 /* PMU1_SSI */
+					0x014 0x0 /* PMU2_SSI */
+					0x018 0x0 /* PMU_CLKOUT */
+					0x10c 0x0 /* PMU_HKADC_SSI */
 				>;
 				pinctrl-single,bias-pulldown = <
 					PULL_DIS
@@ -315,18 +344,35 @@
 					PULL_UP
 				>;
 				pinctrl-single,drive-strength = <
-					DRIVE6_32MA
-					DRIVE6_MASK
+					DRIVE7_06MA DRIVE6_MASK
 				>;
 			};
 
-			sdio_cfg_func: sdio_cfg_func {
+			i2c3_cfg_func: i2c3_cfg_func {
 				pinctrl-single,pins = <
-					0x004 0x0 /* SDIO_CMD */
-					0x008 0x0 /* SDIO_DATA0 */
-					0x00c 0x0 /* SDIO_DATA1 */
-					0x010 0x0 /* SDIO_DATA2 */
-					0x014 0x0 /* SDIO_DATA3 */
+					0x038 0x0 /* I2C3_SCL */
+					0x03c 0x0 /* I2C3_SDA */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {
+				pinctrl-single,pins = <
+					0x050 0x0 /* CSI0_PWD_N */
 				>;
 				pinctrl-single,bias-pulldown = <
 					PULL_DIS
@@ -335,29 +381,64 @@
 					PULL_DOWN
 				>;
 				pinctrl-single,bias-pullup = <
+					PULL_DIS
 					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_04MA DRIVE6_MASK
+				>;
+			};
+
+			csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {
+				pinctrl-single,pins = <
+					0x058 0x0 /* CSI1_PWD_N */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
 					PULL_UP
 					PULL_DIS
 					PULL_UP
 				>;
 				pinctrl-single,drive-strength = <
-					DRIVE6_19MA
-					DRIVE6_MASK
+					DRIVE7_04MA DRIVE6_MASK
 				>;
 			};
-		};
 
-		pmx6: pinmux@ff37e800 {
-			compatible = "pinconf-single";
-			reg = <0x0 0xff37e800 0x0 0x18>;
-			#pinctrl-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			pinctrl-single,register-width = <32>;
+			isp0_cfg_func: isp0_cfg_func {
+				pinctrl-single,pins = <
+					0x064 0x0 /* ISP_CLK0 */
+					0x070 0x0 /* ISP_SCL0 */
+					0x074 0x0 /* ISP_SDA0 */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_04MA DRIVE6_MASK>;
+			};
 
-			sd_clk_cfg_func: sd_clk_cfg_func {
+			isp1_cfg_func: isp1_cfg_func {
 				pinctrl-single,pins = <
-					0x000 0x0 /* SD_CLK */
+					0x068 0x0 /* ISP_CLK1 */
+					0x078 0x0 /* ISP_SCL1 */
+					0x07c 0x0 /* ISP_SDA1 */
 				>;
 				pinctrl-single,bias-pulldown = <
 					PULL_DIS
@@ -372,18 +453,61 @@
 					PULL_UP
 				>;
 				pinctrl-single,drive-strength = <
-					DRIVE6_32MA
-					DRIVE6_MASK
+					DRIVE7_04MA DRIVE6_MASK
 				>;
 			};
 
-			sd_cfg_func: sd_cfg_func {
+			pwr_key_cfg_func: pwr_key_cfg_func {
 				pinctrl-single,pins = <
-					0x004 0x0 /* SD_CMD */
-					0x008 0x0 /* SD_DATA0 */
-					0x00c 0x0 /* SD_DATA1 */
-					0x010 0x0 /* SD_DATA2 */
-					0x014 0x0 /* SD_DATA3 */
+					0x08c 0x0 /* GPIO_034 */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			uart1_cfg_func: uart1_cfg_func {
+				pinctrl-single,pins = <
+					0x0b4 0x0 /* UART1_RXD */
+					0x0b8 0x0 /* UART1_TXD */
+					0x0bc 0x0 /* UART1_CTS_N */
+					0x0c0 0x0 /* UART1_RTS_N */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			uart2_cfg_func: uart2_cfg_func {
+				pinctrl-single,pins = <
+					0x0c8 0x0 /* UART2_CTS_N */
+					0x0cc 0x0 /* UART2_RTS_N */
+					0x0d0 0x0 /* UART2_TXD */
+					0x0d4 0x0 /* UART2_RXD */
 				>;
 				pinctrl-single,bias-pulldown = <
 					PULL_DIS
@@ -392,14 +516,549 @@
 					PULL_DOWN
 				>;
 				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
 					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			uart5_cfg_func: uart5_cfg_func {
+				pinctrl-single,pins = <
+					0x0c8 0x0 /* UART5_RXD */
+					0x0cc 0x0 /* UART5_TXD */
+					0x0d0 0x0 /* UART5_CTS_N */
+					0x0d4 0x0 /* UART5_RTS_N */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
 					PULL_UP
 					PULL_DIS
 					PULL_UP
 				>;
 				pinctrl-single,drive-strength = <
-					DRIVE6_19MA
-					DRIVE6_MASK
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			cam0_rst_cfg_func: cam0_rst_cfg_func {
+				pinctrl-single,pins = <
+					0x0d4 0x0 /* CAM0_RST */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_04MA DRIVE6_MASK
+				>;
+			};
+
+			uart0_cfg_func: uart0_cfg_func {
+				pinctrl-single,pins = <
+					0x0d8 0x0 /* UART0_RXD */
+					0x0dc 0x0 /* UART0_TXD */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			uart6_cfg_func: uart6_cfg_func {
+				pinctrl-single,pins = <
+					0x0d8 0x0 /* UART6_CTS_N */
+					0x0dc 0x0 /* UART6_RTS_N */
+					0x0e0 0x0 /* UART6_RXD */
+					0x0e4 0x0 /* UART6_TXD */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			uart3_cfg_func: uart3_cfg_func {
+				pinctrl-single,pins = <
+					0x0e8 0x0 /* UART3_CTS_N */
+					0x0ec 0x0 /* UART3_RTS_N */
+					0x0f0 0x0 /* UART3_RXD */
+					0x0f4 0x0 /* UART3_TXD */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			uart4_cfg_func: uart4_cfg_func {
+				pinctrl-single,pins = <
+					0x0f8 0x0 /* UART4_CTS_N */
+					0x0fc 0x0 /* UART4_RTS_N */
+					0x100 0x0 /* UART4_RXD */
+					0x104 0x0 /* UART4_TXD */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			cam1_rst_cfg_func: cam1_rst_cfg_func {
+				pinctrl-single,pins = <
+					0x130 0x0 /* CAM1_RST */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_04MA DRIVE6_MASK
+				>;
+			};
+		};
+
+		pmx6: pinmux@ff3b6800 {
+			compatible = "pinconf-single";
+			reg = <0x0 0xff3b6800 0x0 0x18>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			pinctrl-single,register-width = <32>;
+
+			ufs_cfg_func: ufs_cfg_func {
+				pinctrl-single,pins = <
+					0x000 0x0 /* UFS_REF_CLK */
+					0x004 0x0 /* UFS_RST_N */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_08MA DRIVE6_MASK
+				>;
+			};
+
+			spi3_cfg_func: spi3_cfg_func {
+				pinctrl-single,pins = <
+					0x008 0x0 /* SPI3_CLK */
+					0x0 /* SPI3_DI */
+					0x010 0x0 /* SPI3_DO */
+					0x014 0x0 /* SPI3_CS0_N */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+		};
+
+		pmx7: pinmux@ff3fd800 {
+			compatible = "pinconf-single";
+			reg = <0x0 0xff3fd800 0x0 0x18>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			pinctrl-single,register-width = <32>;
+
+			sdio_clk_cfg_func: sdio_clk_cfg_func {
+				pinctrl-single,pins = <
+					0x000 0x0 /* SDIO_CLK */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE6_32MA DRIVE6_MASK
+				>;
+			};
+
+			sdio_cfg_func: sdio_cfg_func {
+				pinctrl-single,pins = <
+					0x004 0x0 /* SDIO_CMD */
+					0x008 0x0 /* SDIO_DATA0 */
+					0x00c 0x0 /* SDIO_DATA1 */
+					0x010 0x0 /* SDIO_DATA2 */
+					0x014 0x0 /* SDIO_DATA3 */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE6_19MA DRIVE6_MASK
+				>;
+			};
+		};
+
+		pmx8: pinmux@ff37e800 {
+			compatible = "pinconf-single";
+			reg = <0x0 0xff37e800 0x0 0x18>;
+			#pinctrl-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			pinctrl-single,register-width = <32>;
+
+			sd_clk_cfg_func: sd_clk_cfg_func {
+				pinctrl-single,pins = <
+					0x000 0x0 /* SD_CLK */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_DIS
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE6_32MA
+					DRIVE6_MASK
+				>;
+			};
+
+			sd_cfg_func: sd_cfg_func {
+				pinctrl-single,pins = <
+					0x004 0x0 /* SD_CMD */
+					0x008 0x0 /* SD_DATA0 */
+					0x00c 0x0 /* SD_DATA1 */
+					0x010 0x0 /* SD_DATA2 */
+					0x014 0x0 /* SD_DATA3 */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE6_19MA
+					DRIVE6_MASK
+				>;
+			};
+		};
+
+		pmx9: pinmux@fff11800 {
+			compatible = "pinconf-single";
+			reg = <0x0 0xfff11800 0x0 0xbc>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			pinctrl-single,register-width = <32>;
+
+			i2c0_cfg_func: i2c0_cfg_func {
+				pinctrl-single,pins = <
+					0x01c 0x0 /* I2C0_SCL */
+					0x020 0x0 /* I2C0_SDA */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			i2c1_cfg_func: i2c1_cfg_func {
+				pinctrl-single,pins = <
+					0x024 0x0 /* I2C1_SCL */
+					0x028 0x0 /* I2C1_SDA */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			i2c7_cfg_func: i2c7_cfg_func {
+				pinctrl-single,pins = <
+					0x02c 0x0 /* I2C7_SCL */
+					0x030 0x0 /* I2C7_SDA */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			slimbus_cfg_func: slimbus_cfg_func {
+				pinctrl-single,pins = <
+					0x034 0x0 /* SLIMBUS_CLK */
+					0x038 0x0 /* SLIMBUS_DATA */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			i2s0_cfg_func: i2s0_cfg_func {
+				pinctrl-single,pins = <
+					0x040 0x0 /* I2S0_DI */
+					0x044 0x0 /* I2S0_DO */
+					0x048 0x0 /* I2S0_XCLK */
+					0x04c 0x0 /* I2S0_XFS */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			i2s2_cfg_func: i2s2_cfg_func {
+				pinctrl-single,pins = <
+					0x050 0x0 /* I2S2_DI */
+					0x054 0x0 /* I2S2_DO */
+					0x058 0x0 /* I2S2_XCLK */
+					0x05c 0x0 /* I2S2_XFS */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			pcie_cfg_func: pcie_cfg_func {
+				pinctrl-single,pins = <
+					0x094 0x0 /* PCIE_CLKREQ_N */
+					0x098 0x0 /* PCIE_WAKE_N */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			spi2_cfg_func: spi2_cfg_func {
+				pinctrl-single,pins = <
+					0x09c 0x0 /* SPI2_CLK */
+					0x0a0 0x0 /* SPI2_DI */
+					0x0a4 0x0 /* SPI2_DO */
+					0x0a8 0x0 /* SPI2_CS0_N */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
+				>;
+			};
+
+			usb_cfg_func: usb_cfg_func {
+				pinctrl-single,pins = <
+					0x0ac 0x0 /* GPIO_219 */
+				>;
+				pinctrl-single,bias-pulldown = <
+					PULL_DIS
+					PULL_DOWN
+					PULL_DIS
+					PULL_DOWN
+				>;
+				pinctrl-single,bias-pullup = <
+					PULL_UP
+					PULL_UP
+					PULL_DIS
+					PULL_UP
+				>;
+				pinctrl-single,drive-strength = <
+					DRIVE7_02MA DRIVE6_MASK
 				>;
 			};
 		};
-- 
2.10.2

Re: [PATCH 03/12] arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig

[Rob Herring]

On Wed, May 17, 2017 at 04:37:36PM +0800, Guodong Xu wrote:
> From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
> 
> This commit adds more pinmux and pinctrl information for devices
> on HiKey960, including i2c, spi, cam, uart, ufs, pcie, csi, pwr_key,
> isp, sd/sdio, i2s, and usb.
> 
> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
> Signed-off-by: Chen Jun <chenjun14@huawei.com>
> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
> ---
>  .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 779 +++++++++++++++++++--
>  1 file changed, 719 insertions(+), 60 deletions(-)

Acked-by: Rob Herring <robh@kernel.org> 

[PATCH 04/12] arm64: dts: hi3660: add resources for clock and reset

[Guodong Xu]

From: Zhangfei Gao <zhangfei.gao@linaro.org>

Add some resource nodes for clock and reset

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 53 +++++++++++++++++++++++++++----
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086..f55710a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi3660-clock.h>
 
 / {
 	compatible = "hisilicon,hi3660";
@@ -141,18 +142,56 @@
 		#size-cells = <2>;
 		ranges;
 
-		fixed_uart5: fixed_19_2M {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <19200000>;
-			clock-output-names = "fixed:uart5";
+		crg_ctrl: crg_ctrl@fff35000 {
+			compatible = "hisilicon,hi3660-crgctrl", "syscon";
+			reg = <0x0 0xfff35000 0x0 0x1000>;
+			#clock-cells = <1>;
 		};
 
-		uart5: uart@fdf05000 {
+		crg_rst: crg_rst_controller {
+			compatible = "hisilicon,hi3660-reset";
+			#reset-cells = <2>;
+			hisi,rst-syscon = <&crg_ctrl>;
+		};
+
+
+		pctrl: pctrl@e8a09000 {
+			compatible = "hisilicon,hi3660-pctrl", "syscon";
+			reg = <0x0 0xe8a09000 0x0 0x2000>;
+			#clock-cells = <1>;
+		};
+
+		pmuctrl: crg_ctrl@fff34000 {
+			compatible = "hisilicon,hi3660-pmuctrl", "syscon";
+			reg = <0x0 0xfff34000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		sctrl: sctrl@fff0a000 {
+			compatible = "hisilicon,hi3660-sctrl", "syscon";
+			reg = <0x0 0xfff0a000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		iomcu: iomcu@ffd7e000 {
+			compatible = "hisilicon,hi3660-iomcu", "syscon";
+			reg = <0x0 0xffd7e000 0x0 0x1000>;
+			#clock-cells = <1>;
+
+		};
+
+		iomcu_rst: reset {
+			compatible = "hisilicon,hi3660-reset";
+			hisi,rst-syscon = <&iomcu>;
+			#reset-cells = <2>;
+		};
+
+		uart5: serial@fdf05000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xfdf05000 0x0 0x1000>;
 			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&fixed_uart5 &fixed_uart5>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
+				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
 			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
-- 
2.10.2

Re: [PATCH 04/12] arm64: dts: hi3660: add resources for clock and reset

[Rob Herring]

On Wed, May 17, 2017 at 04:37:37PM +0800, Guodong Xu wrote:
> From: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> 
> Add some resource nodes for clock and reset
> 
> Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 53 +++++++++++++++++++++++++++----
>  1 file changed, 46 insertions(+), 7 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> 
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[PATCH 05/12] arm64: dts: Add I2C nodes for Hi3660

[Guodong Xu]

From: Zhangfei Gao <zhangfei.gao@linaro.org>

Add I2C nodes for Hi3660-hikey960.

On HiKey960,
I2C0, I2C7 is connected to Low Speed Expansion Connector.
I2C1 is connected to ADV7535.
I2C3 is connected to USB5734.

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 ++++++++
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 56 +++++++++++++++++++++++
 2 files changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 64875a5..f685b1e 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -29,6 +29,24 @@
 	};
 };
 
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	adv7533: adv7533@39 {
+		status = "ok";
+		compatible = "adi,adv7533";
+		reg = <0x39>;
+	};
+};
+
+&i2c7 {
+	status = "okay";
+};
+
 &uart5 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index f55710a..f217c9d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -186,6 +186,62 @@
 			#reset-cells = <2>;
 		};
 
+		i2c0: i2c@FFD71000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0xFFD71000 0x0 0x1000>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <400000>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
+			resets = <&iomcu_rst 0x20 3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@FFD72000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0xFFD72000 0x0 0x1000>;
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <400000>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
+			resets = <&iomcu_rst 0x20 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@FDF0C000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0xFDF0C000 0x0 0x1000>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <400000>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
+			resets = <&crg_rst 0x78 7>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@FDF0B000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0xFDF0B000 0x0 0x1000>;
+			interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-frequency = <400000>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
+			resets = <&crg_rst 0x60 14>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
+			status = "disabled";
+		};
+
 		uart5: serial@fdf05000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xfdf05000 0x0 0x1000>;
-- 
2.10.2

Re: [PATCH 05/12] arm64: dts: Add I2C nodes for Hi3660

[Rob Herring]

On Wed, May 17, 2017 at 04:37:38PM +0800, Guodong Xu wrote:
> From: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> 
> Add I2C nodes for Hi3660-hikey960.
> 
> On HiKey960,
> I2C0, I2C7 is connected to Low Speed Expansion Connector.
> I2C1 is connected to ADV7535.
> I2C3 is connected to USB5734.
> 
> Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 ++++++++
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 56 +++++++++++++++++++++++
>  2 files changed, 74 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> index 64875a5..f685b1e 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> @@ -29,6 +29,24 @@
>  	};
>  };
>  
> +&i2c0 {
> +	status = "okay";
> +};
> +
> +&i2c1 {
> +	status = "okay";
> +
> +	adv7533: adv7533@39 {
> +		status = "ok";
> +		compatible = "adi,adv7533";
> +		reg = <0x39>;
> +	};
> +};
> +
> +&i2c7 {
> +	status = "okay";
> +};

labels for the LS connector?

> +
>  &uart5 {
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index f55710a..f217c9d 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -186,6 +186,62 @@
>  			#reset-cells = <2>;
>  		};
>  
> +		i2c0: i2c@FFD71000 {

lowercase hex please.

> +			compatible = "snps,designware-i2c";

These should have an SoC specific compatible.

> +			reg = <0x0 0xFFD71000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clock-frequency = <400000>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
> +			resets = <&iomcu_rst 0x20 3>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c@FFD72000 {

ditto

> +			compatible = "snps,designware-i2c";
> +			reg = <0x0 0xFFD72000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clock-frequency = <400000>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
> +			resets = <&iomcu_rst 0x20 4>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
> +			status = "disabled";
> +		};
> +
> +		i2c3: i2c@FDF0C000 {
> +			compatible = "snps,designware-i2c";
> +			reg = <0x0 0xFDF0C000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clock-frequency = <400000>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
> +			resets = <&crg_rst 0x78 7>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
> +			status = "disabled";
> +		};
> +
> +		i2c7: i2c@FDF0B000 {
> +			compatible = "snps,designware-i2c";
> +			reg = <0x0 0xFDF0B000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clock-frequency = <400000>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
> +			resets = <&crg_rst 0x60 14>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
> +			status = "disabled";
> +		};
> +
>  		uart5: serial@fdf05000 {
>  			compatible = "arm,pl011", "arm,primecell";
>  			reg = <0x0 0xfdf05000 0x0 0x1000>;
> -- 
> 2.10.2
> 
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Re: [PATCH 05/12] arm64: dts: Add I2C nodes for Hi3660

[zhangfei]

Hi, Rob


Thanks for the review.

On 2017年05月23日 08:39, Rob Herring wrote:
> On Wed, May 17, 2017 at 04:37:38PM +0800, Guodong Xu wrote:
>> From: Zhangfei Gao <zhangfei.gao@linaro.org>
>>
>> Add I2C nodes for Hi3660-hikey960.
>>
>> On HiKey960,
>> I2C0, I2C7 is connected to Low Speed Expansion Connector.
>> I2C1 is connected to ADV7535.
>> I2C3 is connected to USB5734.
>>
>> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
>> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
>> ---
>>   arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 ++++++++
>>   arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 56 +++++++++++++++++++++++
>>   2 files changed, 74 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> index 64875a5..f685b1e 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> @@ -29,6 +29,24 @@
>>   	};
>>   };
>>   
>> +&i2c0 {
>> +	status = "okay";
>> +};
>> +
>> +&i2c1 {
>> +	status = "okay";
>> +
>> +	adv7533: adv7533@39 {
>> +		status = "ok";
>> +		compatible = "adi,adv7533";
>> +		reg = <0x39>;
>> +	};
>> +};
>> +
>> +&i2c7 {
>> +	status = "okay";
>> +};
> labels for the LS connector?
Any examples?
There is compile error if only change dts like
ls-connector {
         &i2c7 {
                 status = "okay";
         };
};

>
>> +
>>   &uart5 {
>>   	status = "okay";
>>   };
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> index f55710a..f217c9d 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> @@ -186,6 +186,62 @@
>>   			#reset-cells = <2>;
>>   		};
>>   
>> +		i2c0: i2c@FFD71000 {
> lowercase hex please.
Yes, will change
>
>> +			compatible = "snps,designware-i2c";
> These should have an SoC specific compatible.
We directly use drivers/i2c/busses/i2c-designware-platdrv.c,
do we still an soc specific compatible?
Checked arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi, and other examples,

compatible = "snps,designware-i2c" is used.


Thanks

Re: [PATCH 05/12] arm64: dts: Add I2C nodes for Hi3660

[zhangfei]

On 2017年05月23日 13:55, zhangfei wrote:
> Hi, Rob
>
>
> Thanks for the review.
>
> On 2017年05月23日 08:39, Rob Herring wrote:
>> On Wed, May 17, 2017 at 04:37:38PM +0800, Guodong Xu wrote:
>>> From: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>>
>>> Add I2C nodes for Hi3660-hikey960.
>>>
>>> On HiKey960,
>>> I2C0, I2C7 is connected to Low Speed Expansion Connector.
>>> I2C1 is connected to ADV7535.
>>> I2C3 is connected to USB5734.
>>>
>>> Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>> Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>> ---
>>>   arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 ++++++++
>>>   arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 56 
>>> +++++++++++++++++++++++
>>>   2 files changed, 74 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts 
>>> b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>>> index 64875a5..f685b1e 100644
>>> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>>> @@ -29,6 +29,24 @@
>>>       };
>>>   };
>>>   +&i2c0 {
>>> +    status = "okay";
>>> +};
>>> +
>>> +&i2c1 {
>>> +    status = "okay";
>>> +
>>> +    adv7533: adv7533@39 {
>>> +        status = "ok";
>>> +        compatible = "adi,adv7533";
>>> +        reg = <0x39>;
>>> +    };
>>> +};
>>> +
>>> +&i2c7 {
>>> +    status = "okay";
>>> +};
>> labels for the LS connector?

Do you mean arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi

                 i2c@78ba000 {
                 /* On Low speed expansion */
                         label = "LS-I2C1";
                         status = "okay";
                 };

                 spi@78b7000 {
                 /* On High speed expansion */
                         label = "HS-SPI1";
                         status = "okay";
                 };

Thanks
>>
>>> +            compatible = "snps,designware-i2c";
>> These should have an SoC specific compatible.
> We directly use drivers/i2c/busses/i2c-designware-platdrv.c,
> do we still an soc specific compatible?
> Checked arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi, and other examples,
>
> compatible = "snps,designware-i2c" is used.
>
>
> Thanks
>

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Re: [PATCH 05/12] arm64: dts: Add I2C nodes for Hi3660

[Rob Herring]

On Tue, May 23, 2017 at 1:36 AM, zhangfei <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
>
>
> On 2017年05月23日 13:55, zhangfei wrote:
>>
>> Hi, Rob
>>
>>
>> Thanks for the review.
>>
>> On 2017年05月23日 08:39, Rob Herring wrote:
>>>
>>> On Wed, May 17, 2017 at 04:37:38PM +0800, Guodong Xu wrote:
>>>>
>>>> From: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>>>
>>>> Add I2C nodes for Hi3660-hikey960.
>>>>
>>>> On HiKey960,
>>>> I2C0, I2C7 is connected to Low Speed Expansion Connector.
>>>> I2C1 is connected to ADV7535.
>>>> I2C3 is connected to USB5734.
>>>>
>>>> Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>>> Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>>> ---
>>>>   arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 ++++++++
>>>>   arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 56
>>>> +++++++++++++++++++++++
>>>>   2 files changed, 74 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>>>> b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>>>> index 64875a5..f685b1e 100644
>>>> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>>>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>>>> @@ -29,6 +29,24 @@
>>>>       };
>>>>   };
>>>>   +&i2c0 {
>>>> +    status = "okay";
>>>> +};
>>>> +
>>>> +&i2c1 {
>>>> +    status = "okay";
>>>> +
>>>> +    adv7533: adv7533@39 {
>>>> +        status = "ok";
>>>> +        compatible = "adi,adv7533";
>>>> +        reg = <0x39>;
>>>> +    };
>>>> +};
>>>> +
>>>> +&i2c7 {
>>>> +    status = "okay";
>>>> +};
>>>
>>> labels for the LS connector?
>
>
> Do you mean arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
>
>                 i2c@78ba000 {
>                 /* On Low speed expansion */
>                         label = "LS-I2C1";
>                         status = "okay";
>                 };
>
>                 spi@78b7000 {
>                 /* On High speed expansion */
>                         label = "HS-SPI1";
>                         status = "okay";
>                 };

Yes. And the names need to align across boards to be useful.

Rob
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Re: [PATCH 05/12] arm64: dts: Add I2C nodes for Hi3660

[Rob Herring]

On Tue, May 23, 2017 at 12:55 AM, zhangfei <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> Hi, Rob
>
>
> Thanks for the review.
>
>
> On 2017年05月23日 08:39, Rob Herring wrote:
>>
>> On Wed, May 17, 2017 at 04:37:38PM +0800, Guodong Xu wrote:
>>>
>>> From: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>>
>>> Add I2C nodes for Hi3660-hikey960.
>>>
>>> On HiKey960,
>>> I2C0, I2C7 is connected to Low Speed Expansion Connector.
>>> I2C1 is connected to ADV7535.
>>> I2C3 is connected to USB5734.

[...]

>>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>>> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>>> index f55710a..f217c9d 100644
>>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>>> @@ -186,6 +186,62 @@
>>>                         #reset-cells = <2>;
>>>                 };
>>>   +             i2c0: i2c@FFD71000 {
>>
>> lowercase hex please.
>
> Yes, will change
>>
>>
>>> +                       compatible = "snps,designware-i2c";
>>
>> These should have an SoC specific compatible.
>
> We directly use drivers/i2c/busses/i2c-designware-platdrv.c,
> do we still an soc specific compatible?

It's fine if the driver uses the snps compatible, but the dts should
still have an SoC specific one.

> Checked arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi, and other examples,
>
> compatible = "snps,designware-i2c" is used.

That was a mistake in the other platforms. We shouldn't continue repeating it.

Rob
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Re: [PATCH 05/12] arm64: dts: Add I2C nodes for Hi3660

[zhangfei]

Hi, Jarkko

Would you mind give some suggestion?

On 2017年05月23日 20:48, Rob Herring wrote:
>
>>>> +                       compatible = "snps,designware-i2c";
>>> These should have an SoC specific compatible.
>> We directly use drivers/i2c/busses/i2c-designware-platdrv.c,
>> do we still an soc specific compatible?
> It's fine if the driver uses the snps compatible, but the dts should
> still have an SoC specific one.
>
>> Checked arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi, and other examples,
>>
>> compatible = "snps,designware-i2c" is used.
> That was a mistake in the other platforms. We shouldn't continue repeating it.
>
> Rob

Rob suggest add something like "hisilicon,hi3660-dw-i2c" as well.
"The problem is dw-i2c does not give any clue as to what the 
configuration or version of the IP is.
Is that fully discoverable with version/capability registers? If not 
then you need a specific compatible.
Generally when we have not required them, it ends up being a problem 
later on."


While Documentation/devicetree/bindings/i2c/i2c-designware.txt
compatible : should be "snps,designware-i2c"

Besides, on Hikey960,
[    3.822353] dw_readl(dev, DW_IC_COMP_VERSION)=0x3132302a
[    3.827763] dw_readl(dev, DW_IC_COMP_TYPE)=0x44570140
Are these two registers enough to distinguish version etc?

Thanks

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Re: [PATCH 05/12] arm64: dts: Add I2C nodes for Hi3660

[Jarkko Nikula]

On 05/24/2017 05:34 AM, zhangfei wrote:
> Rob suggest add something like "hisilicon,hi3660-dw-i2c" as well.
> "The problem is dw-i2c does not give any clue as to what the
> configuration or version of the IP is.
> Is that fully discoverable with version/capability registers? If not
> then you need a specific compatible.
> Generally when we have not required them, it ends up being a problem
> later on."
>
Some features are discoverable from DW_IC_COMP_PARAM_1, 
DW_IC_COMP_VERSION and DW_IC_COMP_TYPE registers. Although my 
specification does not document what's inside of DW_IC_COMP_VERSION and 
DW_IC_COMP_TYPE but code is using them.

>
> While Documentation/devicetree/bindings/i2c/i2c-designware.txt
> compatible : should be "snps,designware-i2c"
>
> Besides, on Hikey960,
> [    3.822353] dw_readl(dev, DW_IC_COMP_VERSION)=0x3132302a
> [    3.827763] dw_readl(dev, DW_IC_COMP_TYPE)=0x44570140
> Are these two registers enough to distinguish version etc?
>
I've seen DW_IC_COMP_VERSION being 0x3131352a or 0x3132312a in our 
platforms. DW_IC_COMP_TYPE has the same value what you are seeing.

-- 
Jarkko
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[PATCH 07/12] arm64: dts: hi3660: Add uarts nodes

[Guodong Xu]

From: Chen Feng <puck.chen@hisilicon.com>

Add nodes uart0 to uart4 and uart6 for hi3660 SoC.
Enable uart3 and uart6, disable uart5, in hikey960 board dts.

On HiKey960:
 - UART6 is used as default console, and is wired out through low speed
         expansion connector.
 - UART3 has RTS/CTS hardware handshake, and is wired out through low
         speed expansion connector.
 - UART5 is not used in commercial launched boards. So disable it.
 - UART4 is connected to Bluetooth, WL1837.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Zhangfei Gao <zhangfei.gao@hisilicon.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 +++++--
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 60 +++++++++++++++++++++++
 2 files changed, 73 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index f685b1e..513c496 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -15,12 +15,16 @@
 	compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
 
 	aliases {
-		serial5 = &uart5;       /* console UART */
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		serial6 = &uart6;
 	};
 
-	chosen {
-		stdout-path = "serial5:115200n8";
-	};
+	chosen {};
 
 	memory@0 {
 		device_type = "memory";
@@ -47,6 +51,10 @@
 	status = "okay";
 };
 
-&uart5 {
+&uart3 {
+	status = "okay";
+};
+
+&uart6 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3bea0d2..0951a29 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -242,6 +242,56 @@
 			status = "disabled";
 		};
 
+		uart0: serial@fdf02000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfdf02000 0x0 0x1000>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
+				 <&crg_ctrl HI3660_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart1: serial@fdf00000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfdf00000 0x0 0x1000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
+				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: serial@fdf03000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfdf03000 0x0 0x1000>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
+				 <&crg_ctrl HI3660_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart3: serial@ffd74000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xffd74000 0x0 0x1000>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
+				 <&crg_ctrl HI3660_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart4: serial@fdf01000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfdf01000 0x0 0x1000>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
+				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
 		uart5: serial@fdf05000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xfdf05000 0x0 0x1000>;
@@ -252,6 +302,16 @@
 			status = "disabled";
 		};
 
+		uart6: serial@fff32000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfff32000 0x0 0x1000>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_UART6>,
+				 <&crg_ctrl HI3660_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
 		gpio0: gpio@e8a0b000 {
 			compatible = "arm,pl061", "arm,primecell";
 			reg = <0 0xe8a0b000 0 0x1000>;
-- 
2.10.2

Re: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes

[Rob Herring]

On Wed, May 17, 2017 at 04:37:40PM +0800, Guodong Xu wrote:
> From: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> 
> Add nodes uart0 to uart4 and uart6 for hi3660 SoC.
> Enable uart3 and uart6, disable uart5, in hikey960 board dts.
> 
> On HiKey960:
>  - UART6 is used as default console, and is wired out through low speed
>          expansion connector.
>  - UART3 has RTS/CTS hardware handshake, and is wired out through low
>          speed expansion connector.
>  - UART5 is not used in commercial launched boards. So disable it.
>  - UART4 is connected to Bluetooth, WL1837.
> 
> Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Reviewed-by: Zhangfei Gao <zhangfei.gao-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 +++++--
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 60 +++++++++++++++++++++++
>  2 files changed, 73 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> index f685b1e..513c496 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> @@ -15,12 +15,16 @@
>  	compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
>  
>  	aliases {
> -		serial5 = &uart5;       /* console UART */
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +		serial6 = &uart6;
>  	};
>  
> -	chosen {
> -		stdout-path = "serial5:115200n8";

Why is this removed?

> -	};
> +	chosen {};
>  
>  	memory@0 {
>  		device_type = "memory";
> @@ -47,6 +51,10 @@
>  	status = "okay";
>  };
>  
> -&uart5 {
> +&uart3 {
> +	status = "okay";
> +};
> +
> +&uart6 {
>  	status = "okay";

labels for LS connector?

>  };
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 3bea0d2..0951a29 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -242,6 +242,56 @@
>  			status = "disabled";
>  		};
>  
> +		uart0: serial@fdf02000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfdf02000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
> +				 <&crg_ctrl HI3660_PCLK>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@fdf00000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfdf00000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
> +				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@fdf03000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfdf03000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
> +				 <&crg_ctrl HI3660_PCLK>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@ffd74000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xffd74000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
> +				 <&crg_ctrl HI3660_PCLK>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@fdf01000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfdf01000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
> +				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
>  		uart5: serial@fdf05000 {
>  			compatible = "arm,pl011", "arm,primecell";
>  			reg = <0x0 0xfdf05000 0x0 0x1000>;
> @@ -252,6 +302,16 @@
>  			status = "disabled";
>  		};
>  
> +		uart6: serial@fff32000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfff32000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_UART6>,
> +				 <&crg_ctrl HI3660_PCLK>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
>  		gpio0: gpio@e8a0b000 {
>  			compatible = "arm,pl061", "arm,primecell";
>  			reg = <0 0xe8a0b000 0 0x1000>;
> -- 
> 2.10.2
> 
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Re: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes

[Guodong Xu]

On Tue, May 23, 2017 at 8:44 AM, Rob Herring <robh@kernel.org> wrote:
> On Wed, May 17, 2017 at 04:37:40PM +0800, Guodong Xu wrote:
>> From: Chen Feng <puck.chen@hisilicon.com>
>>
>> Add nodes uart0 to uart4 and uart6 for hi3660 SoC.
>> Enable uart3 and uart6, disable uart5, in hikey960 board dts.
>>
>> On HiKey960:
>>  - UART6 is used as default console, and is wired out through low speed
>>          expansion connector.
>>  - UART3 has RTS/CTS hardware handshake, and is wired out through low
>>          speed expansion connector.
>>  - UART5 is not used in commercial launched boards. So disable it.
>>  - UART4 is connected to Bluetooth, WL1837.
>>
>> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
>> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
>> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
>> Reviewed-by: Zhangfei Gao <zhangfei.gao@hisilicon.com>
>> ---
>>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 +++++--
>>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 60 +++++++++++++++++++++++
>>  2 files changed, 73 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> index f685b1e..513c496 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> @@ -15,12 +15,16 @@
>>       compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
>>
>>       aliases {
>> -             serial5 = &uart5;       /* console UART */
>> +             serial0 = &uart0;
>> +             serial1 = &uart1;
>> +             serial2 = &uart2;
>> +             serial3 = &uart3;
>> +             serial4 = &uart4;
>> +             serial5 = &uart5;
>> +             serial6 = &uart6;
>>       };
>>
>> -     chosen {
>> -             stdout-path = "serial5:115200n8";
>
> Why is this removed?
>

I will add this back, but will change serial5 to 6. Serial6 is now the
default console.

serial5 is obsoleted on commercial boards.


>> -     };
>> +     chosen {};
>>
>>       memory@0 {
>>               device_type = "memory";
>> @@ -47,6 +51,10 @@
>>       status = "okay";
>>  };
>>
>> -&uart5 {
>> +&uart3 {
>> +     status = "okay";
>> +};
>> +
>> +&uart6 {
>>       status = "okay";
>
> labels for LS connector?
>

Yes, I Will add.

-Guodong

>>  };
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> index 3bea0d2..0951a29 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> @@ -242,6 +242,56 @@
>>                       status = "disabled";
>>               };
>>
>> +             uart0: serial@fdf02000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfdf02000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
>> +                              <&crg_ctrl HI3660_PCLK>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             uart1: serial@fdf00000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfdf00000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
>> +                              <&crg_ctrl HI3660_CLK_GATE_UART1>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             uart2: serial@fdf03000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfdf03000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
>> +                              <&crg_ctrl HI3660_PCLK>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             uart3: serial@ffd74000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xffd74000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
>> +                              <&crg_ctrl HI3660_PCLK>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             uart4: serial@fdf01000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfdf01000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
>> +                              <&crg_ctrl HI3660_CLK_GATE_UART4>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>>               uart5: serial@fdf05000 {
>>                       compatible = "arm,pl011", "arm,primecell";
>>                       reg = <0x0 0xfdf05000 0x0 0x1000>;
>> @@ -252,6 +302,16 @@
>>                       status = "disabled";
>>               };
>>
>> +             uart6: serial@fff32000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfff32000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_UART6>,
>> +                              <&crg_ctrl HI3660_PCLK>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>>               gpio0: gpio@e8a0b000 {
>>                       compatible = "arm,pl061", "arm,primecell";
>>                       reg = <0 0xe8a0b000 0 0x1000>;
>> --
>> 2.10.2
>>

[PATCH 08/12] arm64: dts: hikey960: add WL1837 Bluetooth device node

[Guodong Xu]

This adds the serial slave device for the WL1837 Bluetooth interface.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 513c496..69aa207 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -9,6 +9,7 @@
 
 #include "hi3660.dtsi"
 #include "hikey960-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "HiKey960";
@@ -55,6 +56,16 @@
 	status = "okay";
 };
 
+&uart4 {
+	status = "okay";
+	max-speed = <921600>;
+
+	bluetooth {
+		compatible = "ti,wl1837-st";
+		enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
+	};
+};
+
 &uart6 {
 	status = "okay";
 };
-- 
2.10.2

Re: [PATCH 08/12] arm64: dts: hikey960: add WL1837 Bluetooth device node

[Rob Herring]

On Wed, May 17, 2017 at 04:37:41PM +0800, Guodong Xu wrote:
> This adds the serial slave device for the WL1837 Bluetooth interface.
> 
> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> index 513c496..69aa207 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> @@ -9,6 +9,7 @@
>  
>  #include "hi3660.dtsi"
>  #include "hikey960-pinctrl.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
>  
>  / {
>  	model = "HiKey960";
> @@ -55,6 +56,16 @@
>  	status = "okay";
>  };
>  
> +&uart4 {
> +	status = "okay";
> +	max-speed = <921600>;

This goes in the bluetooth node.

> +
> +	bluetooth {
> +		compatible = "ti,wl1837-st";
> +		enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
>  &uart6 {
>  	status = "okay";
>  };
> -- 
> 2.10.2
> 

Re: [PATCH 08/12] arm64: dts: hikey960: add WL1837 Bluetooth device node

[Guodong Xu]

On Tue, May 23, 2017 at 8:45 AM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Wed, May 17, 2017 at 04:37:41PM +0800, Guodong Xu wrote:
>> This adds the serial slave device for the WL1837 Bluetooth interface.
>>
>> Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> ---
>>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> index 513c496..69aa207 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> @@ -9,6 +9,7 @@
>>
>>  #include "hi3660.dtsi"
>>  #include "hikey960-pinctrl.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>>
>>  / {
>>       model = "HiKey960";
>> @@ -55,6 +56,16 @@
>>       status = "okay";
>>  };
>>
>> +&uart4 {
>> +     status = "okay";
>> +     max-speed = <921600>;
>
> This goes in the bluetooth node.

Yeah, thanks. I will fix.

-Guodong

>
>> +
>> +     bluetooth {
>> +             compatible = "ti,wl1837-st";
>> +             enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
>> +     };
>> +};
>> +
>>  &uart6 {
>>       status = "okay";
>>  };
>> --
>> 2.10.2
>>
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[PATCH 10/12] arm64: dts: hi3660: add spi device nodes

[Guodong Xu]

From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>

Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960.

On HiKey960:
 - SPI2 is wired out through low speed expansion connector.
 - SPI3 is wired out through high speed expansion connector.

Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts |  8 ++++++
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 30 +++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 69aa207..79735ee 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -69,3 +69,11 @@
 &uart6 {
 	status = "okay";
 };
+
+&spi2 {
+	status = "okay";
+};
+
+&spi3 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index c2bca5d..48da97f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -728,5 +728,35 @@
 			clock-names = "apb_pclk";
 			status = "ok";
 		};
+
+		spi2: spi@ffd68000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x0 0xffd68000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
+			clock-names = "apb_pclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi2_pmx_func>;
+			num-cs = <1>;
+			cs-gpios = <&gpio27 2 0>;
+			status = "disabled";
+		};
+
+		spi3: spi@ff3b3000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x0 0xff3b3000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
+			clock-names = "apb_pclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi3_pmx_func>;
+			num-cs = <1>;
+			cs-gpios = <&gpio18 5 0>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.10.2

Re: [PATCH 10/12] arm64: dts: hi3660: add spi device nodes

[Rob Herring]

On Wed, May 17, 2017 at 04:37:43PM +0800, Guodong Xu wrote:
> From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
> 
> Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960.
> 
> On HiKey960:
>  - SPI2 is wired out through low speed expansion connector.
>  - SPI3 is wired out through high speed expansion connector.
> 
> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts |  8 ++++++
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 30 +++++++++++++++++++++++
>  2 files changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> index 69aa207..79735ee 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> @@ -69,3 +69,11 @@
>  &uart6 {
>  	status = "okay";
>  };
> +
> +&spi2 {
> +	status = "okay";
> +};
> +
> +&spi3 {
> +	status = "okay";

LS connector label?

Re: [PATCH 10/12] arm64: dts: hi3660: add spi device nodes

[Guodong Xu]

On Tue, May 23, 2017 at 8:46 AM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Wed, May 17, 2017 at 04:37:43PM +0800, Guodong Xu wrote:
>> From: Wang Xiaoyin <hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
>>
>> Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960.
>>
>> On HiKey960:
>>  - SPI2 is wired out through low speed expansion connector.
>>  - SPI3 is wired out through high speed expansion connector.
>>
>> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
>> Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> ---
>>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts |  8 ++++++
>>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 30 +++++++++++++++++++++++
>>  2 files changed, 38 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> index 69aa207..79735ee 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> @@ -69,3 +69,11 @@
>>  &uart6 {
>>       status = "okay";
>>  };
>> +
>> +&spi2 {
>> +     status = "okay";
>> +};
>> +
>> +&spi3 {
>> +     status = "okay";
>
> LS connector label?

Thanks Rob. I will fix that, adding label accordingly.
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[PATCH 01/12] dt-bindings: arm: hisilicon: add bindings for HiKey960 board

[Guodong Xu]

Add bindings for HiKey960 Board.

Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 2e73215..7111fbc8 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -4,6 +4,10 @@ Hi3660 SoC
 Required root node properties:
 	- compatible = "hisilicon,hi3660";
 
+HiKey960 Board
+Required root node properties:
+	- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
+
 Hi3798cv200 SoC
 Required root node properties:
 	- compatible = "hisilicon,hi3798cv200";
-- 
2.10.2

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Re: [PATCH 01/12] dt-bindings: arm: hisilicon: add bindings for HiKey960 board

[Rob Herring]

On Wed, May 17, 2017 at 04:37:34PM +0800, Guodong Xu wrote:
> Add bindings for HiKey960 Board.
> 
> Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
>  1 file changed, 4 insertions(+)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> 
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[PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC

[Guodong Xu]

From: Wang Xiaoyin <hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>

This patch adds pl061 device nodes for Hi3660 SoC.

Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 409 ++++++++++++++++++++++++++++++
 1 file changed, 409 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index f217c9d..3bea0d2 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -251,5 +251,414 @@
 			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
+
+		gpio0: gpio@e8a0b000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0b000 0 0x1000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 1 0 7>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio1: gpio@e8a0c000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0c000 0 0x1000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 1 7 7>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio2: gpio@e8a0d000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0d000 0 0x1000>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 14 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio3: gpio@e8a0e000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0e000 0 0x1000>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 22 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio4: gpio@e8a0f000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0f000 0 0x1000>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 30 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio5: gpio@e8a10000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a10000 0 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 38 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio6: gpio@e8a11000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a11000 0 0x1000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 46 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio7: gpio@e8a12000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a12000 0 0x1000>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 54 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio8: gpio@e8a13000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a13000 0 0x1000>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 62 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio9: gpio@e8a14000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a14000 0 0x1000>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 70 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio10: gpio@e8a15000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a15000 0 0x1000>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 78 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio11: gpio@e8a16000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a16000 0 0x1000>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 86 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio12: gpio@e8a17000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a17000 0 0x1000>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio13: gpio@e8a18000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a18000 0 0x1000>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 102 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio14: gpio@e8a19000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a19000 0 0x1000>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 110 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio15: gpio@e8a1a000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a1a000 0 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 118 6>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio16: gpio@e8a1b000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a1b000 0 0x1000>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio17: gpio@e8a1c000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a1c000 0 0x1000>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio18: gpio@ff3b4000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xff3b4000 0 0x1000>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx2 0 0 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio19: gpio@ff3b5000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xff3b5000 0 0x1000>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx2 0 8 4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio20: gpio@e8a1f000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a1f000 0 0x1000>;
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx1 0 0 6>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio21: gpio@e8a20000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a20000 0 0x1000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx3 0 0 6>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio22: gpio@fff0b000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0b000 0 0x1000>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO176 */
+			gpio-ranges = <&pmx4 2 0 6>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio23: gpio@fff0c000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0c000 0 0x1000>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO184 */
+			gpio-ranges = <&pmx4 0 6 7>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		 gpio24: gpio@fff0d000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0d000 0 0x1000>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO192 */
+			gpio-ranges = <&pmx4 0 13 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio25: gpio@fff0e000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0e000 0 0x1000>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO200 */
+			gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio26: gpio@fff0f000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0f000 0 0x1000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO208 */
+			gpio-ranges = <&pmx4 0 28 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio27: gpio@fff10000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff10000 0 0x1000>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO216 */
+			gpio-ranges = <&pmx4 0 36 6>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio28: gpio@fff1d000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff1d000 0 0x1000>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
 	};
 };
-- 
2.10.2

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Re: [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC

[Rob Herring]

On Wed, May 17, 2017 at 04:37:39PM +0800, Guodong Xu wrote:
> From: Wang Xiaoyin <hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> 
> This patch adds pl061 device nodes for Hi3660 SoC.
> 
> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 409 ++++++++++++++++++++++++++++++
>  1 file changed, 409 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index f217c9d..3bea0d2 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -251,5 +251,414 @@
>  			clock-names = "uartclk", "apb_pclk";
>  			status = "disabled";
>  		};
> +
> +		gpio0: gpio@e8a0b000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0b000 0 0x1000>;
> +			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 1 0 7>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
> +			clock-names = "apb_pclk";
> +			status = "ok";

You don't need "ok" here if these are default enabled.

> +		};
> +
> +		gpio1: gpio@e8a0c000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0c000 0 0x1000>;
> +			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 1 7 7>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
> +			clock-names = "apb_pclk";
> +			status = "ok";

ditto...

> +		};
> +
> +		gpio2: gpio@e8a0d000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0d000 0 0x1000>;
> +			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 14 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio3: gpio@e8a0e000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0e000 0 0x1000>;
> +			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 22 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio4: gpio@e8a0f000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0f000 0 0x1000>;
> +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 30 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio5: gpio@e8a10000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a10000 0 0x1000>;
> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 38 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio6: gpio@e8a11000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a11000 0 0x1000>;
> +			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 46 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio7: gpio@e8a12000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a12000 0 0x1000>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 54 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio8: gpio@e8a13000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a13000 0 0x1000>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 62 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio9: gpio@e8a14000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a14000 0 0x1000>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 70 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio10: gpio@e8a15000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a15000 0 0x1000>;
> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 78 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio11: gpio@e8a16000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a16000 0 0x1000>;
> +			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 86 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio12: gpio@e8a17000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a17000 0 0x1000>;
> +			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio13: gpio@e8a18000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a18000 0 0x1000>;
> +			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 102 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio14: gpio@e8a19000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a19000 0 0x1000>;
> +			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 110 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio15: gpio@e8a1a000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a1a000 0 0x1000>;
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 118 6>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio16: gpio@e8a1b000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a1b000 0 0x1000>;
> +			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio17: gpio@e8a1c000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a1c000 0 0x1000>;
> +			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio18: gpio@ff3b4000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xff3b4000 0 0x1000>;
> +			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx2 0 0 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio19: gpio@ff3b5000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xff3b5000 0 0x1000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx2 0 8 4>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio20: gpio@e8a1f000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a1f000 0 0x1000>;
> +			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx1 0 0 6>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio21: gpio@e8a20000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a20000 0 0x1000>;
> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			gpio-ranges = <&pmx3 0 0 6>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio22: gpio@fff0b000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xfff0b000 0 0x1000>;
> +			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			/* GPIO176 */
> +			gpio-ranges = <&pmx4 2 0 6>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio23: gpio@fff0c000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xfff0c000 0 0x1000>;
> +			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			/* GPIO184 */
> +			gpio-ranges = <&pmx4 0 6 7>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		 gpio24: gpio@fff0d000 {

extra space     ^               
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Re: [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC

[Guodong Xu]

[-- Attachment #1: Type: text/plain, Size: 17068 bytes --]

On Tue, May 23, 2017 at 8:41 AM, Rob Herring <robh@kernel.org> wrote:

> On Wed, May 17, 2017 at 04:37:39PM +0800, Guodong Xu wrote:
> > From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
> >
> > This patch adds pl061 device nodes for Hi3660 SoC.
> >
> > Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
> > ---
> >  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 409
> ++++++++++++++++++++++++++++++
> >  1 file changed, 409 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> > index f217c9d..3bea0d2 100644
> > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> > @@ -251,5 +251,414 @@
> >                       clock-names = "uartclk", "apb_pclk";
> >                       status = "disabled";
> >               };
> > +
> > +             gpio0: gpio@e8a0b000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a0b000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 1 0 7>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
>
> You don't need "ok" here if these are default enabled.
>
> > +             };
> > +
> > +             gpio1: gpio@e8a0c000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a0c000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 1 7 7>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
>
> ditto...
>
> > +             };
> > +
> > +             gpio2: gpio@e8a0d000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a0d000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 14 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio3: gpio@e8a0e000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a0e000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 22 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio4: gpio@e8a0f000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a0f000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 30 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio5: gpio@e8a10000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a10000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 38 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio6: gpio@e8a11000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a11000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 46 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio7: gpio@e8a12000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a12000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 54 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio8: gpio@e8a13000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a13000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 62 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio9: gpio@e8a14000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a14000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 70 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio10: gpio@e8a15000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a15000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 78 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio11: gpio@e8a16000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a16000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 86 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio12: gpio@e8a17000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a17000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio13: gpio@e8a18000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a18000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 102 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio14: gpio@e8a19000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a19000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 110 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio15: gpio@e8a1a000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a1a000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx0 0 118 6>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio16: gpio@e8a1b000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a1b000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio17: gpio@e8a1c000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a1c000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio18: gpio@ff3b4000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xff3b4000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx2 0 0 8>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio19: gpio@ff3b5000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xff3b5000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx2 0 8 4>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio20: gpio@e8a1f000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a1f000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     gpio-ranges = <&pmx1 0 0 6>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio21: gpio@e8a20000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xe8a20000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     gpio-ranges = <&pmx3 0 0 6>;
> > +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio22: gpio@fff0b000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xfff0b000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     /* GPIO176 */
> > +                     gpio-ranges = <&pmx4 2 0 6>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +             gpio23: gpio@fff0c000 {
> > +                     compatible = "arm,pl061", "arm,primecell";
> > +                     reg = <0 0xfff0c000 0 0x1000>;
> > +                     interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     /* GPIO184 */
> > +                     gpio-ranges = <&pmx4 0 6 7>;
> > +                     interrupt-controller;
> > +                     #interrupt-cells = <2>;
> > +                     clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
> > +                     clock-names = "apb_pclk";
> > +                     status = "ok";
> > +             };
> > +
> > +              gpio24: gpio@fff0d000 {
>
> extra space     ^
>

Thanks, Rob. I will fix.

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Re: [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC

[Guodong Xu]

On Tue, May 23, 2017 at 8:41 AM, Rob Herring <robh@kernel.org> wrote:
> On Wed, May 17, 2017 at 04:37:39PM +0800, Guodong Xu wrote:
>> From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
>>
>> This patch adds pl061 device nodes for Hi3660 SoC.
>>
>> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
>> ---
>>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 409 ++++++++++++++++++++++++++++++
>>  1 file changed, 409 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> index f217c9d..3bea0d2 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> @@ -251,5 +251,414 @@
>>                       clock-names = "uartclk", "apb_pclk";
>>                       status = "disabled";
>>               };
>> +
>> +             gpio0: gpio@e8a0b000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0b000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 1 0 7>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>
> You don't need "ok" here if these are default enabled.
>
>> +             };
>> +
>> +             gpio1: gpio@e8a0c000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0c000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 1 7 7>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>
> ditto...
>
>> +             };
>> +
>> +             gpio2: gpio@e8a0d000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0d000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 14 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio3: gpio@e8a0e000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0e000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 22 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio4: gpio@e8a0f000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0f000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 30 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio5: gpio@e8a10000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a10000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 38 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio6: gpio@e8a11000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a11000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 46 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio7: gpio@e8a12000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a12000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 54 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio8: gpio@e8a13000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a13000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 62 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio9: gpio@e8a14000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a14000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 70 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio10: gpio@e8a15000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a15000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 78 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio11: gpio@e8a16000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a16000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 86 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio12: gpio@e8a17000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a17000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio13: gpio@e8a18000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a18000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 102 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio14: gpio@e8a19000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a19000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 110 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio15: gpio@e8a1a000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a1a000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 118 6>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio16: gpio@e8a1b000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a1b000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio17: gpio@e8a1c000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a1c000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio18: gpio@ff3b4000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xff3b4000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx2 0 0 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio19: gpio@ff3b5000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xff3b5000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx2 0 8 4>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio20: gpio@e8a1f000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a1f000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx1 0 0 6>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio21: gpio@e8a20000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a20000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     gpio-ranges = <&pmx3 0 0 6>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio22: gpio@fff0b000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xfff0b000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     /* GPIO176 */
>> +                     gpio-ranges = <&pmx4 2 0 6>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio23: gpio@fff0c000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xfff0c000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     /* GPIO184 */
>> +                     gpio-ranges = <&pmx4 0 6 7>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +              gpio24: gpio@fff0d000 {
>
> extra space     ^

Thanks, Rob. I will fix this and all above.

[PATCH 09/12] arm64: dts: hi3660: Add pl031 rtc node

[Guodong Xu]

From: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>

Add dts node to enable pl031 rtc.

Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 0951a29..c2bca5d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -312,6 +312,14 @@
 			status = "disabled";
 		};
 
+		rtc0: rtc@fff04000 {
+			compatible = "arm,pl031", "arm,primecell";
+			reg = <0x0 0Xfff04000 0x0 0x1000>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_PCLK>;
+			clock-names = "apb_pclk";
+		};
+
 		gpio0: gpio@e8a0b000 {
 			compatible = "arm,pl061", "arm,primecell";
 			reg = <0 0xe8a0b000 0 0x1000>;
-- 
2.10.2

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Re: [PATCH 09/12] arm64: dts: hi3660: Add pl031 rtc node

[Rob Herring]

On Wed, May 17, 2017 at 04:37:42PM +0800, Guodong Xu wrote:
> From: Chen Feng <puck.chen@hisilicon.com>
> 
> Add dts node to enable pl031 rtc.
> 
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)

Acked-by: Rob Herring <robh@kernel.org> 

[PATCH 11/12] arm64: dts: hi3660: add power key dts node

[Guodong Xu]

From: Chen Jun <chenjun14-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>

We use gpio_034 as power key on hikey960, and set gpio with pull-up
state, when key press the voltage on the gpio will come to lower, and
power key event will be reported.

Signed-off-by: Chen Jun <chenjun14-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: John Stultz <john.stultz-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 79735ee..6de86c0 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -10,6 +10,8 @@
 #include "hi3660.dtsi"
 #include "hikey960-pinctrl.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "HiKey960";
@@ -32,6 +34,21 @@
 		/* rewrite this at bootloader */
 		reg = <0x0 0x0 0x0 0x0>;
 	};
+
+	soc {
+		keys: gpio-keys {
+			compatible = "gpio-keys";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
+
+			power {
+				wakeup-source;
+				gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+				label = "GPIO Power";
+				linux,code = <KEY_POWER>;
+			};
+		};
+	};
 };
 
 &i2c0 {
-- 
2.10.2

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Re: [PATCH 11/12] arm64: dts: hi3660: add power key dts node

[Rob Herring]

On Wed, May 17, 2017 at 04:37:44PM +0800, Guodong Xu wrote:
> From: Chen Jun <chenjun14@huawei.com>
> 
> We use gpio_034 as power key on hikey960, and set gpio with pull-up
> state, when key press the voltage on the gpio will come to lower, and
> power key event will be reported.
> 
> Signed-off-by: Chen Jun <chenjun14@huawei.com>
> Signed-off-by: John Stultz <john.stultz@linaro.org>
> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> index 79735ee..6de86c0 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> @@ -10,6 +10,8 @@
>  #include "hi3660.dtsi"
>  #include "hikey960-pinctrl.dtsi"
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
>  
>  / {
>  	model = "HiKey960";
> @@ -32,6 +34,21 @@
>  		/* rewrite this at bootloader */
>  		reg = <0x0 0x0 0x0 0x0>;
>  	};
> +
> +	soc {
> +		keys: gpio-keys {

This isn't part of the SoC, so it should move out of the soc node.

> +			compatible = "gpio-keys";
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
> +
> +			power {
> +				wakeup-source;
> +				gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
> +				label = "GPIO Power";
> +				linux,code = <KEY_POWER>;
> +			};
> +		};
> +	};
>  };
>  
>  &i2c0 {
> -- 
> 2.10.2
> 

[PATCH 12/12] arm64: dts: hikey960: add LED nodes

[Guodong Xu]

HiKey960 has four user LEDs, and two special purpose LEDs: WiFi and BT
respectively.

All of them are implemented as GPIO.

Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 48 +++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 6de86c0..4839885 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -48,6 +48,54 @@
 				linux,code = <KEY_POWER>;
 			};
 		};
+
+		leds {
+			compatible = "gpio-leds";
+			status = "disabled";
+			user_led1 {
+				label = "user_led1";
+				/* gpio_150_user_led1 */
+				gpios = <&gpio18 6 0>;
+				linux,default-trigger = "heartbeat";
+			};
+
+			user_led2 {
+				label = "user_led2";
+				/* gpio_151_user_led2 */
+				gpios = <&gpio18 7 0>;
+				linux,default-trigger = "mmc0";
+			};
+
+			user_led3 {
+				label = "user_led3";
+				/* gpio_189_user_led3 */
+				gpios = <&gpio23 5 0>;
+				default-state = "off";
+			};
+
+			user_led4 {
+				label = "user_led4";
+				/* gpio_190_user_led4 */
+				gpios = <&gpio23 6 0>;
+				linux,default-trigger = "cpu0";
+			};
+
+			wlan_active_led {
+				label = "wifi_active";
+				/* gpio_205_wifi_active */
+				gpios = <&gpio25 5 0>;
+				linux,default-trigger = "phy0tx";
+				default-state = "off";
+			};
+
+			bt_active_led {
+				label = "bt_active";
+				gpios = <&gpio25 7 0>;
+				/* gpio_207_user_led1 */
+				linux,default-trigger = "hci0rx";
+				default-state = "off";
+			};
+		};
 	};
 };
 
-- 
2.10.2

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Re: [PATCH 12/12] arm64: dts: hikey960: add LED nodes

[Rob Herring]

On Wed, May 17, 2017 at 04:37:45PM +0800, Guodong Xu wrote:
> HiKey960 has four user LEDs, and two special purpose LEDs: WiFi and BT
> respectively.
> 
> All of them are implemented as GPIO.
> 
> Signed-off-by: Guodong Xu <guodong.xu-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 48 +++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> index 6de86c0..4839885 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> @@ -48,6 +48,54 @@
>  				linux,code = <KEY_POWER>;
>  			};
>  		};
> +
> +		leds {

This too should move out of the soc node.

> +			compatible = "gpio-leds";
> +			status = "disabled";
> +			user_led1 {
> +				label = "user_led1";
> +				/* gpio_150_user_led1 */
> +				gpios = <&gpio18 6 0>;
> +				linux,default-trigger = "heartbeat";
> +			};
> +
> +			user_led2 {
> +				label = "user_led2";
> +				/* gpio_151_user_led2 */
> +				gpios = <&gpio18 7 0>;
> +				linux,default-trigger = "mmc0";
> +			};
> +
> +			user_led3 {
> +				label = "user_led3";
> +				/* gpio_189_user_led3 */
> +				gpios = <&gpio23 5 0>;
> +				default-state = "off";
> +			};
> +
> +			user_led4 {
> +				label = "user_led4";
> +				/* gpio_190_user_led4 */
> +				gpios = <&gpio23 6 0>;
> +				linux,default-trigger = "cpu0";
> +			};
> +
> +			wlan_active_led {
> +				label = "wifi_active";
> +				/* gpio_205_wifi_active */
> +				gpios = <&gpio25 5 0>;
> +				linux,default-trigger = "phy0tx";
> +				default-state = "off";
> +			};
> +
> +			bt_active_led {
> +				label = "bt_active";
> +				gpios = <&gpio25 7 0>;
> +				/* gpio_207_user_led1 */
> +				linux,default-trigger = "hci0rx";
> +				default-state = "off";
> +			};
> +		};
>  	};
>  };
>  
> -- 
> 2.10.2
> 
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Re: [PATCH 12/12] arm64: dts: hikey960: add LED nodes

[Guodong Xu]

On Tue, May 23, 2017 at 8:48 AM, Rob Herring <robh@kernel.org> wrote:
> On Wed, May 17, 2017 at 04:37:45PM +0800, Guodong Xu wrote:
>> HiKey960 has four user LEDs, and two special purpose LEDs: WiFi and BT
>> respectively.
>>
>> All of them are implemented as GPIO.
>>
>> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
>> ---
>>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 48 +++++++++++++++++++++++
>>  1 file changed, 48 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> index 6de86c0..4839885 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> @@ -48,6 +48,54 @@
>>                               linux,code = <KEY_POWER>;
>>                       };
>>               };
>> +
>> +             leds {
>
> This too should move out of the soc node.

Thanks, Rob. I will fix these.

-Guodong

>
>> +                     compatible = "gpio-leds";
>> +                     status = "disabled";
>> +                     user_led1 {
>> +                             label = "user_led1";
>> +                             /* gpio_150_user_led1 */
>> +                             gpios = <&gpio18 6 0>;
>> +                             linux,default-trigger = "heartbeat";
>> +                     };
>> +
>> +                     user_led2 {
>> +                             label = "user_led2";
>> +                             /* gpio_151_user_led2 */
>> +                             gpios = <&gpio18 7 0>;
>> +                             linux,default-trigger = "mmc0";
>> +                     };
>> +
>> +                     user_led3 {
>> +                             label = "user_led3";
>> +                             /* gpio_189_user_led3 */
>> +                             gpios = <&gpio23 5 0>;
>> +                             default-state = "off";
>> +                     };
>> +
>> +                     user_led4 {
>> +                             label = "user_led4";
>> +                             /* gpio_190_user_led4 */
>> +                             gpios = <&gpio23 6 0>;
>> +                             linux,default-trigger = "cpu0";
>> +                     };
>> +
>> +                     wlan_active_led {
>> +                             label = "wifi_active";
>> +                             /* gpio_205_wifi_active */
>> +                             gpios = <&gpio25 5 0>;
>> +                             linux,default-trigger = "phy0tx";
>> +                             default-state = "off";
>> +                     };
>> +
>> +                     bt_active_led {
>> +                             label = "bt_active";
>> +                             gpios = <&gpio25 7 0>;
>> +                             /* gpio_207_user_led1 */
>> +                             linux,default-trigger = "hci0rx";
>> +                             default-state = "off";
>> +                     };
>> +             };
>>       };
>>  };
>>
>> --
>> 2.10.2
>>