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Thu, 11 Jun 2026 01:51:25 -0700 (PDT) X-Received: by 2002:ac8:5a82:0:b0:50b:5286:f757 with SMTP id d75a77b69052e-517ee1d6c5amr17027171cf.4.1781167884709; Thu, 11 Jun 2026 01:51:24 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bfcb688410csm31719566b.61.2026.06.11.01.51.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Jun 2026 01:51:23 -0700 (PDT) Message-ID: <10c2e008-74fe-4dac-99bf-194a1767bc16@oss.qualcomm.com> Date: Thu, 11 Jun 2026 10:51:21 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/3] clk: qcom: camcc-glymur: Add camera clock controller driver To: Bryan O'Donoghue , Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das References: <20260517-glymur_camcc-v4-0-9d00acffdbf7@oss.qualcomm.com> <20260517-glymur_camcc-v4-2-9d00acffdbf7@oss.qualcomm.com> <8bd4365e-0171-425c-9738-0b186047cb15@kernel.org> <2a496bdf-4728-47b9-84ba-063712a6e5b6@oss.qualcomm.com> <0a197b43-a672-4849-91c7-6e5bfe3175f7@kernel.org> <66335474-d600-45ab-9ac6-e946f24142c8@oss.qualcomm.com> <639c94f9-6f62-4502-ad7e-5ae60f5f6d02@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <639c94f9-6f62-4502-ad7e-5ae60f5f6d02@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 1437t2XGssyxfd9ZgtZ-yPzL6PVg0aRt X-Authority-Analysis: v=2.4 cv=B9eJFutM c=1 sm=1 tr=0 ts=6a2a770e cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=JoSlTferZKbt7Xiq8IoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDA4NiBTYWx0ZWRfX/s8+3heJ/0KL KnUFwz97RQAYFHEGWVHIkVRvnQlRt8y4FlTjwyDrTpE5u2YavKugkqBCuUYr6F5ut1TrwinnQ8C KB5IZgKkr/idH/iOxWX0VrN94IoSoQePNBUTSd93sC+8U39/7iF9pD5GXjYEDtDnALbVPUc0S54 OXOE8powHUcrCL01sHlfUv0zjG3Hpec9araXgJCdduThmeuZOVHqr0FujWZfnSCwJuSwF1vIh/l B/cDfnPhYM7fDoD7ybs2xQoXN2sC3kG2e5l/PNvMFs5ipdeCdZbNoqkaDCrX84iD0PnObWRMSOm Eh7IOQHXyQ5rmg6bKDg8B+O33pGO57uqNIXxUM9u9m78lLFn1ej2p2dd6/eszNgmUgKGrzKEaLv 4SmqBsuEonKmKwZuNPjwd0m6ahKS10uHOfF2Ksm+zvR64gW1/jDArLbDHHiDpc/n1SU/LG3trdH uECk773M+u7EvlWOLQw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDA4NiBTYWx0ZWRfX0g4BYqxKBMIT 9xhYM/lOCREwaCM7q5US6z5I3T0iuI8om5v5APvM017opjL7tTiE8QV1+R5cQ0/WqtjQEvFVzg1 dAvuNlqsgY/6yBX9F55ScsB79tMHAyM= X-Proofpoint-ORIG-GUID: 1437t2XGssyxfd9ZgtZ-yPzL6PVg0aRt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_01,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110086 On 5/25/26 9:49 AM, Bryan O'Donoghue wrote: > On 25/05/2026 08:06, Jagadeesh Kona wrote: >>> That's not in your overview letter so generally I'd advise to include things like "did X because Y" - "didn't do Q because Z" anyway, how does it make a difference if the values are static ? >>> >>> They are no less magic numbers that way. >>> >>> What exactly is the resistance to defining the bits ? >>> >>> I'll state again - when a vendor is submitting something upstream where that vendor 100% controls their own documentation - there's no reason at all to be presenting magic hex numbers - even more the case with generated code. >>> >>> Just update the script to enumerate the bit fields, I honestly don't get the aversion. >>> >> Hi Bryan, >> >> There’s no standard interface for these bits, and bit definitions/fields vary across PLL types. >> So, common macros aren’t feasible and would need redefinitions per controller. Since these bits >> are not reused elsewhere > > - Asking for named bits not common macros > - Reuse isn't why you name a bit > > , IMO directly using values from the hardware documentation keeps the >> implementation simpler, avoids unnecessary abstraction, and makes debugging—through direct >> comparison with the hardware spec easier. > > How are hex values in upstream code easier to debug ? > > Without the spec you can't change or understand hex values in upstream code, which is the whole point I'm making here. I get the 'understanding' part, but regarding change, as I said previously, these must remain as-is - any difference for a PLL impacts every single clock downstream of it. Some of them also correspond to specific electrical properties, just like with PHY init sequences. The existing values are a result of tuning and silicon validation across presumably many, many chip units. There may be updates (very rarely post the chip going into production), but I'd assume these would go through the same testing procedures Konrad