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AJvYcCXwFjk7DBeq1kotYfF5o29aAHGKoCRL6xgCCvzDlsCazS4FcwGoqxrs8rtg432FQbcox+I20P1B7wr6r0krP+ncGItOBZ9U0JxVPg== X-Gm-Message-State: AOJu0YwX5Jnb8gSrYpE7wG35YRhl/lXZD17kGSlIHHQgbtgkYeSF6I0i j8WlmwP6ZagtR3s/hxXkpa0Pmlo7UufePpnLOg2OR7GdXecmgImFSFtDadwyx98= X-Google-Smtp-Source: AGHT+IGqE47uiLD78T1yQU2qNPN6dVRDsaT5Rxu1kmz28dCgLQ7tsFftgT+1AISRebYrTKMrx/S7WA== X-Received: by 2002:a17:906:b094:b0:a3c:a4ba:7917 with SMTP id x20-20020a170906b09400b00a3ca4ba7917mr11807476ejy.0.1708538179316; Wed, 21 Feb 2024 09:56:19 -0800 (PST) Received: from [192.168.2.107] ([79.115.63.202]) by smtp.gmail.com with ESMTPSA id qo3-20020a170907874300b00a3e4efbfdacsm4234766ejc.225.2024.02.21.09.56.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Feb 2024 09:56:18 -0800 (PST) Message-ID: <10f692ae-ac7a-4243-aadc-80712f781d39@linaro.org> Date: Wed, 21 Feb 2024 17:56:16 +0000 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 12/12] spi: s3c64xx: switch exynos850 to new port config data Content-Language: en-US To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org References: <20240216070555.2483977-1-tudor.ambarus@linaro.org> <20240216070555.2483977-13-tudor.ambarus@linaro.org> From: Tudor Ambarus In-Reply-To: <20240216070555.2483977-13-tudor.ambarus@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hey, Sam, On 2/16/24 07:05, Tudor Ambarus wrote: > Exynos850 has the same version of USI SPI (v2.1) as GS101. I tested GS101 and it worked, I guess exynos850 SPI shall work too as it uses the same SPI version, v2.1. Can you run a test on your side too see if works? If not, Mark can drop this patch I guess. Please let us know your preference. Cheers, ta > Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port > config data. > > Backward compatibility with DT is not broken because when alises are > set: > - the SPI core will set the bus number according to the alias ID > - the FIFO depth is always the same size for exynos850 (64 bytes) no > matter the alias ID number. > > Advantages of the change: > - drop dependency on the OF alias ID. > - FIFO depth is inferred from the compatible. Exynos850 integrates 3 SPI > IPs, all with 64 bytes FIFO depths. > - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial > masks is misleading and can hide problems of the driver logic. > > Just compiled tested. > > Signed-off-by: Tudor Ambarus > --- > drivers/spi/spi-s3c64xx.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index 784786407d2e..9fcbe040cb2f 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -1576,10 +1576,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { > }; > > static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { > - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ > - .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, > - /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ > - .rx_lvl_offset = 15, > + .fifo_depth = 64, > + .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, > + .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, > .tx_st_done = 25, > .clk_div = 4, > .high_speed = true,