[PATCH 0/7] ARM: dts: rockchip: add Utgard Mali nodes for some socs

[PATCH 0/7] ARM: dts: rockchip: add Utgard Mali nodes for some socs

[Heiko Stuebner]

This adds a mali-supply similar to the Midgard binding, the
compatibles for 3 Rockchip socs and the nodes for these.

The rk3036 and rk3188 gpus were tested, on the boards that
get their gpus enabled, using the current Lima resurrection
project and were able to probe the gpus sucessfully.

The only special thing Rockchip Malis do, is that all MMUs have
a shared interrupt and all PPs also have a shared interrupt, but
that works out well with the current binding.


Heiko Stuebner (7):
  dt-bindings: gpu: mali-utgard: Add Rockchip Utgard Malis
  dt-bindings: gpu: mali-utgard: add optional supply regulator
  ARM: dts: rockchip: add rk3036 gpu node
  ARM: dts: rockchip: enable the gpu on rk3036-kylin boards
  ARM: dts: rockchip: add rk322x gpu node
  ARM: dts: rockchip: add gpu nodes on rk3066/rk3188
  ARM: dts: rockchip: enable gpu on rk3188-radxarock

 .../devicetree/bindings/gpu/arm,mali-utgard.txt    | 10 +++++++++
 arch/arm/boot/dts/rk3036-kylin.dts                 |  5 +++++
 arch/arm/boot/dts/rk3036.dtsi                      | 19 +++++++++++++++++
 arch/arm/boot/dts/rk3066a.dtsi                     | 24 ++++++++++++++++++++++
 arch/arm/boot/dts/rk3188-radxarock.dts             |  4 ++++
 arch/arm/boot/dts/rk3188.dtsi                      | 24 ++++++++++++++++++++++
 arch/arm/boot/dts/rk322x.dtsi                      | 21 +++++++++++++++++++
 arch/arm/boot/dts/rk3xxx.dtsi                      | 11 ++++++++++
 8 files changed, 118 insertions(+)

-- 
2.14.1

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[PATCH 1/7] dt-bindings: gpu: mali-utgard: Add Rockchip Utgard Malis

[Heiko Stuebner]

Some (older or lower power) Rockchip socs use Utgard-based Mali-GPUs.
So add the necessary compatibles for them. As the setup is the same for
all of them (needing only the additional reset line), they get added in
a somewhat condensed form, to not inflate the document unnecessary.

Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index 2b6243e730f6..3b7f6f72f032 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -58,6 +58,13 @@ to specify one more vendor-specific compatible, among:
     Required properties:
       * resets: phandle to the reset line for the GPU
 
+  - rockchip,rk3036-mali
+  - rockchip,rk3066-mali
+  - rockchip,rk3188-mali
+  - rockchip,rk3228-mali
+    Required properties:
+      * resets: phandle to the reset line for the GPU
+
   - stericsson,db8500-mali
     Required properties:
       * interrupt-names and interrupts:
-- 
2.14.1

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[PATCH 2/7] dt-bindings: gpu: mali-utgard: add optional supply regulator

[Heiko Stuebner]

Mali GPUs have a separate supplying regulator in a lot of socs,
so describe a mali-supply property. The already described
operating points will likely also need access to this regulator.

Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index 3b7f6f72f032..bcaa640c883f 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -39,6 +39,9 @@ Optional properties:
     Memory region to allocate from, as defined in
     Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
 
+  - mali-supply : Phandle to regulator for the Mali device. Refer to
+    Documentation/devicetree/bindings/regulator/regulator.txt for details.
+
   - operating-points-v2:
     Operating Points for the GPU, as defined in
     Documentation/devicetree/bindings/opp/opp.txt
-- 
2.14.1

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[PATCH 3/7] ARM: dts: rockchip: add rk3036 gpu node

[Heiko Stuebner]

The rk3036 uses a Mali400 GPU with one pixel processor.
This adds the core node for it, which can be enabled
in board devicetrees.

Rockchip Mali GPUs use only one clock line for both bus and core.

Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
 arch/arm/boot/dts/rk3036.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 4916c65e0ace..5b084c0143ce 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -152,6 +152,25 @@
 		};
 	};
 
+	gpu: gpu@10090000 {
+		compatible = "rockchip,rk3036-mali", "arm,mali-400";
+		reg = <0x10090000 0x10000>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gp",
+				  "gpmmu",
+				  "pp0",
+				  "pp0mmu";
+		assigned-clocks = <&cru SCLK_GPU>;
+		assigned-clock-rates = <100000000>;
+		clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
+		clock-names = "core", "bus";
+		resets = <&cru SRST_GPU>;
+		status = "disabled";
+	};
+
 	vop: vop@10118000 {
 		compatible = "rockchip,rk3036-vop";
 		reg = <0x10118000 0x19c>;
-- 
2.14.1

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[PATCH 4/7] ARM: dts: rockchip: enable the gpu on rk3036-kylin boards

[Heiko Stuebner]

Enable the gpu node and add the gpu supply for it.

Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
 arch/arm/boot/dts/rk3036-kylin.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index fdb1570bc7d3..e2a0f576946f 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -135,6 +135,11 @@
 	status = "okay";
 };
 
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
 &hdmi {
 	status = "okay";
 };
-- 
2.14.1

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[PATCH 5/7] ARM: dts: rockchip: add rk322x gpu node

[Heiko Stuebner]

The rk3228/3229 uses a Mali400 GPU with two pixel processors.
This adds the core node for it, which can be enabled
in board devicetrees.

Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
 arch/arm/boot/dts/rk322x.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 06814421eed2..c97287ebb0ea 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -558,6 +558,27 @@
 		status = "disabled";
 	};
 
+	gpu: gpu@20000000 {
+		compatible = "rockchip,rk3228-mali", "arm,mali-400";
+		reg = <0x20000000 0x10000>;
+		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gp",
+				  "gpmmu",
+				  "pp0",
+				  "pp0mmu",
+				  "pp1",
+				  "pp1mmu";
+		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+		clock-names = "core", "bus";
+		resets = <&cru SRST_GPU_A>;
+		status = "disabled";
+	};
+
 	vpu_mmu: iommu@20020800 {
 		compatible = "rockchip,iommu";
 		reg = <0x20020800 0x100>;
-- 
2.14.1

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[PATCH 6/7] ARM: dts: rockchip: add gpu nodes on rk3066/rk3188

[Heiko Stuebner]

The old Cortex-A9 socs use Mali400 GPUs with 4 pixel processors.
This adds the core gpu nodes with the per-soc interrupts but sharing
the core node.

Rockchip SoCs use only one clock to supply the GPUs

Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
 arch/arm/boot/dts/rk3066a.dtsi | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/rk3188.dtsi  | 24 ++++++++++++++++++++++++
 arch/arm/boot/dts/rk3xxx.dtsi  | 11 +++++++++++
 3 files changed, 59 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index f50481fd8e5c..b76119dd5733 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -610,6 +610,30 @@
 	};
 };
 
+&gpu {
+	compatible = "rockchip,rk3066-mali", "arm,mali-400";
+	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "gp",
+			  "gpmmu",
+			  "pp0",
+			  "pp0mmu",
+			  "pp1",
+			  "pp1mmu",
+			  "pp2",
+			  "pp2mmu",
+			  "pp3",
+			  "pp3mmu";
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_xfer>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 1399bc04ea77..9e24d0ffadac 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -553,6 +553,30 @@
 	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 };
 
+&gpu {
+	compatible = "rockchip,rk3188-mali", "arm,mali-400";
+	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "gp",
+			  "gpmmu",
+			  "pp0",
+			  "pp0mmu",
+			  "pp1",
+			  "pp1mmu",
+			  "pp2",
+			  "pp2mmu",
+			  "pp3",
+			  "pp3mmu";
+};
+
 &i2c0 {
 	compatible = "rockchip,rk3188-i2c";
 	pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 0e718508a3bc..7458047f5fd5 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -117,6 +117,17 @@
 		clock-output-names = "xin24m";
 	};
 
+	gpu: gpu@10090000 {
+		compatible = "arm,mali-400";
+		reg = <0x10090000 0x10000>;
+		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+		clock-names = "core", "bus";
+		assigned-clocks = <&cru ACLK_GPU>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_GPU>;
+		status = "disabled";
+	};
+
 	L2: l2-cache-controller@10138000 {
 		compatible = "arm,pl310-cache";
 		reg = <0x10138000 0x1000>;
-- 
2.14.1

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[PATCH 7/7] ARM: dts: rockchip: enable gpu on rk3188-radxarock

[Heiko Stuebner]

Enable the gpu node on that board.

Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
---
 arch/arm/boot/dts/rk3188-radxarock.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 53d6fc2fdbce..00e05a6662ac 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -176,6 +176,10 @@
 	cpu0-supply = <&vdd_arm>;
 };
 
+&gpu {
+	status = "okay";
+};
+
 &i2c1 {
 	status = "okay";
 	clock-frequency = <400000>;
-- 
2.14.1

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Re: [PATCH 1/7] dt-bindings: gpu: mali-utgard: Add Rockchip Utgard Malis

[Rob Herring]

On Tue, Sep 05, 2017 at 12:57:33PM +0200, Heiko Stuebner wrote:
> Some (older or lower power) Rockchip socs use Utgard-based Mali-GPUs.
> So add the necessary compatibles for them. As the setup is the same for
> all of them (needing only the additional reset line), they get added in
> a somewhat condensed form, to not inflate the document unnecessary.
> 
> Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> index 2b6243e730f6..3b7f6f72f032 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> @@ -58,6 +58,13 @@ to specify one more vendor-specific compatible, among:
>      Required properties:
>        * resets: phandle to the reset line for the GPU
>  
> +  - rockchip,rk3036-mali
> +  - rockchip,rk3066-mali
> +  - rockchip,rk3188-mali
> +  - rockchip,rk3228-mali

Need to list the compatibles in the compatible property section. You can 
say "Rockchip variants" or something here.

> +    Required properties:
> +      * resets: phandle to the reset line for the GPU
> +
>    - stericsson,db8500-mali
>      Required properties:
>        * interrupt-names and interrupts:
> -- 
> 2.14.1
> 
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Re: [PATCH 2/7] dt-bindings: gpu: mali-utgard: add optional supply regulator

[Rob Herring]

On Tue, Sep 05, 2017 at 12:57:34PM +0200, Heiko Stuebner wrote:
> Mali GPUs have a separate supplying regulator in a lot of socs,
> so describe a mali-supply property. The already described
> operating points will likely also need access to this regulator.
> 
> Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> index 3b7f6f72f032..bcaa640c883f 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> @@ -39,6 +39,9 @@ Optional properties:
>      Memory region to allocate from, as defined in
>      Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
>  
> +  - mali-supply : Phandle to regulator for the Mali device. Refer to
> +    Documentation/devicetree/bindings/regulator/regulator.txt for details.

Wouldn't a power domain be more appropriate?

> +
>    - operating-points-v2:
>      Operating Points for the GPU, as defined in
>      Documentation/devicetree/bindings/opp/opp.txt
> -- 
> 2.14.1
> 
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Re: [PATCH 2/7] dt-bindings: gpu: mali-utgard: add optional supply regulator

[Heiko Stübner]

Hi Rob,

Am Dienstag, 12. September 2017, 17:09:20 CEST schrieb Rob Herring:
> On Tue, Sep 05, 2017 at 12:57:34PM +0200, Heiko Stuebner wrote:
> > Mali GPUs have a separate supplying regulator in a lot of socs,
> > so describe a mali-supply property. The already described
> > operating points will likely also need access to this regulator.
> > 
> > Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> > ---
> > 
> >  Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> > b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index
> > 3b7f6f72f032..bcaa640c883f 100644
> > --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> > 
> > @@ -39,6 +39,9 @@ Optional properties:
> >      Memory region to allocate from, as defined in
> >      Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
> > 
> > +  - mali-supply : Phandle to regulator for the Mali device. Refer to
> > +    Documentation/devicetree/bindings/regulator/regulator.txt for
> > details.
> 
> Wouldn't a power domain be more appropriate?

At least on Rockchip socs there is a power-domain, but also the separate 
additional regulator. See the similar mali-midgard binding.


Heiko
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Re: [PATCH 2/7] dt-bindings: gpu: mali-utgard: add optional supply regulator

[Rob Herring]

On Wed, Sep 13, 2017 at 12:12:24AM +0200, Heiko Stübner wrote:
> Hi Rob,
> 
> Am Dienstag, 12. September 2017, 17:09:20 CEST schrieb Rob Herring:
> > On Tue, Sep 05, 2017 at 12:57:34PM +0200, Heiko Stuebner wrote:
> > > Mali GPUs have a separate supplying regulator in a lot of socs,
> > > so describe a mali-supply property. The already described
> > > operating points will likely also need access to this regulator.
> > > 
> > > Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> > > ---
> > > 
> > >  Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 3 +++
> > >  1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> > > b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index
> > > 3b7f6f72f032..bcaa640c883f 100644
> > > --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> > > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> > > 
> > > @@ -39,6 +39,9 @@ Optional properties:
> > >      Memory region to allocate from, as defined in
> > >      Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
> > > 
> > > +  - mali-supply : Phandle to regulator for the Mali device. Refer to
> > > +    Documentation/devicetree/bindings/regulator/regulator.txt for
> > > details.
> > 
> > Wouldn't a power domain be more appropriate?
> 
> At least on Rockchip socs there is a power-domain, but also the separate 
> additional regulator. See the similar mali-midgard binding.

And that regulator's state is independent of the power domain's state? 

But I guess OPPs need a regulator. Really we should allow OPPs to be 
tied to the power domain. Maybe we do, I can't keep up with the ever 
evolving PM stuff.

So, given we already have it for midgard,

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Rob
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Re: [PATCH 2/7] dt-bindings: gpu: mali-utgard: add optional supply regulator

[Heiko Stuebner]

Am Mittwoch, 13. September 2017, 09:34:15 CEST schrieb Rob Herring:
> On Wed, Sep 13, 2017 at 12:12:24AM +0200, Heiko Stübner wrote:
> > Hi Rob,
> > 
> > Am Dienstag, 12. September 2017, 17:09:20 CEST schrieb Rob Herring:
> > > On Tue, Sep 05, 2017 at 12:57:34PM +0200, Heiko Stuebner wrote:
> > > > Mali GPUs have a separate supplying regulator in a lot of socs,
> > > > so describe a mali-supply property. The already described
> > > > operating points will likely also need access to this regulator.
> > > > 
> > > > Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> > > > ---
> > > > 
> > > >  Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 3 +++
> > > >  1 file changed, 3 insertions(+)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> > > > b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index
> > > > 3b7f6f72f032..bcaa640c883f 100644
> > > > --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> > > > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
> > > > 
> > > > @@ -39,6 +39,9 @@ Optional properties:
> > > >      Memory region to allocate from, as defined in
> > > >      Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
> > > > 
> > > > +  - mali-supply : Phandle to regulator for the Mali device. Refer to
> > > > +    Documentation/devicetree/bindings/regulator/regulator.txt for
> > > > details.
> > > 
> > > Wouldn't a power domain be more appropriate?
> > 
> > At least on Rockchip socs there is a power-domain, but also the separate 
> > additional regulator. See the similar mali-midgard binding.
> 
> And that regulator's state is independent of the power domain's state? 
>
> But I guess OPPs need a regulator. Really we should allow OPPs to be 
> tied to the power domain. Maybe we do, I can't keep up with the ever 
> evolving PM stuff.

Yep, the external gpu regulator state is completely independent of the
power-domain inside the soc and is most of the time one of the regulators
coming from the external pmic or sometimes even a completely separate
i2c-connected ic.

It's the same for the cpu cores on Rockchip socs, they have power-domains
for controlling the actual on/off state and need separate supplying
i2c-connected regulators that still have to be enabled on their own.


> So, given we already have it for midgard,
> 
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Thanks, added for v2.

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