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Thu, 27 Jun 2024 16:23:34 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 09FE74002D; Thu, 27 Jun 2024 16:23:29 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B888B220B57; Thu, 27 Jun 2024 16:22:42 +0200 (CEST) Received: from [10.48.86.79] (10.48.86.79) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 27 Jun 2024 16:22:42 +0200 Message-ID: <1139b106-1c05-44ba-9dac-649bcc8d9315@foss.st.com> Date: Thu, 27 Jun 2024 16:22:41 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 12/12] arm64: dts: st: add HPDMA nodes on stm32mp251 To: Amelie Delaunay , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin CC: , , , , , References: <20240531150712.2503554-1-amelie.delaunay@foss.st.com> <20240531150712.2503554-13-amelie.delaunay@foss.st.com> Content-Language: en-US From: Alexandre TORGUE In-Reply-To: <20240531150712.2503554-13-amelie.delaunay@foss.st.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-27_11,2024-06-27_03,2024-05-17_01 Hi Amélie On 5/31/24 17:07, Amelie Delaunay wrote: > The High Performance Direct Memory Access (HPDMA) controller is used to > perform programmable data transfers between memory-mapped peripherals > and memories (or between memories) via linked-lists. > > There are 3 instances of HPDMA on stm32mp251, using stm32-dma3 driver, with > 16 channels per instance and with one interrupt per channel. > Channels 0 to 7 are implemented with a FIFO of 8 bytes. > Channels 8 to 11 are implemented with a FIFO of 32 bytes. > Channels 12 to 15 are implemented with a FIFO of 128 bytes. > Thanks to stm32-dma3 bindings, the user can ask for a channel with specific > FIFO size. > > Signed-off-by: Amelie Delaunay > --- > v4: use SCMI clocks now that they are available > > v2: use SoC specific compatible st,stm32mp25-dma3 > --- > arch/arm64/boot/dts/st/stm32mp251.dtsi | 69 ++++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi > index dcd0656d67a8..d057dcee2534 100644 > --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi > +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi > @@ -107,6 +107,75 @@ soc@0 { > interrupt-parent = <&intc>; ... Applied on stm32-next. Thanks!! Alex