From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 461BF9479; Thu, 3 Oct 2024 07:01:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938896; cv=none; b=prJ6MjsRpc9eFt6oRyDFz9o7D9dlj/+p7THWsb6hiqLvWrtN41ALYDq6EnbLx3EMNELgebfbg/UO+rroHM06fBMzs5wwk9G3aMb4Xz3ewU830iUUiNOETUTXtoBBE1hnO5l/ucrqqkgoFECKOj3hztDq3Q8PmKqSfMC/9pZxjkg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938896; c=relaxed/simple; bh=w/1E+1RpWQxHFMN1YUQv6kHMHCMNVL2WNyQLnB/eCo8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=fOq6YDTrseWO+QCh6kQ75L0ikVGSfWA/oid9cqKbMrTS9uqtj8QqERmXsvTcrsLfoLak6cRLgpH/mE1WSXkmTtL1O1oFYrZu5bUuxYzK/cS1LqCcXEXCmfBYoAlLvyfUIyCaHjwfIlT97LtAYEB9IJ72vQm2Tb1U9PziZMsube8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Jd1ByyQc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Jd1ByyQc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C070C4CEC7; Thu, 3 Oct 2024 07:01:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727938895; bh=w/1E+1RpWQxHFMN1YUQv6kHMHCMNVL2WNyQLnB/eCo8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Jd1ByyQch7WaIc9oKMoSCW2VynZDBdzkFys7IljGpM8aH8jU0DST1ZW3pR+B2PLUf Unzt6/89v4REmJbHTcguilLv89mdenK58PdzfofEWy2aoQOS4I6LxugvloW354kSti y3RNH01h4GtTLcy7W3ixSoc+KmScEw8yFsY0vayeUYEm2UiEEu+KWuEIbMYrUB45xs ERuPUtEMfLuJdFvt8I7Ugy0IxXRelkAVJ0Cd0yhq5zwbd1Rwc5rfT4yFRmnXmTCY8t 3GtMDdGt8D4VhqZUKnaLfZffdNWsabBRfx8NGPoF4FUyf3VAmHg45o+mb3bJKmjdPm q851wjfizvVKw== Message-ID: <1195de0e-4a14-446f-bd1f-0116d4abf18b@kernel.org> Date: Thu, 3 Oct 2024 09:01:29 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] dt-bindings: spi: xilinx: Add clocks & clock-names properties To: "Mahapatra, Amit Kumar" , Conor Dooley Cc: "broonie@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "Simek, Michal" , "linux-spi@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "git (AMD-Xilinx)" , "amitrkcian2002@gmail.com" References: <20240923123242.2101562-1-amit.kumar-mahapatra@amd.com> <20240924-impaired-starving-eef91b339f67@spud> <20240925-trapdoor-stunt-33516665fdc5@spud> <03a1c7e7-c516-41ab-a668-7c6785ab1c4f@kernel.org> <20240928-postcard-lively-c0c9bbe74d04@spud> <20240930-unbalance-wake-e1a6f07ea79d@spud> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 03/10/2024 08:23, Mahapatra, Amit Kumar wrote: > Hello Conor, > >> -----Original Message----- >> From: Conor Dooley >> Sent: Monday, September 30, 2024 10:10 PM >> To: Mahapatra, Amit Kumar >> Cc: Krzysztof Kozlowski ; broonie@kernel.org; robh@kernel.org; >> krzk+dt@kernel.org; conor+dt@kernel.org; Simek, Michal >> ; linux-spi@vger.kernel.org; devicetree@vger.kernel.org; >> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; git (AMD-Xilinx) >> ; amitrkcian2002@gmail.com >> Subject: Re: [PATCH] dt-bindings: spi: xilinx: Add clocks & clock-names properties >> >> On Mon, Sep 30, 2024 at 03:44:47PM +0000, Mahapatra, Amit Kumar wrote: >>> Hello Conor, >>> >>>>>>>>> Subject: Re: [PATCH] dt-bindings: spi: xilinx: Add clocks & >>>>>>>>> clock-names properties >>>>>>>>> >>>>>>>>> On Mon, Sep 23, 2024 at 06:02:42PM +0530, Amit Kumar Mahapatra >> wrote: >>>>>>>>>> Include the 'clocks' and 'clock-names' properties in the AXI >>>>>>>>>> Quad-SPI bindings. When the AXI4-Lite interface is enabled, >>>>>>>>>> the core operates in legacy mode, maintaining backward >>>>>>>>>> compatibility with version 1.00, and uses 's_axi_aclk' and >>>>>>>>>> 'ext_spi_clk'. For the AXI interface, it uses 's_axi4_aclk' and >> 'ext_spi_clk'. >>>> >>>>>>>>>> + properties: >>>>>>>>>> + clock-names: >>>>>>>>>> + items: >>>>>>>>>> + - const: s_axi_aclk >>>>>>>>>> + - const: ext_spi_clk >>>>>>>>> >>>>>>>>> These are all clocks, there should be no need to have "clk" in the names. >>>>>>>> >>>>>>>> These are the names exported by the IP and used by the DTG. >>>>>>> >>>>>>> So? This is a binding, not a verilog file. >>>>>> >>>>>> Axi Quad SPI is an FPGA-based IP, and the clock names are >>>>>> derived from the IP signal names as specified in the IP documentation [1]. >>>>>> We chose these names to ensure alignment with the I/O signal >>>>>> names listed in Table 2-2 on page 19 of [1]. >>>>>> >>>>>> [1] >>>>>> chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/https://www.amd. >>>>>> com/content/dam/xilinx/support/documents/ip_documentation/axi_qu >>>>>> ad_s >>>>>> pi/v3_2/pg153-axi-quad-spi.pdf >>>>> >>>>> So if hardware engineers call them "pink_pony_clk_aclk_really_clk" >>>>> we should follow... >>>>> >>>>> - bus or axi >>>>> - ext_spi or spi >>>>> >>>>> You have descriptions of each item to reference real signals. >>>>> Conor's comment is valid - do no make it verilog file. >>>>> >>>>>> >>>>>>> >>>>>>>>>> + >>>>>>>>>> + else: >>>>>>>>>> + properties: >>>>>>>>>> + clock-names: >>>>>>>>>> + items: >>>>>>>>>> + - const: s_axi4_aclk >>>>>>>>>> + - const: ext_spi_clk >>>>> >>>>> Nah, these are the same. >>>> >>>> They may be different, depending on whether or not the driver has to >>>> handle "axi4- lite" versus "axi" differently. That said, I find the >>>> commit message kinda odd in that it states that axi4-lite goes with the s_axi_aclk >> clock and axi goes with s_axi4_aclk. >>> >>> Apologies for the typo. When the AXI4 interface is enabled, it uses >>> s_axi4_aclk, and when the AXI4-Lite interface is enabled, it uses s_axi_aclk. >>> >>> In my next series I will update my commit message & change the >>> clock-names 's_axi4_aclk', 's_axi_aclk' & 'ext_spi_clk' to 'axi4', >>> 'axi' & 'ref' respectively >> >> There's no driver here, so it is hard to know (why isn't there?) - are you using the axi > > We are working on the driver. Once it is ready we will send it to upstream. Why would you send separate binding from driver? That's only making everything more difficult... > >> v axi4 to do some sort of differentiation in the driver? > In the driver we don't do any different operations based on the clocks , > we simply enable the available clocks in the driver. So it is the same clock? Best regards, Krzysztof