From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jerome Brunet <jbrunet@baylibre.com>
Cc: Xianwei Zhao <xianwei.zhao@amlogic.com>,
Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Bartosz Golaszewski <brgl@bgdev.pl>,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/3] dt-bindings: pinctrl: Add support for Amlogic A4 SoCs
Date: Mon, 21 Oct 2024 08:32:40 +0200 [thread overview]
Message-ID: <119e86e4-acb4-455d-9b0b-ee851b621c91@kernel.org> (raw)
In-Reply-To: <8cb615cf-1b4e-49ba-91fc-6e1f5f57cd3c@kernel.org>
On 21/10/2024 08:31, Krzysztof Kozlowski wrote:
>>>>
>>>> reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
>>>>
>>>> And others will go in the driver to see that is maps to GPIOX_10 ? the number
>>>> being completly made up, with no link to anything HW/Datasheet
>>>> whatsoever ?
>>>>
>>>> This is how things should be done now ?
>>>
>>> Why would you need to do this? Why it cannot be <&gpio 10
>>> GPIO_ACTIVE_LOW>, assuming it is GPIO 10?
>>>
>>> Bindings have absolutely nothing to do with it. You have GPIO 10, not
>>> 42, right?
>>
>> That's what being proposed here, as far as I can see.
>>
>> GPIOX_10 (not GPIO 10) maps to 42. If this goes through, for DTs to be
>> valid in any OS, all need to share the same definition. That looks like
>> a binding to me.
>>
>> On these SOC, gpios in each controller are organized in bank with
>> different number of pins. So far, this was represented as single linear
>> array and that was not a problem since the mapping was part of the binding.
>>
>> Are you suggesting 2 params instead of one ? something like this maybe ?
>>
>> reset-gpios = <&gpio BANK_X 10 GPIO_ACTIVE_LOW>;
>
> No, I propose the same as you wrote:
> <&gpio 10 GPIO_ACTIVE_LOW>
>
> but I don't mind putting bank there.
>
>>
>> This means this A4 controller will be software incompatible with the
>> previous generation. It will need to handled differently eventhough the
>> HW is exactly the same.
>>
>> Note that some form of binding would still be required to define the
>> banks which are referenced by arbitrary letter in doc, not numbers.
>
> Usually banks are considered separate gpio controllers, so numbering
> always start from 0 because phandle encodes the bank.
>
> And this is exactly what Rob already asked in v1 review.
Ha, actually I misread his reply, I think he proposed your syntax:
<&gpio BANK_X 10 GPIO_ACTIVE_LOW>
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-10-21 6:32 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-18 8:10 [PATCH v3 0/3] Pinctrl: A4: Add pinctrl driver Xianwei Zhao via B4 Relay
2024-10-18 8:10 ` [PATCH v3 1/3] dt-bindings: pinctrl: Add support for Amlogic A4 SoCs Xianwei Zhao via B4 Relay
2024-10-18 8:28 ` Krzysztof Kozlowski
2024-10-18 8:39 ` Jerome Brunet
2024-10-18 9:01 ` Xianwei Zhao
2024-10-18 9:20 ` Jerome Brunet
2024-10-18 10:13 ` Krzysztof Kozlowski
2024-10-18 12:26 ` Jerome Brunet
2024-10-21 6:31 ` Krzysztof Kozlowski
2024-10-21 6:32 ` Krzysztof Kozlowski [this message]
2024-10-18 12:31 ` Neil Armstrong
2024-10-18 15:31 ` Krzysztof Kozlowski
2024-10-21 7:38 ` neil.armstrong
2024-10-21 9:56 ` Krzysztof Kozlowski
2024-10-21 10:38 ` neil.armstrong
2024-10-21 15:27 ` Krzysztof Kozlowski
2024-10-28 9:07 ` Xianwei Zhao
2024-10-28 9:09 ` neil.armstrong
2024-10-28 9:36 ` Xianwei Zhao
2024-10-28 9:46 ` neil.armstrong
2024-10-28 9:59 ` Xianwei Zhao
2024-10-28 10:44 ` neil.armstrong
2024-11-08 6:18 ` Xianwei Zhao
2024-10-18 8:10 ` [PATCH v3 2/3] pinctrl: meson: Add driver " Xianwei Zhao via B4 Relay
2024-10-18 15:51 ` Christophe JAILLET
2024-10-28 9:46 ` Xianwei Zhao
2024-10-18 8:10 ` [PATCH v3 3/3] arm64: dts: amlogic: a4: add pinctrl node Xianwei Zhao via B4 Relay
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