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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id b37-20020a05651c0b2500b0026dcac60624sm219926ljr.108.2022.10.01.03.01.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Oct 2022 03:01:56 -0700 (PDT) Message-ID: <11a99a84-47ec-ca3e-5781-0f17ed33dbf9@linaro.org> Date: Sat, 1 Oct 2022 12:01:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH 2/3] arm64: dts: qcom: sdm845-db845c: correct SPI2 pins drive strength Content-Language: en-US To: Doug Anderson Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Rob Clark , linux-arm-msm , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , "# 4.0+" References: <20220930182212.209804-1-krzysztof.kozlowski@linaro.org> <20220930182212.209804-2-krzysztof.kozlowski@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 30/09/2022 22:12, Doug Anderson wrote: > Hi, > > On Fri, Sep 30, 2022 at 11:22 AM Krzysztof Kozlowski > wrote: >> >> The pin configuration (done with generic pin controller helpers and >> as expressed by bindings) requires children nodes with either: >> 1. "pins" property and the actual configuration, >> 2. another set of nodes with above point. >> >> The qup_spi2_default pin configuration used second method - with a >> "pinmux" child. >> >> Fixes: 8d23a0040475 ("arm64: dts: qcom: db845c: add Low speed expansion i2c and spi nodes") >> Cc: >> Signed-off-by: Krzysztof Kozlowski >> >> --- >> >> Not tested on hardware. >> --- >> arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts >> index 132417e2d11e..a157eab66dee 100644 >> --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts >> +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts >> @@ -1123,7 +1123,9 @@ &wifi { >> >> /* PINCTRL - additions to nodes defined in sdm845.dtsi */ >> &qup_spi2_default { >> - drive-strength = <16>; >> + pinmux { >> + drive-strength = <16>; >> + }; > > The convention on Qualcomm boards of this era is that muxing (setting > the function) is done under a "pinmux" node and, unless some of the > pins need to be treated differently like for the UARTs, configuration > (bias, drive strength, etc) is done under a "pinconf" subnode. Yes, although this was not expressed in bindings. > I > believe that the "pinconf" subnode also needs to replicate the list of > pins, or at least that's what we did everywhere else on sdm845 / > sc7180. Yes. > > Thus to match conventions, I assume you'd do: > > &qup_spi2_default { > pinconf { No, because I want a convention of all pinctrl bindings and drivers, not convention of old pinctrl ones. The new ones are already moved or being moved to "-state" and "-pins". In the same time I am also unifying the requirement of "function" property - enforcing it in each node, thus "pinconf" will not be valid anymore. > pins = "gpio27", "gpio28", "gpio29", "gpio30"; > drive-strength = <16>; > }; > }; > > We've since moved away from this to a less cumbersome approach, but > for "older" boards like db845c we should probably match the existing > convention, or have a flag day and change all sdm845 boards over to > the new convention. That's what my next patchset from yesterday was doing. Unifying the bindings with modern bindings and converting DTS to match them. https://lore.kernel.org/linux-devicetree/20220930200529.331223-1-krzysztof.kozlowski@linaro.org/T/#t Best regards, Krzysztof