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[88.156.142.199]) by smtp.gmail.com with ESMTPSA id s24-20020a056512203800b0048ad4c718f3sm713281lfs.30.2022.11.06.05.58.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 06 Nov 2022 05:58:42 -0800 (PST) Message-ID: <11c5aea8-bc31-c924-9f73-2138096c1bab@linaro.org> Date: Sun, 6 Nov 2022 14:58:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [RFC][PATCH v3 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms Content-Language: en-US To: Marek Vasut , devicetree@vger.kernel.org Cc: Fabio Estevam , Krzysztof Kozlowski , Lucas Stach , Richard Zhu , Rob Herring , Shawn Guo , linux-arm-kernel@lists.infradead.org, NXP Linux Team References: <20221104170417.232132-1-marex@denx.de> <20221104170417.232132-3-marex@denx.de> From: Krzysztof Kozlowski In-Reply-To: <20221104170417.232132-3-marex@denx.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 04/11/2022 18:04, Marek Vasut wrote: > The i.MX6 and i.MX7D does not use block controller to toggle PCIe > reset, hence the PCIe DT description contains three reset entries > on these older SoCs. Add this exception into the binding document. > > Signed-off-by: Marek Vasut > --- > Cc: Fabio Estevam > Cc: Krzysztof Kozlowski > Cc: Lucas Stach > Cc: Richard Zhu > Cc: Rob Herring > Cc: Shawn Guo > Cc: linux-arm-kernel@lists.infradead.org > Cc: NXP Linux Team > To: devicetree@vger.kernel.org > --- > V2: - Add mx8mq to 3-reset PCIe core variant > - Handle the resets in allOf section > V3: - Reinstate reset: maxItems:3 and add minItems:2 > - Move reset-names back to main section > - The validation no longer works and introduces errors like these: > arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: reset-names:0: 'pciephy' was expected > --- > .../bindings/pci/fsl,imx6q-pcie.yaml | 25 +++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > index 5d731aca34b4d..44a1404cbc2c0 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -80,11 +80,13 @@ properties: > - const: pcie_phy > > resets: > + minItems: 2 > maxItems: 3 > description: Phandles to PCIe-related reset lines exposed by SRC > IP block. Additional required by imx7d-pcie and imx8mq-pcie. > > reset-names: > + minItems: 2 > items: > - const: pciephy > - const: apps > @@ -251,6 +253,29 @@ allOf: > maxItems: 1 > power-domain-names: false > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx6q-pcie > + - fsl,imx6sx-pcie > + - fsl,imx6qp-pcie > + - fsl,imx7d-pcie > + - fsl,imx8mq-pcie > + then: > + properties: > + reset-names: > + maxItems: 3 In your patch v2, for such case you explicitly set both minItems and maxItems to the same value. Here you do not. Let's keep both min and max. Best regards, Krzysztof