From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A79A20ADF3; Fri, 11 Oct 2024 08:26:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728635160; cv=none; b=KVV2YoV1Bv4Ge9r+Y+Ge99b1axNHIzc3kyqEwVcUuz8CW9aZF2oEfJqfbT/jQazqdiiCVnJIn9CPcRtEQl+ij7JAggh1hnhA/5mcNq0amSuDTzMVkVWaRi4yGIrp+3XGE9XOV0IwVxJWvRU9K9AkbfwJl8fKh0DNpNBf2RY1H7Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728635160; c=relaxed/simple; bh=L50c2V8W/RlzvTod6zS7Wvye+fgjpftpYkVsG3RMnD4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=PGQnLDOxDpZSj7H3W33+3JrC80Kzn+9YZ54naxIvGVHWWa6uBcJCOKg7d+aLix9LFP3TLMDZt3j7RNjvFyBMmAhef9duVYGi+6jh55t8oEssNjKL5E7b1aGt2M5RPQ5g+5l03ig+T7aWd37NSjEGT520nj5oSq80ymEoGCUDcW0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KL1dfOjO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KL1dfOjO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D554C4CEC3; Fri, 11 Oct 2024 08:25:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728635160; bh=L50c2V8W/RlzvTod6zS7Wvye+fgjpftpYkVsG3RMnD4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=KL1dfOjOCZgmtryrJRAb/xQiK/Rt7bUOYOh1c+m/DeyeMtEyn/FIlOBzsboqo1N8J girR/BLuhyuqQg5zge8hM9ZY9s93a2RO5569JRtG7rY2f96N+Pqbc2dEg6GosBVS7w R4Ue3DvBF+cSICmJTJsBav/LNRDWW4+RjUFXXcaLydiNbmG8VXzOL0TdOOJQeZDhBN niI2eFtYbvO8TFbTfGl6Y3qNHjInn+EGt/I7D5/orjC/ajwQ3mgJP4FkYJXapZy2cV Xuu+q9PwqphttjtuMorvJsqll4lmnIeIolDGMalwFgbU/b36JPJ3VcONMhopriXtol Bn8o/8WXuJZ1Q== Message-ID: <11cf07c7-08d6-425d-9590-1afab6d052d2@kernel.org> Date: Fri, 11 Oct 2024 17:25:56 +0900 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 07/12] PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() MSI-X hiding To: Manivannan Sadhasivam Cc: Lorenzo Pieralisi , Kishon Vijay Abraham I , Shawn Lin , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Rick Wertenbroek , Wilfred Mallawa , Niklas Cassel References: <20241007041218.157516-1-dlemoal@kernel.org> <20241007041218.157516-8-dlemoal@kernel.org> <20241010072512.f7e4kdqcfe5okcvg@thinkpad> From: Damien Le Moal Content-Language: en-US Organization: Western Digital Research In-Reply-To: <20241010072512.f7e4kdqcfe5okcvg@thinkpad> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/10/24 16:25, Manivannan Sadhasivam wrote: > On Mon, Oct 07, 2024 at 01:12:13PM +0900, Damien Le Moal wrote: >> Move the code in rockchip_pcie_ep_probe() to hide the MSI-X capability >> to its own function, rockchip_pcie_ep_hide_msix_cap(). No functional >> changes. >> >> Signed-off-by: Damien Le Moal > > Reviewed-by: Manivannan Sadhasivam > > Btw, can someone from Rockchip confirm if this hiding is necessary for all the > SoCs? It looks to me like an SoC quirk. All SoCs ? Are there several versions of the RK3399 ? As far as I know, there is only one. This is unlike the designware IP block used in the RK3588 which can also be found in other SoC and may have some variations due to different synthesis parameters. -- Damien Le Moal Western Digital Research