From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Rob Clark <robdclark@gmail.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
devicetree@vger.kernel.org,
Neil Armstrong <neil.armstrong@linaro.org>
Subject: Re: [PATCH v2 3/7] drm/msm/adreno: Implement SMEM-based speed bin
Date: Tue, 25 Jun 2024 19:41:29 +0200 [thread overview]
Message-ID: <11e54c5d-a53b-40ec-b72e-db608ecfd23c@linaro.org> (raw)
In-Reply-To: <CAF6AEGvhkEWCtCKdRjhyk18+cxbn0QLkRUrMqEfgGU-c+K1YxQ@mail.gmail.com>
On 25.06.2024 7:20 PM, Rob Clark wrote:
> On Wed, Jun 5, 2024 at 1:10 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
[...]
>> struct adreno_speedbin {
>> - uint16_t fuse;
>> + /* <= 16-bit for NVMEM fuses, 32b for SOCID values */
>> + uint32_t fuse;
>> +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */
>> +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0)
>> +#define ADRENO_SKU_ID(fcode) (SOCINFO_PC_UNKNOWN << 16 | fcode)
>
> So, as I understand this, we are actually only using the feature-code,
> which is the low 16b. So in reality the "fuse" is still only 16b?
Right, a leftover from when the pcode was used too.. None of them should
exceed 16b.
Konrad
next prev parent reply other threads:[~2024-06-25 17:41 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-05 20:10 [PATCH v2 0/7] Add SMEM-based speedbin matching Konrad Dybcio
2024-06-05 20:10 ` [PATCH v2 1/7] soc: qcom: Move some socinfo defines to the header Konrad Dybcio
2024-06-05 20:10 ` [PATCH v2 2/7] soc: qcom: smem: Add a feature code getter Konrad Dybcio
2024-06-05 20:10 ` [PATCH v2 3/7] drm/msm/adreno: Implement SMEM-based speed bin Konrad Dybcio
2024-06-25 17:20 ` Rob Clark
2024-06-25 17:41 ` Konrad Dybcio [this message]
2024-06-05 20:10 ` [PATCH v2 4/7] drm/msm/adreno: Add speedbin data for SM8550 / A740 Konrad Dybcio
2024-06-25 17:21 ` Rob Clark
2024-06-25 17:45 ` Konrad Dybcio
2024-06-05 20:10 ` [PATCH v2 5/7] drm/msm/adreno: Define A530 speed bins explicitly Konrad Dybcio
2024-06-05 20:10 ` [PATCH v2 6/7] drm/msm/adreno: Redo the speedbin assignment Konrad Dybcio
2024-06-05 20:10 ` [PATCH v2 7/7] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Konrad Dybcio
2024-06-21 5:29 ` (subset) [PATCH v2 0/7] Add SMEM-based speedbin matching Bjorn Andersson
-- strict thread matches above, loose matches on Subject: below --
2024-04-17 20:02 Konrad Dybcio
2024-04-17 20:02 ` [PATCH v2 3/7] drm/msm/adreno: Implement SMEM-based speed bin Konrad Dybcio
2024-04-17 23:43 ` Dmitry Baryshkov
2024-04-18 9:51 ` Konrad Dybcio
2024-04-18 11:07 ` Dmitry Baryshkov
2024-04-18 11:31 ` Konrad Dybcio
2024-04-18 11:48 ` Dmitry Baryshkov
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