Re: [PATCH v2] arm64: dts: ti: k3-am642-sr-som: mux ethernet phy reset signals input

[Josua Mayer <josua@solid-run.com>]

Am 03.09.24 um 14:42 schrieb Nishanth Menon:
> On 11:52-20240903, Josua Mayer wrote:
>> Specifically on AM64 SoM design, the DP83869 phys have a chance to lock
>> up if reset gpio changes state. Update the pinmux to input-only,
>> strongly enforcing that these signals are left floating at all times.
>>
>> This avoids sporadic phy initialisation errors mostly encountered during
>> power-on and reset. In this state the phys respond to all mdio messages
>> with a constant response, recovering only after power-cycle.
>>
>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>> ---
>> Changes in v2:
>> - update commit message with additional details
>> - rebased on v6.11-rc1
>> - Link to v1: https://lore.kernel.org/r/20240704-am64-phy-lockup-v1-1-4a38ded44f9d@solid-run.com
>> ---
>>  arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>> index c19d0b8bbf0f..b1f06071df4c 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>> @@ -320,7 +320,7 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */
>>  	ethernet_phy0_default_pins: ethernet-phy0-default-pins {
>>  		pinctrl-single,pins = <
>>  			/* reset */
>> -			AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */
>> +			AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */
>>  			/* reference clock */
>>  			AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */
>>  		>;
>> @@ -329,7 +329,7 @@ AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */
>>  	ethernet_phy1_default_pins: ethernet-phy1-default-pins {
>>  		pinctrl-single,pins = <
>>  			/* reset */
>> -			AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */
>> +			AM64X_IOPAD(0x0150, PIN_INPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */
>>  			/* led0, external pull-down on SoM */
>>  			AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */
>>  			/* led1/rxer */
>> @@ -340,7 +340,7 @@ AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */
>>  	ethernet_phy2_default_pins: ethernet-phy2-default-pins {
>>  		pinctrl-single,pins = <
>>  			/* reset */
>> -			AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */
>> +			AM64X_IOPAD(0x00d4, PIN_INPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */
> PIN_INPUT is bi-directional despite what the name states.
Good point, I will try to measure the electrical signal during boot
and better understand what exactly happens.

Guess is there are glitches when either u-boot or linux
are changing the pinmux registers.
Hence whatever glitch-free value we end up picking for u-boot
should be reflected in linux dts also.

> Either way, it
> is a bit late for me to pick things up.
>
>>  			/* led0, external pull-down on SoM */
>>  			AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */
>>  			/* led1/rxer */
>>
>> ---
>> base-commit: 8400291e289ee6b2bf9779ff1c83a291501f017b
>> change-id: 20240704-am64-phy-lockup-107ea5ffa228
>>
>> Best regards,
>> -- 
>> Josua Mayer <josua@solid-run.com>
>>