From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFD73C10DCE for ; Tue, 24 Mar 2020 04:52:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9C70A20663 for ; Tue, 24 Mar 2020 04:52:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="JWe/d/Rh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725941AbgCXEwH (ORCPT ); Tue, 24 Mar 2020 00:52:07 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:61542 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725827AbgCXEwG (ORCPT ); Tue, 24 Mar 2020 00:52:06 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1585025525; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: References: Cc: To: From: Subject: Sender; bh=FUO2P5XLMY1BU2WaJp22Owb49Q1cP6EsFYl11OgO0lQ=; b=JWe/d/RhLTROw+IzPpmmmbDzHtaqx1a2VD+5otX3W37QBz5esHMYZ1OKMi1fCdt6r2GryViK X+WmnIzZUSQz1qKisGYfXcSvqL7Xh6A3vPeKBxCvpWafuMBs3HicEVyyC1u65AqDQpSLUTgk fmowBgSyXTmpWZw4A264lKukUWE= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e7991f5.7fd853bb21f0-smtp-out-n02; Tue, 24 Mar 2020 04:52:05 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 3B1EDC43636; Tue, 24 Mar 2020 04:52:05 +0000 (UTC) Received: from [10.206.24.160] (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sanm) by smtp.codeaurora.org (Postfix) with ESMTPSA id 04320C433CB; Tue, 24 Mar 2020 04:51:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 04320C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sanm@codeaurora.org Subject: Re: [PATCH v4 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings From: "Sandeep Maheswaram (Temp)" To: Stephen Boyd , Andy Gross , Bjorn Andersson , Doug Anderson , Felipe Balbi , Greg Kroah-Hartman , Mark Rutland , Matthias Kaehlcke , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manu Gautam References: <1581316605-29202-1-git-send-email-sanm@codeaurora.org> <1581316605-29202-2-git-send-email-sanm@codeaurora.org> <158137029351.121156.8319119424832255457@swboyd.mtv.corp.google.com> Message-ID: <123a100a-7185-f222-0067-aceacb8c2635@codeaurora.org> Date: Tue, 24 Mar 2020 10:21:57 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Stephen, Can you check my reply to the review comments and let me know how to proceeed. Thanks Sandeep On 3/13/2020 5:41 PM, Sandeep Maheswaram (Temp) wrote: > Hi Stephen, > > On 2/11/2020 3:01 AM, Stephen Boyd wrote: >> Quoting Sandeep Maheswaram (2020-02-09 22:36:44) >>> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml >>> b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml >>> new file mode 100644 >>> index 0000000..0353401 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml >>> @@ -0,0 +1,155 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm SuperSpeed DWC3 USB SoC controller >>> + >>> +maintainers: >>> +  - Manu Gautam >>> + >>> +properties: >>> +  compatible: >>> +    items: >>> +      - enum: >>> +          - qcom,msm8996-dwc3 >>> +          - qcom,msm8998-dwc3 >>> +          - qcom,sdm845-dwc3 >>> +      - const: qcom,dwc3 >>> + >>> +  reg: >>> +    description: Offset and length of register set for QSCRATCH >>> wrapper >>> +    maxItems: 1 >>> + >>> +  "#address-cells": >>> +    enum: [ 1, 2 ] >>> + >>> +  "#size-cells": >>> +    enum: [ 1, 2 ] >>> + >>> +  power-domains: >>> +    description: specifies a phandle to PM domain provider node >>> +    maxItems: 1 >>> + >>> +  clocks: >>> +    description: >>> +      A list of phandle and clock-specifier pairs for the clocks >>> +      listed in clock-names. >>> +    items: >>> +      - description: System Config NOC clock. >>> +      - description: Master/Core clock, has to be >= 125 MHz >>> +          for SS operation and >= 60MHz for HS operation. >>> +      - description: System bus AXI clock. >>> +      - description: Mock utmi clock needed for ITP/SOF generation >>> +          in host mode.Its frequency should be 19.2MHz. >> Please add a space between the end of sentence and next one. > will do in next version >> >>> +      - description: Sleep clock, used for wakeup when >>> +          USB3 core goes into low power mode (U3). >>> + >>> +  clock-names: >>> +    items: >>> +      - const: cfg_noc >>> +      - const: core >>> +      - const: iface >>> +      - const: mock_utmi >>> +      - const: sleep >>> + >>> +  assigned-clocks: >>> +    items: >>> +      - description: Phandle to MOCK_UTMI_CLK. >>> +      - description: Phandle to MASTER_CLK. >> It's a phandle and clock specifier pair, not always just a phandle. >> Maybe the base schema can enforce that somehow, but the description >> isn't accurate. > will do in next version >> >>> + >>> +  assigned-clock-rates: >>> +    items: >>> +      - description: Must be 19.2MHz (19200000). >>> +      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS >>> mode. >> Can this be more strict? I see in [1] that it was suggested to update >> the schema checker. Did you try that? > > Tried that but need to add maximum value also and even after that > getting some errors as below. > > /Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml: > usb@a6f8800: assigned-clock-rates: Additional items are not allowed > ([150000000] was unexpected) > > /local/mnt/workspace/sandeep/bu_build/src/third_party/kernel/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml: > usb@a6f8800: assigned-clock-rates:0: [19200000] is too short >> >>> + >>> +  resets: >>> +    maxItems: 1 >>> + >>> +  interrupts: >>> +    items: >>> +      - description: The interrupt that is asserted >>> +          when a wakeup event is received on USB2 bus. >>> +      - description: The interrupt that is asserted >>> +          when a wakeup event is received on USB3 bus. >>> +      - description: Wakeup event on DM line. >>> +      - description: Wakeup event on DP line. >>> + >>> +  interrupt-names: >>> +    items: >>> +      - const: hs_phy_irq >>> +      - const: ss_phy_irq >>> +      - const: dm_hs_phy_irq >>> +      - const: dp_hs_phy_irq >>> + >>> +  qcom,select-utmi-as-pipe-clk: >>> +    description: >>> +      If present, disable USB3 pipe_clk requirement. >>> +      Used when dwc3 operates without SSPHY and only >>> +      HS/FS/LS modes are supported. >>> +    type: boolean >>> + >>> +# Required child node: >>> + >>> +patternProperties: >>> +  "^dwc3@[0-9a-f]+$": >>> +    type: object >>> +    description: >>> +      A child node must exist to represent the core DWC3 IP block >>> +      The content of the node is defined in dwc3.txt. >>> + >>> +required: >>> +  - compatible >>> +  - reg >>> +  - "#address-cells" >>> +  - "#size-cells" >>> +  - power-domains >>> +  - clocks >>> +  - clock-names >> Why aren't interrupts required? They're always present, aren't they? > In qcom,dwc3.txt file interrupts are mentioned in Optional properties > and I also didnt find any interrupts in 8996.dtsi >> >>> + >>> +examples: >>> +  - | >>> +    #include >>> +    #include >> It would be good to include >> here too, just in case someone wants to move that include out of >> arm-gic.h, which is possible. >> >>> +    usb_1: usb@a6f8800 { >> Can we drop the phandle? It's not used. > will do in next version >> >>> +        compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; >>> +        reg = <0 0x0a6f8800 0 0x400>; >>> + >>> +        #address-cells = <2>; >>> +        #size-cells = <2>; >>> + >>> +        clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, >>> +                 <&gcc GCC_USB30_PRIM_MASTER_CLK>, >>> +                 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, >>> +                 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >>> +                 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; >>> +        clock-names = "cfg_noc", "core", "iface", "mock_utmi", >>> +                        "sleep"; >> Spacing looks off. Are there tabs? > will correct in next version >> >>> + >>> +        assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >>> +                          <&gcc GCC_USB30_PRIM_MASTER_CLK>; >>> +        assigned-clock-rates = <19200000>, <150000000>; >>> + >>> +        interrupts = , >>> +                     , >>> +                     , >>> +                     ; >>> +        interrupt-names = "hs_phy_irq", "ss_phy_irq", >>> +                              "dm_hs_phy_irq", "dp_hs_phy_irq"; >> Same spacing nit > will correct in next version >> >>> + >>> +            power-domains = <&gcc USB30_PRIM_GDSC>; >>> + >>> +            resets = <&gcc GCC_USB30_PRIM_BCR>; >>> + >>> +            usb_1_dwc3: dwc3@a600000 { >> Drop this phandle too? It isn't used. > will correct in next version >> >>> +                compatible = "snps,dwc3"; >>> +                reg = <0 0x0a600000 0 0xcd00>; >>> +                interrupts = ; >>> +                iommus = <&apps_smmu 0x740 0>; >>> +                snps,dis_u2_susphy_quirk; >>> +                snps,dis_enblslpm_quirk; >>> +                phys = <&usb_1_hsphy>, <&usb_1_ssphy>; >>> +                phy-names = "usb2-phy", "usb3-phy"; >>> +            }; >> [1] https://lkml.kernel.org/r/20191218221310.GA4624@bogus > -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation