From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benjamin Herrenschmidt Subject: Re: Request review of device tree documentation Date: Sat, 12 Jun 2010 20:45:29 +1000 Message-ID: <1276339529.1962.184.camel@pasglop> References: <33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com> <4C13430B.5000907@firmworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <4C13430B.5000907-D5eQfiDGL7eakBO8gow8eQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org To: Mitch Bradley Cc: microblaze-uclinux-rVRm/Wmeqae7NGdpmJTKYQ@public.gmane.org, devicetree-discuss , linuxppc-dev , Dan Malek , Jeremy Kerr List-Id: devicetree@vger.kernel.org On Fri, 2010-06-11 at 22:19 -1000, Mitch Bradley wrote: > It seems that many of the differences at the CPU level can be determined > by looking at "coprocessor" registers. For what purpose(s) do we need > to identify the core? That will inform our choice of a core ID schema. The primary thing I see would be architecture version compliance, though this is better carried additionally via a binary field in the header or a GPR at the entry point, to help the initial asm code to setup the MMU etc... before getting into C code. Cheers, Ben.