From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
Takashi Iwai <tiwai@suse.com>,
Maxim Kochetkov <fido_max@inbox.ru>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Jose Abreu <joabreu@synopsys.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Walker Chen <walker.chen@starfivetech.com>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<alsa-devel@alsa-project.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v1 2/5] ASoC: dt-bindings: snps,designware-i2s: Add StarFive JH7110 SoC support
Date: Mon, 7 Aug 2023 17:03:05 +0800 [thread overview]
Message-ID: <12a9bfda-9c9f-6baf-3e5f-ce7cc7d79aee@starfivetech.com> (raw)
In-Reply-To: <37a636dd-fbd8-d475-8814-e0cc6d5cc812@linaro.org>
On 2023/8/6 5:02, Krzysztof Kozlowski wrote:
> On 02/08/2023 10:42, Xingyu Wu wrote:
>> Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings
>> of Designware I2S controller. The I2S controller needs two reset items''
>
> Thank you for your patch. There is something to discuss/improve.
>
>>
>> resets:
>> items:
>> - description: Optional controller resets
>> + - description: controller reset of Sampling rate
>> + minItems: 1
>>
>> dmas:
>> items:
>> @@ -51,6 +75,17 @@ properties:
>> - const: rx
>> minItems: 1
>>
>> + starfive,syscon:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to System Register Controller sys_syscon node.
>> + - description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register.
>> + - description: I2S-rx enabled control mask
>> + description:
>> + The phandle to System Register Controller syscon node and the I2S-rx(ADC)
>> + enabled control offset and mask of SYS_SYSCONSAIF__SYSCFG register.
>> +
>> allOf:
>> - $ref: dai-common.yaml#
>> - if:
>> @@ -66,6 +101,66 @@ allOf:
>> properties:
>> "#sound-dai-cells":
>> const: 0
>
> You need to constrain clocks and resets also for all other existing
> variants.
>>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,designware-i2s
>> + then:
>> + properties:
>> + clocks:
>> + maxItems: 1
>> + clock-names:
>> + maxItems: 1
>> + resets:
>> + maxItems: 1
>> + else:
>> + properties:
>> + resets:
>> + minItems: 2
The resets of TX0/TX1/RX on JH7110 SoC are mentioned in 'else' here.
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: starfive,jh7110-i2stx0
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 5
>
> Also maxItems
Will add.
>
>> + clock-names:
>> + minItems: 5
>
> Also maxItems
Will add.
>
> What about resets? 1 or 2 items?
Mentioned it in the 'else'.
Or do you mean I should drop the 'else' and add the resets in here?
And is the same for TX1 and RX?
>
>> + required:
>> + - resets
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: starfive,jh7110-i2stx1
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 9
>> + clock-names:
>> + minItems: 9
>
> resets?>
>> + required:
>> + - resets
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: starfive,jh7110-i2srx
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 9
>> + clock-names:
>> + minItems: 9
>
> resets?
>
>> + required:
>> + - resets
>> + - starfive,syscon
>> + else:
>> + properties:
>> + starfive,syscon: false
>>
>> required:
>> - compatible
>
Best regards,
Xingyu Wu
next prev parent reply other threads:[~2023-08-07 9:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-02 8:42 [PATCH v1 0/5] Add I2S support for the StarFive JH7110 SoC Xingyu Wu
2023-08-02 8:42 ` [PATCH v1 1/5] ASoC: dwc: Use ops to get platform data Xingyu Wu
2023-08-02 8:42 ` [PATCH v1 2/5] ASoC: dt-bindings: snps,designware-i2s: Add StarFive JH7110 SoC support Xingyu Wu
2023-08-05 21:02 ` Krzysztof Kozlowski
2023-08-07 9:03 ` Xingyu Wu [this message]
2023-08-07 9:17 ` Krzysztof Kozlowski
2023-08-07 9:33 ` Xingyu Wu
2023-08-02 8:42 ` [PATCH v1 3/5] ASoC: dwc: i2s: " Xingyu Wu
2023-08-03 5:16 ` Maxim Kochetkov
2023-08-04 9:20 ` Xingyu Wu
2023-08-02 8:43 ` [PATCH v1 4/5] riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1 Xingyu Wu
2023-08-02 8:43 ` [PATCH v1 5/5] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1 Xingyu Wu
2023-08-05 21:04 ` Krzysztof Kozlowski
2023-08-07 9:04 ` Xingyu Wu
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