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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
	Loic Poulain <loic.poulain@oss.qualcomm.com>
Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: qcm2290: Add crypto engine
Date: Thu, 27 Mar 2025 18:13:29 +0100	[thread overview]
Message-ID: <12e011f2-1aa3-4e95-a081-bf81e00912c2@oss.qualcomm.com> (raw)
In-Reply-To: <h3ol4qc242w7h3u7uiywxyc2v6op6cvxhzuk2dx5q5dvhitolp@pb6c53ki3cag>

On 3/27/25 4:05 PM, Dmitry Baryshkov wrote:
> On Thu, Mar 27, 2025 at 03:28:42PM +0100, Loic Poulain wrote:
>> Add Qualcomm Crypto Engine (QCE) and BAM related nodes for this SoC.
>>
>> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/qcm2290.dtsi | 28 +++++++++++++++++++++++++++
>>  1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>> index f0746123e594..c9ac06164d43 100644
>> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>> @@ -749,6 +749,34 @@ config_noc: interconnect@1900000 {
>>  			#interconnect-cells = <2>;
>>  		};
>>  
>> +		cryptobam: dma@1b04000 {
>> +			compatible = "qcom,bam-v1.7.0";
>> +			reg = <0x0 0x01b04000 0x0 0x24000>;
>> +			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
>> +			clock-names = "bam_clk";
>> +			#dma-cells = <1>;
>> +			qcom,ee = <0>;
>> +			qcom,controlled-remotely;
>> +			iommus = <&apps_smmu 0x0084 0x0011>,
>> +				 <&apps_smmu 0x0086 0x0011>,
>> +				 <&apps_smmu 0x0094 0x0011>,
>> +				 <&apps_smmu 0x0096 0x0011>;
>> +		};
>> +
>> +		crypto: crypto@1b3a000 {
>> +			compatible = "qcom,qcm2290-qce", "qcom,qce";
>> +			reg = <0x0 0x01b3a000 0x0 0x6000>;
>> +			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
>> +			clock-names = "core";
>> +			dmas = <&cryptobam 6>, <&cryptobam 7>;
>> +			dma-names = "rx", "tx";
>> +			iommus = <&apps_smmu 0x0084 0x0011>,
>> +				 <&apps_smmu 0x0086 0x0011>,
>> +				 <&apps_smmu 0x0094 0x0011>,
>> +				 <&apps_smmu 0x0096 0x0011>;
> 
> Don't these fall into the previous entries + mask? The same question
> applies to BAM SMMU entries.

(effective sid = e.g. 0x0084 & ~0x0011)

Konrad

  reply	other threads:[~2025-03-27 17:13 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-27 14:28 [PATCH] arm64: dts: qcom: qcm2290: Add crypto engine Loic Poulain
2025-03-27 15:05 ` Dmitry Baryshkov
2025-03-27 17:13   ` Konrad Dybcio [this message]
2025-03-27 18:17     ` Dmitry Baryshkov

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