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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac71961f9absm22821366b.103.2025.03.27.10.13.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Mar 2025 10:13:30 -0700 (PDT) Message-ID: <12e011f2-1aa3-4e95-a081-bf81e00912c2@oss.qualcomm.com> Date: Thu, 27 Mar 2025 18:13:29 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: qcm2290: Add crypto engine To: Dmitry Baryshkov , Loic Poulain Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20250327142842.1138203-1-loic.poulain@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=TuvmhCXh c=1 sm=1 tr=0 ts=67e5873e cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=L3SEVPxwON1qY0H_nQ8A:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: 7VASmzwQL9_RGkLkX8fUa6JBSsbZKZxl X-Proofpoint-ORIG-GUID: 7VASmzwQL9_RGkLkX8fUa6JBSsbZKZxl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-27_02,2025-03-26_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503270117 On 3/27/25 4:05 PM, Dmitry Baryshkov wrote: > On Thu, Mar 27, 2025 at 03:28:42PM +0100, Loic Poulain wrote: >> Add Qualcomm Crypto Engine (QCE) and BAM related nodes for this SoC. >> >> Signed-off-by: Loic Poulain >> --- >> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 28 +++++++++++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi >> index f0746123e594..c9ac06164d43 100644 >> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi >> @@ -749,6 +749,34 @@ config_noc: interconnect@1900000 { >> #interconnect-cells = <2>; >> }; >> >> + cryptobam: dma@1b04000 { >> + compatible = "qcom,bam-v1.7.0"; >> + reg = <0x0 0x01b04000 0x0 0x24000>; >> + interrupts = ; >> + clocks = <&rpmcc RPM_SMD_CE1_CLK>; >> + clock-names = "bam_clk"; >> + #dma-cells = <1>; >> + qcom,ee = <0>; >> + qcom,controlled-remotely; >> + iommus = <&apps_smmu 0x0084 0x0011>, >> + <&apps_smmu 0x0086 0x0011>, >> + <&apps_smmu 0x0094 0x0011>, >> + <&apps_smmu 0x0096 0x0011>; >> + }; >> + >> + crypto: crypto@1b3a000 { >> + compatible = "qcom,qcm2290-qce", "qcom,qce"; >> + reg = <0x0 0x01b3a000 0x0 0x6000>; >> + clocks = <&rpmcc RPM_SMD_CE1_CLK>; >> + clock-names = "core"; >> + dmas = <&cryptobam 6>, <&cryptobam 7>; >> + dma-names = "rx", "tx"; >> + iommus = <&apps_smmu 0x0084 0x0011>, >> + <&apps_smmu 0x0086 0x0011>, >> + <&apps_smmu 0x0094 0x0011>, >> + <&apps_smmu 0x0096 0x0011>; > > Don't these fall into the previous entries + mask? The same question > applies to BAM SMMU entries. (effective sid = e.g. 0x0084 & ~0x0011) Konrad