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(2a02-a466-4d7a-0-1072-bb1c-c0f3-280f.fixed6.kpn.net. [2a02:a466:4d7a:0:1072:bb1c:c0f3:280f]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c6f35sm166925266b.12.2026.09.23.11.02.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Sep 2026 11:02:02 -0700 (PDT) Message-ID: <12e5e5ad-7d55-469d-a63e-d19e3279c6c1@pardini.net> Date: Wed, 23 Sep 2026 20:02:01 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S To: Diederik de Haas , Heiner Kallweit , nic_swsd@realtek.com, Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Sebastian Reichel , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Jonas Karlman References: <20260910-rk3588-dts-rtl-eth-describe-dt-alias-v5-0-c1b9e5f10cd6@pardini.net> <20260910-rk3588-dts-rtl-eth-describe-dt-alias-v5-5-c1b9e5f10cd6@pardini.net> Content-Language: en-US From: Ricardo Pardini In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 23/09/2026 19:15, Diederik de Haas wrote: > Hi, > > On Thu Sep 10, 2026 at 10:07 PM CEST, Ricardo Pardini via B4 Relay wrote: >> From: Ricardo Pardini >> >> The FriendlyElec NanoPi R5S (rk3568) carries two on-board Realtek >> RTL8125 NICs behind pcie2x1 and pcie3x1, alongside the existing gmac0 >> RGMII PHY. >> >> Describe the fixed function nodes and attach ethernet1/ethernet2 >> aliases (ethernet0 stays mapped to gmac0), so that U-Boot's >> fdt_fixup_ethernet() can inject mac-address properties from its >> eth1addr/eth2addr env, for stable MACs across boots that both U-Boot >> and the kernel agree on. >> >> Signed-off-by: Ricardo Pardini >> --- >> arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 30 ++++++++++++++++++++++ >> 1 file changed, 30 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts >> index 90ce6f0e1dcff..9ed11663c31c9 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts >> +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts >> @@ -15,6 +15,8 @@ / { >> >> aliases { >> ethernet0 = &gmac0; >> + ethernet1 = &rtl_eth1; >> + ethernet2 = &rtl_eth2; >> }; > > With my NanoPi-R5S I'm still getting the following warning: > > r8169 0001:11:00.0: can't read MAC address, setting random one > > ``` > root@nanopi-r5s:~# ip link > 1: lo: mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000 > link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 > 2: end1: mtu 1500 qdisc fq_codel state DOWN mode DEFAULT group default qlen 1000 > link/ether 4e:52:85:9e:22:f9 brd ff:ff:ff:ff:ff:ff > altname enp1s0 > altname enx4e52859e22f9 > 3: end2: mtu 1500 qdisc fq_codel state DOWN mode DEFAULT group default qlen 1000 > link/ether 12:e5:47:9e:e2:f1 brd ff:ff:ff:ff:ff:ff > altname enP1p17s0 > 4: end0: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 > link/ether 4e:52:85:9e:22:f8 brd ff:ff:ff:ff:ff:ff > altname enx4e52859e22f8 > ``` > > I did not do anything (explicitly) in U-Boot, but it seems it created a > non-random MAC address for end0 and end1 ... and then stopped. > AFAIK gmac0=end0 already had a non-random MAC address and I hoped/expected > it would create non-random addresses for end1 and end2, which would've made > the above warning go away too. > > Is this an issue with this patch, with U-Boot or me? Hi Diederik, in this case (3 ethernet's) I think it's down to U-boot. Check the output of `printenv` in u-boot, you'll probably find it only pre-computes 2 MAC addresses, and doesn't feed the ethernet2 alias during its fdt_fixup_ethernet(). Try doing `setenv eth2addr xx:xx...` in u-boot before booting -- it should work. I think that's what I did when testing the R5S with this series, but it has been a very long time ago. One way around this (without u-boot) would be to use Alexey's series [1] which could compute as many MACs as needed out of the CPU serialnum - but that also won't work as-sent vs rk356x, I believe he's checking an alternative proposed. [1] https://lore.kernel.org/linux-rockchip/20260902-rk3576-otp-cpuid-mac-v2-0-e4b7fe2ab13f@flipper.net/ > > Full details: > https://paste.sr.ht/~diederik/8ae7d354985afcd1c3464e3a4ad81da1b4442364 > > Side note: > I wonder how 'random' those addresses are as during testing ``ssh rock5b`` > landed me on another device (NanoPC-T6 Plus), f.e. My router has DHCP > reservations based on MAC addresses and it looks like it got confused ;-) Interesting. I dunno what seed is used, as I've been fully set on making it non-random, but I wouldn't discard the possibility of conflicts across different machines. One more reason to have this series ;-) I'll soon send a v6 to linux-rockchip/dt (with small fixes Sashiko found to DTs, and without the binding) and split a single-patch v1 to net-next with only the binding, collecting Rob's review. If and when those land, we'd have open road both for u-boot local-mac-address and Alexey's nvmem-cells for the RTLs. Regards, Ricardo > > Cheers, > Diederik > >> gpio-keys { >> @@ -107,6 +109,20 @@ &pcie2x1 { >> num-lanes = <1>; >> reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; >> status = "okay"; >> + >> + pcie@0,0 { >> + reg = <0x000000 0 0 0 0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges; >> + device_type = "pci"; >> + bus-range = <0x00 0x0f>; >> + >> + rtl_eth1: ethernet@0,0 { >> + compatible = "pci10ec,8125"; >> + reg = <0x010000 0 0 0 0>; >> + }; >> + }; >> }; >> >> &pcie30phy { >> @@ -119,6 +135,20 @@ &pcie3x1 { >> reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; >> vpcie3v3-supply = <&vcc3v3_pcie>; >> status = "okay"; >> + >> + pcie@0,0 { >> + reg = <0x100000 0 0 0 0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges; >> + device_type = "pci"; >> + bus-range = <0x10 0x1f>; >> + >> + rtl_eth2: ethernet@0,0 { >> + compatible = "pci10ec,8125"; >> + reg = <0x110000 0 0 0 0>; >> + }; >> + }; >> }; >> >> &pcie3x2 { >