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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80676f23bsm15251674a12.32.2024.12.30.07.04.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Dec 2024 07:04:09 -0800 (PST) Message-ID: <12fb6164-fa53-46e7-9a22-bb9b373f9860@oss.qualcomm.com> Date: Mon, 30 Dec 2024 16:04:07 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] PCI: dwc: Add ECAM support with iATU configuration To: Krishna Chaitanya Chundru , cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, mmareddy@quicinc.com, Krishna chaitanya chundru References: <20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com> <20241224-enable_ecam-v2-2-43daef68a901@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241224-enable_ecam-v2-2-43daef68a901@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: qSggPj8uQ6kVAsFK3sH0rnVw7B4MK4qY X-Proofpoint-ORIG-GUID: qSggPj8uQ6kVAsFK3sH0rnVw7B4MK4qY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 spamscore=0 suspectscore=0 mlxscore=0 impostorscore=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412300130 On 24.12.2024 3:10 PM, Krishna Chaitanya Chundru wrote: > From: Krishna chaitanya chundru > > The current implementation requires iATU for every configuration > space access which increases latency & cpu utilization. > > Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature, > which shifts/maps the BDF (bits [31:16] of the third header DWORD, which > would be matched against the Base and Limit addresses) of the incoming > CfgRd0/CfgWr0 down to bits[27:12]of the translated address. > > Configuring iATU in config shift feature enables ECAM feature to access the > config space, which avoids iATU configuration for every config access. > > Add "ctrl2" into struct dw_pcie_ob_atu_cfg to enable config shift feature. > > As DBI comes under config space, this avoids remapping of DBI space > separately. Instead, it uses the mapped config space address returned from > ECAM initialization. Change the order of dw_pcie_get_resources() execution > to achieve this. > > Enable the ECAM feature if the config space size is equal to size required > to represent number of buses in the bus range property, add a function > which checks this. The DWC glue drivers uses this function and decide to > enable ECAM mode or not. > > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/Kconfig | 1 + > drivers/pci/controller/dwc/pcie-designware-host.c | 136 +++++++++++++++++++--- > drivers/pci/controller/dwc/pcie-designware.c | 2 +- > drivers/pci/controller/dwc/pcie-designware.h | 11 ++ > 4 files changed, 130 insertions(+), 20 deletions(-) > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > index b6d6778b0698..73c3aed6b60a 100644 > --- a/drivers/pci/controller/dwc/Kconfig > +++ b/drivers/pci/controller/dwc/Kconfig > @@ -9,6 +9,7 @@ config PCIE_DW > config PCIE_DW_HOST > bool > select PCIE_DW > + select PCI_HOST_COMMON > > config PCIE_DW_EP > bool > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index d2291c3ceb8b..4e07fefe12e1 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -418,6 +418,61 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) > } > } > > +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = {0}; > + struct resource_entry *bus; > + int ret, bus_range_max; resource_size_t for bus_range_max since you feed it the ouput of resource_size() > + > + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); > + > + /* > + * Root bus under the root port doesn't require any iATU configuration > + * as DBI space will represent Root bus configuration space. > + * Immediate bus under Root Bus, needs type 0 iATU configuration and > + * remaining buses need type 1 iATU configuration. > + */ > + atu.index = 0; > + atu.type = PCIE_ATU_TYPE_CFG0; > + atu.cpu_addr = pp->cfg0_base + SZ_1M; > + atu.size = SZ_1M; > + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > + if (ret) > + return ret; > + > + bus_range_max = resource_size(bus->res); > + > + /* Configure remaining buses in type 1 iATU configuration */ > + atu.index = 1; > + atu.type = PCIE_ATU_TYPE_CFG1; > + atu.cpu_addr = pp->cfg0_base + SZ_2M; > + atu.size = (SZ_1M * (bus_range_max - 2)); This explodes badly with: bus-range = <0 0>; > + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; > + return dw_pcie_prog_outbound_atu(pci, &atu); A newline before the return statement would make it prettier [...] > +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct platform_device *pdev = to_platform_device(pci->dev); > + struct resource *config_res, *bus_range; > + u64 bus_config_space_count; > + > + bus_range = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res; > + if (!bus_range) > + return false; > + > + config_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); > + if (!config_res) > + return false; > + > + bus_config_space_count = resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT; > + if (resource_size(bus_range) > bus_config_space_count) > + return false; > + > + return true; return bus_config_space_count <= resource_size(bus_range); Konrad