[PATCH v3 0/1] arm64: zynqmp: Misc zynqmp changes

[PATCH v3 0/1] arm64: zynqmp: Misc zynqmp changes

[Michal Simek]

Hi,

the series is syncing the latest dt changes based on board status and the
latest DT schema.
The patches are based on
https://lore.kernel.org/all/20230321070619.29440-1-parth.gajjar@amd.com/

I have applied patches which were reviewed already to have smaller series.
Patches can be found https://github.com/Xilinx/linux-xlnx/tree/zynqmp/dt
or they are in Linux-next already.

v1 is at
https://lore.kernel.org/r/7d034b9e-e4e6-5d72-8b37-78e25918aa59@amd.com.

v2 is at
https://lore.kernel.org/r/cover.1684767562.git.michal.simek@amd.com

Thanks,
Michal

Changes in v3:
- Add missing cache-unified

Changes in v2:
- Update commit message to remove Linux part - reported by Laurent

Radhey Shyam Pandey (1):
  arm64: zynqmp: Add L2 cache nodes

 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

-- 
2.36.1

[PATCH v3 1/1] arm64: zynqmp: Add L2 cache nodes

[Michal Simek]

From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>

Describe SoC L2 cache hierarchy.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

Changes in v3:
- Add missing cache-unified

Changes in v2:
- Update commit message to remove Linux part - reported by Laurent

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.

---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 02cfcc716936..394db49ac6cb 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -33,6 +33,7 @@ cpu0: cpu@0 {
 			operating-points-v2 = <&cpu_opp_table>;
 			reg = <0x0>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@1 {
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
 			reg = <0x1>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu@2 {
@@ -51,6 +53,7 @@ cpu2: cpu@2 {
 			reg = <0x2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu@3 {
@@ -60,6 +63,13 @@ cpu3: cpu@3 {
 			reg = <0x3>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
 		};
 
 		idle-states {
-- 
2.36.1

Re: [PATCH v3 0/1] arm64: zynqmp: Misc zynqmp changes

[Michal Simek]

On 6/5/23 13:23, Michal Simek wrote:
> Hi,
> 
> the series is syncing the latest dt changes based on board status and the
> latest DT schema.
> The patches are based on
> https://lore.kernel.org/all/20230321070619.29440-1-parth.gajjar@amd.com/
> 
> I have applied patches which were reviewed already to have smaller series.
> Patches can be found https://github.com/Xilinx/linux-xlnx/tree/zynqmp/dt
> or they are in Linux-next already.
> 
> v1 is at
> https://lore.kernel.org/r/7d034b9e-e4e6-5d72-8b37-78e25918aa59@amd.com.
> 
> v2 is at
> https://lore.kernel.org/r/cover.1684767562.git.michal.simek@amd.com
> 
> Thanks,
> Michal
> 
> Changes in v3:
> - Add missing cache-unified
> 
> Changes in v2:
> - Update commit message to remove Linux part - reported by Laurent
> 
> Radhey Shyam Pandey (1):
>    arm64: zynqmp: Add L2 cache nodes
> 
>   arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 

Applied.
M