[PATCH v2 1/8] sh-pfc: Add OF support

[PATCH v2 1/8] sh-pfc: Add OF support

[Laurent Pinchart]

Support device instantiation through the device tree. The compatible
property is used to select the SoC pinmux information.

Set the gpio_chip device field to the PFC device to enable automatic
GPIO OF support.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: devicetree-discuss@lists.ozlabs.org
---
 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       |   77 ++++++++++++++++++++
 drivers/pinctrl/sh-pfc/core.c                      |   62 +++++++++++++++-
 drivers/pinctrl/sh-pfc/pinctrl.c                   |   54 ++++++++++++++
 3 files changed, 191 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt

(Comment from the cover letter repeated here)

I'm still a bit unsure about the DT bindings. The platforms that implement
pinctrl DT bindings use a wide variety of architectures. I haven't found clear
guidelines regarding how those bindings should be implemented
(Documentation/devicetree/pinctrl just states that bindings are
driver-specific). Comments will be appreciated.

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
new file mode 100644
index 0000000..77752c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -0,0 +1,77 @@
+* Renesas GPIO and Pin Mux/Config controller
+
+Required Properties:
+- compatible: should be one of the following.
+  - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+  - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
+  - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
+  - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
+
+- reg: Base address and length of each memory resource used by the pin
+  controller hardware module.
+
+- gpio-controller: Marks the device node as a gpio controller.
+
+- #gpio-cells: Should be 2. The first cell is the pin number and the second cell
+  is used to specify optional parameters as bit flags. Only the GPIO active low
+  flag (bit 0) is currently supported.
+
+
+The PFC node also acts as a container for pin control maps represented as
+subnodes. Each subnode contains a function name and one or more pin or pin group
+name. The subnode names are ignored, all subnodes are parsed through phandles
+and processed purely based on their content.
+
+Required Subnode Properties:
+- renesas,pins : An array of strings. Each string contains the name of a pin or
+  pin group.
+- renesas,function: A string containing the name of the function to mux to the
+  pin or pin group.
+
+  Valid values for group and function names can be found in the group and
+  function arrays of the PFC data file corresponding to the SoC
+  (drivers/pinctrl/spear/pfc-*.c)
+
+Please refer to pinctrl-bindings.txt in this directory for details of the common
+pinctrl bindings used by client devices.
+
+
+The syntax of the gpio specifier used by client nodes should be the following
+with values derived from the SoC user manual.
+
+  <[phandle of the gpio controller node]
+   [pin number within the gpio controller]
+   [flags and pull up/down]>
+
+
+Example 1: SH73A0 (SH-Mobile AG5) pin controller node
+
+	gpio: pfc@e6050000 {
+		compatible = "renesas,pfc-sh73a0";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605801c 0x1c>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+Example 2: A GPIO LED node that references a GPIO
+
+	leds {
+		compatible = "gpio-leds";
+		led1 {
+			gpios = <&gpio 20 1>; /* Active low */
+		};
+	};
+
+Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state and pin control maps
+           for the LCD device
+
+	&gpio {
+		pinctrl-0 = <&lcd_pins>;
+		pinctrl-names = "default";
+
+		lcd_pins: pfc_lcd_pins {
+			renesas,pins = "lcd_data24", "lcd_sync";
+			renesas,function = "lcd";
+		};
+	};
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 912b579..d0e8e77 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -19,6 +19,7 @@
 #include <linux/ioport.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of_device.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
@@ -510,8 +511,55 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
 	return sh_pfc_config_mux(pfc, mark, pinmux_type, cfg_mode);
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id sh_pfc_of_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_R8A7740
+	{
+		.compatible = "renesas,pfc-r8a7740",
+		.data = &r8a7740_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7779
+	{
+		.compatible = "renesas,pfc-r8a7779",
+		.data = &r8a7779_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH7367
+	{
+		.compatible = "renesas,pfc-sh7367",
+		.data = &sh7367_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH7372
+	{
+		.compatible = "renesas,pfc-sh7372",
+		.data = &sh7372_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH7377
+	{
+		.compatible = "renesas,pfc-sh7377",
+		.data = &sh7377_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH73A0
+	{
+		.compatible = "renesas,pfc-sh73a0",
+		.data = &sh73a0_pinmux_info,
+	},
+#endif
+	{ },
+};
+MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
+#endif
+
 static int sh_pfc_probe(struct platform_device *pdev)
 {
+	const struct platform_device_id *platid = platform_get_device_id(pdev);
+#ifdef CONFIG_OF
+	struct device_node *np = pdev->dev.of_node;
+#endif
 	struct sh_pfc_soc_info *info;
 	struct sh_pfc *pfc;
 	int ret;
@@ -521,8 +569,15 @@ static int sh_pfc_probe(struct platform_device *pdev)
 	 */
 	BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
 
-	info = pdev->id_entry->driver_data
-	      ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
+	if (platid)
+		info = (void *)platid->driver_data;
+#ifdef CONFIG_OF
+	else if (np)
+		info = (void *)of_match_device(sh_pfc_of_table, &pdev->dev)->data;
+#endif
+	else
+		info = pdev->dev.platform_data;
+
 	if (info == NULL)
 		return -ENODEV;
 
@@ -646,6 +701,9 @@ static struct platform_driver sh_pfc_driver = {
 	.driver		= {
 		.name	= DRV_NAME,
 		.owner	= THIS_MODULE,
+#ifdef CONFIG_OF
+		.of_match_table = sh_pfc_of_table,
+#endif
 	},
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 6ee4105..78b78d2 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -15,7 +15,9 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/pinctrl/pinctrl.h>
@@ -65,11 +67,63 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 	seq_printf(s, "%s", DRV_NAME);
 }
 
+static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
+				 struct device_node *np,
+				 struct pinctrl_map **map, unsigned *num_maps)
+{
+	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+	struct pinctrl_map *maps;
+	struct property *prop;
+	unsigned int index = 0;
+	const char *function;
+	const char *group;
+	int ret;
+
+	ret = of_property_read_string(np, "renesas,function", &function);
+	if (ret < 0) {
+		dev_err(pmx->pfc->dev, "No function provided in DT\n");
+		return ret;
+	}
+
+	ret = of_property_count_strings(np, "renesas,pins");
+	if (ret < 0)
+		return ret;
+
+	if (!ret) {
+		dev_err(pmx->pfc->dev, "No pin(group) provided in DT node\n");
+		return -ENODEV;
+	}
+
+	maps = kzalloc(sizeof(*maps) * ret, GFP_KERNEL);
+	if (maps == NULL)
+		return -ENOMEM;
+
+	of_property_for_each_string(np, "renesas,pins", prop, group) {
+		maps[index].type = PIN_MAP_TYPE_MUX_GROUP;
+		maps[index].data.mux.group = group;
+		maps[index].data.mux.function = function;
+		index++;
+	}
+
+	*map = maps;
+	*num_maps = index;
+
+	return 0;
+}
+
+static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
+			       struct pinctrl_map *map, unsigned num_maps)
+{
+	kfree(map);
+}
+
 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 	.get_groups_count	= sh_pfc_get_groups_count,
 	.get_group_name		= sh_pfc_get_group_name,
 	.get_group_pins		= sh_pfc_get_group_pins,
 	.pin_dbg_show		= sh_pfc_pin_dbg_show,
+	.dt_node_to_map		= sh_pfc_dt_node_to_map,
+	.dt_free_map		= sh_pfc_dt_free_map,
 };
 
 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
-- 
1.7.8.6

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Guennadi Liakhovetski]

Hi Laurent

On Wed, 9 Jan 2013, Laurent Pinchart wrote:

> Support device instantiation through the device tree. The compatible
> property is used to select the SoC pinmux information.
> 
> Set the gpio_chip device field to the PFC device to enable automatic
> GPIO OF support.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Cc: devicetree-discuss@lists.ozlabs.org

This whole pinctrl mega-series is a very welcome improvement to the 
sh-/r-mobile GPIO framework, and is very well done IMHO! But, 
unfortunately, as discussed with you privately yesterday, there is still a 
problem with pinctrl DT support on sh73a0, which will, probably, enforce 
an update to one or several of patches from this lot. To explain to other 
readers, on sh73a0 pin numbers are not contiguous, they are sparse. 
When pins are referred to from C code, macro names are used, which are 
then correctly decoded to respective positions in pin descriptor tables. 
Whereas with DT, pins are referred to from .dts files using their physical 
numbers, which then refer to either wrong or missing entries in those 
tables.

I do not know where this problem should be solved best - either in 
descriptor tables, or in DT handling code, so, I don't know which patches 
would be affected. Don't think you'll want to keep the one-to-one 
index-to-pin mapping by also making pin-descriptor arrays sparse, so, so 
far I only see one possibility to fix this - by using the .enum_id field 
from struct sh_pfc_pin instead of just the index - both in  C and in DT 
case, and those .enum_id values will have to provide physical pin numbers 
instead of plane indices. That way you'd have to update at least 
drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the sh_pfc_map_gpios() function in 
drivers/pinctrl/sh-pfc/pinctrl.c.

Anyway, I'm sure you'll find a suitable solution of this problem and for 
now I'll let Simon decide which patches he wants to apply and which ones 
he'd prefer to hold back;-)

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Simon Horman]

On Sat, Jan 12, 2013 at 06:18:54PM +0100, Guennadi Liakhovetski wrote:
> Hi Laurent
> 
> On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> 
> > Support device instantiation through the device tree. The compatible
> > property is used to select the SoC pinmux information.
> > 
> > Set the gpio_chip device field to the PFC device to enable automatic
> > GPIO OF support.
> > 
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Cc: devicetree-discuss@lists.ozlabs.org
> 
> This whole pinctrl mega-series is a very welcome improvement to the 
> sh-/r-mobile GPIO framework, and is very well done IMHO! But, 
> unfortunately, as discussed with you privately yesterday, there is still a 
> problem with pinctrl DT support on sh73a0, which will, probably, enforce 
> an update to one or several of patches from this lot. To explain to other 
> readers, on sh73a0 pin numbers are not contiguous, they are sparse. 
> When pins are referred to from C code, macro names are used, which are 
> then correctly decoded to respective positions in pin descriptor tables. 
> Whereas with DT, pins are referred to from .dts files using their physical 
> numbers, which then refer to either wrong or missing entries in those 
> tables.
> 
> I do not know where this problem should be solved best - either in 
> descriptor tables, or in DT handling code, so, I don't know which patches 
> would be affected. Don't think you'll want to keep the one-to-one 
> index-to-pin mapping by also making pin-descriptor arrays sparse, so, so 
> far I only see one possibility to fix this - by using the .enum_id field 
> from struct sh_pfc_pin instead of just the index - both in  C and in DT 
> case, and those .enum_id values will have to provide physical pin numbers 
> instead of plane indices. That way you'd have to update at least 
> drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the sh_pfc_map_gpios() function in 
> drivers/pinctrl/sh-pfc/pinctrl.c.
> 
> Anyway, I'm sure you'll find a suitable solution of this problem and for 
> now I'll let Simon decide which patches he wants to apply and which ones 
> he'd prefer to hold back;-)

Actually, I'd appreciate some guidance from Laurent on this.
It seems that the problems you raise go quite far back into the mega-series.

I was intending to send pull requests for the following branches soon.
But I am now concerned that at least the sh73a0 patches may need reworking.

pfc2: (based on a merge of sh-soc2 and pfc)
sh-pfc: Add shx3 pinmux support
sh-pfc: Add sh7786 pinmux support
sh-pfc: Add sh7785 pinmux support
sh-pfc: Add sh7757 pinmux support
sh-pfc: Add sh7734 pinmux support
sh-pfc: Add sh7724 pinmux support
sh-pfc: Add sh7723 pinmux support
sh-pfc: Add sh7722 pinmux support
sh-pfc: Add sh7720 pinmux support
sh-pfc: Add sh7269 pinmux support
sh-pfc: Add sh7264 pinmux support
sh-pfc: Add sh7203 pinmux support
sh-pfc: Add sh73a0 pinmux support
sh-pfc: Add sh7372 pinmux support
sh-pfc: Add r8a7779 pinmux support
sh-pfc: Add r8a7740 pinmux support
sh-pfc: Support pinmux info in driver data instead of platform data
sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/
sh-pfc: Remove unused resource and num_resources platform data fields
sh-pfc: Remove platform device registration

sh-soc2: (based on pfc)
sh: shx3: Register PFC platform device
sh: sh7786: Register PFC platform device
sh: sh7785: Register PFC platform device
sh: sh7757: Register PFC platform device
sh: sh7734: Register PFC platform device
sh: sh7724: Register PFC platform device
sh: sh7723: Register PFC platform device
sh: sh7722: Register PFC platform device
sh: sh7720: Register PFC platform device
sh: sh7269: Register PFC platform device
sh: sh7264: Register PFC platform device
sh: sh7203: Register PFC platform device
sh: Add PFC platform device registration helper function


soc: (based on sh-soc)
ARM: shmobile: sh73a0: Add pin control resources
ARM: shmobile: sh7372: Add pin control resources
ARM: shmobile: r8a7740: Add pin control resources
ARM: shmobile: sh73a0: Register PFC platform device
ARM: shmobile: sh7372: Register PFC platform device
ARM: shmobile: r8a7779: Register PFC platform device
ARM: shmobile: r8a7740: Register PFC platform device
ARM: shmobile: Select PINCTRL
ARM: shmobile: add function declarations for sh7372 DT helper functions
ARM: sh7372: fix cache clean / invalidate order
ARM: sh7372: add clock lookup entries for DT-based devices
ARM: mach-shmobile: sh73a0 external IRQ wake update
ARM: shmobile: sh73a0: fixup div4_clks bitmap
ARM: shmobile: r8a7740: add TMU timer support
ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c

pfc: (based on sh-soc)
sh-pfc: Support passing resources through platform device
sh-pfc: Split platform device and platform driver registration
sh-pfc: Use sh_pfc_ namespace prefix through the whole driver
sh-pfc: Sort headers alphabetically
sh-pfc: Remove check for impossible error condition
sh-pfc: Let the compiler decide whether to inline functions
sh-pfc: Use devm_ioremap_nocache()
sh-pfc: Use devm_kzalloc()
sh-pfc: Move platform device and driver to the core
sh-pfc: Merge PFC core and gpio
sh-pfc: Merge PFC core and pinctrl
sh-pfc: Move private definitions and declarations to private header
sh-pfc: Split platform data from the sh_pfc structure
sh-pfc: Remove all use of __devinit/__devexit

sh-soc:
sh: shx3: Fix last GPIO index
sh: sh7786: Fix last GPIO index
sh: sh7786: Fix port E, G and J GPIOs
sh: sh7757: Fix GPIO_FN_ET0_MDIO and GPIO_FN_ET1_MDIO GPIO entries
sh: sh7723: Rename GPIO_FN_SIUOSPD to GPIO_FN_SIUAOSPD
sh: sh7269: Rename CRX0CRX1(CRX2) marks to match GPIO names
sh: sh7264: Rename CRX0CRX1 mark to match GPIO names

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Simon Horman]

On Tue, Jan 15, 2013 at 10:10:19AM +0900, Simon Horman wrote:
> On Sat, Jan 12, 2013 at 06:18:54PM +0100, Guennadi Liakhovetski wrote:
> > Hi Laurent
> > 
> > On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> > 
> > > Support device instantiation through the device tree. The compatible
> > > property is used to select the SoC pinmux information.
> > > 
> > > Set the gpio_chip device field to the PFC device to enable automatic
> > > GPIO OF support.
> > > 
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > Cc: devicetree-discuss@lists.ozlabs.org
> > 
> > This whole pinctrl mega-series is a very welcome improvement to the 
> > sh-/r-mobile GPIO framework, and is very well done IMHO! But, 
> > unfortunately, as discussed with you privately yesterday, there is still a 
> > problem with pinctrl DT support on sh73a0, which will, probably, enforce 
> > an update to one or several of patches from this lot. To explain to other 
> > readers, on sh73a0 pin numbers are not contiguous, they are sparse. 
> > When pins are referred to from C code, macro names are used, which are 
> > then correctly decoded to respective positions in pin descriptor tables. 
> > Whereas with DT, pins are referred to from .dts files using their physical 
> > numbers, which then refer to either wrong or missing entries in those 
> > tables.
> > 
> > I do not know where this problem should be solved best - either in 
> > descriptor tables, or in DT handling code, so, I don't know which patches 
> > would be affected. Don't think you'll want to keep the one-to-one 
> > index-to-pin mapping by also making pin-descriptor arrays sparse, so, so 
> > far I only see one possibility to fix this - by using the .enum_id field 
> > from struct sh_pfc_pin instead of just the index - both in  C and in DT 
> > case, and those .enum_id values will have to provide physical pin numbers 
> > instead of plane indices. That way you'd have to update at least 
> > drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the sh_pfc_map_gpios() function in 
> > drivers/pinctrl/sh-pfc/pinctrl.c.
> > 
> > Anyway, I'm sure you'll find a suitable solution of this problem and for 
> > now I'll let Simon decide which patches he wants to apply and which ones 
> > he'd prefer to hold back;-)
> 
> Actually, I'd appreciate some guidance from Laurent on this.
> It seems that the problems you raise go quite far back into the mega-series.
> 
> I was intending to send pull requests for the following branches soon.
> But I am now concerned that at least the sh73a0 patches may need reworking.

I have concluded that the changes below are safe and have
proceeded with sending them to arm-soc. However, I am still awaiting
a response from arm-soc.

> pfc2: (based on a merge of sh-soc2 and pfc)
> sh-pfc: Add shx3 pinmux support
> sh-pfc: Add sh7786 pinmux support
> sh-pfc: Add sh7785 pinmux support
> sh-pfc: Add sh7757 pinmux support
> sh-pfc: Add sh7734 pinmux support
> sh-pfc: Add sh7724 pinmux support
> sh-pfc: Add sh7723 pinmux support
> sh-pfc: Add sh7722 pinmux support
> sh-pfc: Add sh7720 pinmux support
> sh-pfc: Add sh7269 pinmux support
> sh-pfc: Add sh7264 pinmux support
> sh-pfc: Add sh7203 pinmux support
> sh-pfc: Add sh73a0 pinmux support
> sh-pfc: Add sh7372 pinmux support
> sh-pfc: Add r8a7779 pinmux support
> sh-pfc: Add r8a7740 pinmux support
> sh-pfc: Support pinmux info in driver data instead of platform data
> sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/
> sh-pfc: Remove unused resource and num_resources platform data fields
> sh-pfc: Remove platform device registration
> 
> sh-soc2: (based on pfc)
> sh: shx3: Register PFC platform device
> sh: sh7786: Register PFC platform device
> sh: sh7785: Register PFC platform device
> sh: sh7757: Register PFC platform device
> sh: sh7734: Register PFC platform device
> sh: sh7724: Register PFC platform device
> sh: sh7723: Register PFC platform device
> sh: sh7722: Register PFC platform device
> sh: sh7720: Register PFC platform device
> sh: sh7269: Register PFC platform device
> sh: sh7264: Register PFC platform device
> sh: sh7203: Register PFC platform device
> sh: Add PFC platform device registration helper function
> 
> 
> soc: (based on sh-soc)
> ARM: shmobile: sh73a0: Add pin control resources
> ARM: shmobile: sh7372: Add pin control resources
> ARM: shmobile: r8a7740: Add pin control resources
> ARM: shmobile: sh73a0: Register PFC platform device
> ARM: shmobile: sh7372: Register PFC platform device
> ARM: shmobile: r8a7779: Register PFC platform device
> ARM: shmobile: r8a7740: Register PFC platform device
> ARM: shmobile: Select PINCTRL
> ARM: shmobile: add function declarations for sh7372 DT helper functions
> ARM: sh7372: fix cache clean / invalidate order
> ARM: sh7372: add clock lookup entries for DT-based devices
> ARM: mach-shmobile: sh73a0 external IRQ wake update
> ARM: shmobile: sh73a0: fixup div4_clks bitmap
> ARM: shmobile: r8a7740: add TMU timer support
> ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c
> 
> pfc: (based on sh-soc)
> sh-pfc: Support passing resources through platform device
> sh-pfc: Split platform device and platform driver registration
> sh-pfc: Use sh_pfc_ namespace prefix through the whole driver
> sh-pfc: Sort headers alphabetically
> sh-pfc: Remove check for impossible error condition
> sh-pfc: Let the compiler decide whether to inline functions
> sh-pfc: Use devm_ioremap_nocache()
> sh-pfc: Use devm_kzalloc()
> sh-pfc: Move platform device and driver to the core
> sh-pfc: Merge PFC core and gpio
> sh-pfc: Merge PFC core and pinctrl
> sh-pfc: Move private definitions and declarations to private header
> sh-pfc: Split platform data from the sh_pfc structure
> sh-pfc: Remove all use of __devinit/__devexit
> 
> sh-soc:
> sh: shx3: Fix last GPIO index
> sh: sh7786: Fix last GPIO index
> sh: sh7786: Fix port E, G and J GPIOs
> sh: sh7757: Fix GPIO_FN_ET0_MDIO and GPIO_FN_ET1_MDIO GPIO entries
> sh: sh7723: Rename GPIO_FN_SIUOSPD to GPIO_FN_SIUAOSPD
> sh: sh7269: Rename CRX0CRX1(CRX2) marks to match GPIO names
> sh: sh7264: Rename CRX0CRX1 mark to match GPIO names
> --
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> 

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Laurent Pinchart]

Hi Simon,

On Monday 21 January 2013 09:38:28 Simon Horman wrote:
> On Tue, Jan 15, 2013 at 10:10:19AM +0900, Simon Horman wrote:
> > On Sat, Jan 12, 2013 at 06:18:54PM +0100, Guennadi Liakhovetski wrote:
> > > On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> > > > Support device instantiation through the device tree. The compatible
> > > > property is used to select the SoC pinmux information.
> > > > 
> > > > Set the gpio_chip device field to the PFC device to enable automatic
> > > > GPIO OF support.
> > > > 
> > > > Signed-off-by: Laurent Pinchart
> > > > <laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
> > > > Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> > > 
> > > This whole pinctrl mega-series is a very welcome improvement to the
> > > sh-/r-mobile GPIO framework, and is very well done IMHO! But,
> > > unfortunately, as discussed with you privately yesterday, there is still
> > > a problem with pinctrl DT support on sh73a0, which will, probably,
> > > enforce an update to one or several of patches from this lot. To explain
> > > to other readers, on sh73a0 pin numbers are not contiguous, they are
> > > sparse. When pins are referred to from C code, macro names are used,
> > > which are then correctly decoded to respective positions in pin
> > > descriptor tables. Whereas with DT, pins are referred to from .dts files
> > > using their physical numbers, which then refer to either wrong or
> > > missing entries in those tables.
> > > 
> > > I do not know where this problem should be solved best - either in
> > > descriptor tables, or in DT handling code, so, I don't know which
> > > patches would be affected. Don't think you'll want to keep the one-to-
> > > one index-to-pin mapping by also making pin-descriptor arrays sparse,
> > > so, so far I only see one possibility to fix this - by using the
> > > .enum_id field from struct sh_pfc_pin instead of just the index - both
> > > in  C and in DT case, and those .enum_id values will have to provide
> > > physical pin numbers instead of plane indices. That way you'd have to
> > > update at least drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the
> > > sh_pfc_map_gpios() function in drivers/pinctrl/sh-pfc/pinctrl.c.
> > > 
> > > Anyway, I'm sure you'll find a suitable solution of this problem and for
> > > now I'll let Simon decide which patches he wants to apply and which ones
> > > he'd prefer to hold back;-)
> > 
> > Actually, I'd appreciate some guidance from Laurent on this.
> > It seems that the problems you raise go quite far back into the
> > mega-series.
> > 
> > I was intending to send pull requests for the following branches soon.
> > But I am now concerned that at least the sh73a0 patches may need
> > reworking.
> 
> I have concluded that the changes below are safe and have
> proceeded with sending them to arm-soc. However, I am still awaiting
> a response from arm-soc.

Sorry for the late reply. The below changes are indeed safe, what I need to 
rework are the pinctrl API and DT series.

> > pfc2: (based on a merge of sh-soc2 and pfc)
> > sh-pfc: Add shx3 pinmux support
> > sh-pfc: Add sh7786 pinmux support
> > sh-pfc: Add sh7785 pinmux support
> > sh-pfc: Add sh7757 pinmux support
> > sh-pfc: Add sh7734 pinmux support
> > sh-pfc: Add sh7724 pinmux support
> > sh-pfc: Add sh7723 pinmux support
> > sh-pfc: Add sh7722 pinmux support
> > sh-pfc: Add sh7720 pinmux support
> > sh-pfc: Add sh7269 pinmux support
> > sh-pfc: Add sh7264 pinmux support
> > sh-pfc: Add sh7203 pinmux support
> > sh-pfc: Add sh73a0 pinmux support
> > sh-pfc: Add sh7372 pinmux support
> > sh-pfc: Add r8a7779 pinmux support
> > sh-pfc: Add r8a7740 pinmux support
> > sh-pfc: Support pinmux info in driver data instead of platform data
> > sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/
> > sh-pfc: Remove unused resource and num_resources platform data fields
> > sh-pfc: Remove platform device registration
> > 
> > sh-soc2: (based on pfc)
> > sh: shx3: Register PFC platform device
> > sh: sh7786: Register PFC platform device
> > sh: sh7785: Register PFC platform device
> > sh: sh7757: Register PFC platform device
> > sh: sh7734: Register PFC platform device
> > sh: sh7724: Register PFC platform device
> > sh: sh7723: Register PFC platform device
> > sh: sh7722: Register PFC platform device
> > sh: sh7720: Register PFC platform device
> > sh: sh7269: Register PFC platform device
> > sh: sh7264: Register PFC platform device
> > sh: sh7203: Register PFC platform device
> > sh: Add PFC platform device registration helper function
> > 
> > 
> > soc: (based on sh-soc)
> > ARM: shmobile: sh73a0: Add pin control resources
> > ARM: shmobile: sh7372: Add pin control resources
> > ARM: shmobile: r8a7740: Add pin control resources
> > ARM: shmobile: sh73a0: Register PFC platform device
> > ARM: shmobile: sh7372: Register PFC platform device
> > ARM: shmobile: r8a7779: Register PFC platform device
> > ARM: shmobile: r8a7740: Register PFC platform device
> > ARM: shmobile: Select PINCTRL
> > ARM: shmobile: add function declarations for sh7372 DT helper functions
> > ARM: sh7372: fix cache clean / invalidate order
> > ARM: sh7372: add clock lookup entries for DT-based devices
> > ARM: mach-shmobile: sh73a0 external IRQ wake update
> > ARM: shmobile: sh73a0: fixup div4_clks bitmap
> > ARM: shmobile: r8a7740: add TMU timer support
> > ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in
> > setup-r8a7740.c
> > 
> > pfc: (based on sh-soc)
> > sh-pfc: Support passing resources through platform device
> > sh-pfc: Split platform device and platform driver registration
> > sh-pfc: Use sh_pfc_ namespace prefix through the whole driver
> > sh-pfc: Sort headers alphabetically
> > sh-pfc: Remove check for impossible error condition
> > sh-pfc: Let the compiler decide whether to inline functions
> > sh-pfc: Use devm_ioremap_nocache()
> > sh-pfc: Use devm_kzalloc()
> > sh-pfc: Move platform device and driver to the core
> > sh-pfc: Merge PFC core and gpio
> > sh-pfc: Merge PFC core and pinctrl
> > sh-pfc: Move private definitions and declarations to private header
> > sh-pfc: Split platform data from the sh_pfc structure
> > sh-pfc: Remove all use of __devinit/__devexit
> > 
> > sh-soc:
> > sh: shx3: Fix last GPIO index
> > sh: sh7786: Fix last GPIO index
> > sh: sh7786: Fix port E, G and J GPIOs
> > sh: sh7757: Fix GPIO_FN_ET0_MDIO and GPIO_FN_ET1_MDIO GPIO entries
> > sh: sh7723: Rename GPIO_FN_SIUOSPD to GPIO_FN_SIUAOSPD
> > sh: sh7269: Rename CRX0CRX1(CRX2) marks to match GPIO names
> > sh: sh7264: Rename CRX0CRX1 mark to match GPIO names

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Simon Horman]

On Thu, Jan 24, 2013 at 12:17:32PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> On Monday 21 January 2013 09:38:28 Simon Horman wrote:
> > On Tue, Jan 15, 2013 at 10:10:19AM +0900, Simon Horman wrote:
> > > On Sat, Jan 12, 2013 at 06:18:54PM +0100, Guennadi Liakhovetski wrote:
> > > > On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> > > > > Support device instantiation through the device tree. The compatible
> > > > > property is used to select the SoC pinmux information.
> > > > > 
> > > > > Set the gpio_chip device field to the PFC device to enable automatic
> > > > > GPIO OF support.
> > > > > 
> > > > > Signed-off-by: Laurent Pinchart
> > > > > <laurent.pinchart+renesas@ideasonboard.com>
> > > > > Cc: devicetree-discuss@lists.ozlabs.org
> > > > 
> > > > This whole pinctrl mega-series is a very welcome improvement to the
> > > > sh-/r-mobile GPIO framework, and is very well done IMHO! But,
> > > > unfortunately, as discussed with you privately yesterday, there is still
> > > > a problem with pinctrl DT support on sh73a0, which will, probably,
> > > > enforce an update to one or several of patches from this lot. To explain
> > > > to other readers, on sh73a0 pin numbers are not contiguous, they are
> > > > sparse. When pins are referred to from C code, macro names are used,
> > > > which are then correctly decoded to respective positions in pin
> > > > descriptor tables. Whereas with DT, pins are referred to from .dts files
> > > > using their physical numbers, which then refer to either wrong or
> > > > missing entries in those tables.
> > > > 
> > > > I do not know where this problem should be solved best - either in
> > > > descriptor tables, or in DT handling code, so, I don't know which
> > > > patches would be affected. Don't think you'll want to keep the one-to-
> > > > one index-to-pin mapping by also making pin-descriptor arrays sparse,
> > > > so, so far I only see one possibility to fix this - by using the
> > > > .enum_id field from struct sh_pfc_pin instead of just the index - both
> > > > in  C and in DT case, and those .enum_id values will have to provide
> > > > physical pin numbers instead of plane indices. That way you'd have to
> > > > update at least drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the
> > > > sh_pfc_map_gpios() function in drivers/pinctrl/sh-pfc/pinctrl.c.
> > > > 
> > > > Anyway, I'm sure you'll find a suitable solution of this problem and for
> > > > now I'll let Simon decide which patches he wants to apply and which ones
> > > > he'd prefer to hold back;-)
> > > 
> > > Actually, I'd appreciate some guidance from Laurent on this.
> > > It seems that the problems you raise go quite far back into the
> > > mega-series.
> > > 
> > > I was intending to send pull requests for the following branches soon.
> > > But I am now concerned that at least the sh73a0 patches may need
> > > reworking.
> > 
> > I have concluded that the changes below are safe and have
> > proceeded with sending them to arm-soc. However, I am still awaiting
> > a response from arm-soc.
> 
> Sorry for the late reply. The below changes are indeed safe, what I need to 
> rework are the pinctrl API and DT series.

Thanks. After some discussions with arm-soc I have finally sent a
pull-request for these changes which now live in the pfc branch of
my renesas tree.

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Laurent Pinchart]

Hi Guennadi,

On Saturday 12 January 2013 18:18:54 Guennadi Liakhovetski wrote:
> On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> > Support device instantiation through the device tree. The compatible
> > property is used to select the SoC pinmux information.
> > 
> > Set the gpio_chip device field to the PFC device to enable automatic
> > GPIO OF support.
> > 
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com>
> > Cc: devicetree-discuss@lists.ozlabs.org
> 
> This whole pinctrl mega-series is a very welcome improvement to the
> sh-/r-mobile GPIO framework, and is very well done IMHO! But,
> unfortunately, as discussed with you privately yesterday, there is still a
> problem with pinctrl DT support on sh73a0, which will, probably, enforce
> an update to one or several of patches from this lot. To explain to other
> readers, on sh73a0 pin numbers are not contiguous, they are sparse.
> When pins are referred to from C code, macro names are used, which are
> then correctly decoded to respective positions in pin descriptor tables.
> Whereas with DT, pins are referred to from .dts files using their physical
> numbers, which then refer to either wrong or missing entries in those
> tables.
> 
> I do not know where this problem should be solved best - either in
> descriptor tables, or in DT handling code, so, I don't know which patches
> would be affected. Don't think you'll want to keep the one-to-one
> index-to-pin mapping by also making pin-descriptor arrays sparse, so, so
> far I only see one possibility to fix this - by using the .enum_id field
> from struct sh_pfc_pin instead of just the index - both in  C and in DT
> case, and those .enum_id values will have to provide physical pin numbers
> instead of plane indices.

I was thinking about something similar as well. I will use physical pin 
numbers, but I then need to find a way to number the pins, as they're not 
numbered in the documentation. Opinions on possible numbering schemes from 
anyone familiar with several SoCs both in SH Mobile and SuperH will be 
appreciated.

> That way you'd have to update at least drivers/pinctrl/sh-pfc/pfc-sh73a0.c
> and the sh_pfc_map_gpios() function in drivers/pinctrl/sh-pfc/pinctrl.c.
> 
> Anyway, I'm sure you'll find a suitable solution of this problem and for
> now I'll let Simon decide which patches he wants to apply and which ones
> he'd prefer to hold back;-)

-- 
Regards,

Laurent Pinchart