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Thu, 8 Aug 2024 02:38:46 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 8 Aug 2024 02:38:46 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 8 Aug 2024 02:38:45 -0500 Received: from [10.24.68.216] (a0498981-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.216]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4787cgrG016932; Thu, 8 Aug 2024 02:38:42 -0500 Message-ID: <1319a6ac-6784-45d6-8a0e-170e40d3aa18@ti.com> Date: Thu, 8 Aug 2024 13:08:41 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: ti: k3-am68-sk-base-board: Add clklb pin mux for mmc1 Content-Language: en-US To: Neha Malcom Francis , , CC: , , , , , , , , References: <20240807101624.2713490-1-b-kapoor@ti.com> <8fa39624-9a92-404d-8651-9ade5700a7d3@ti.com> From: Bhavya Kapoor In-Reply-To: <8fa39624-9a92-404d-8651-9ade5700a7d3@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Hi Neha, On 08/08/24 11:51 am, Neha Malcom Francis wrote: > Hi Bhavya > > On 07/08/24 15:46, Bhavya Kapoor wrote: >> mmc1 was not functional since pin mux for clklb was not present. >> Thus, add clklb pin mux to get MMC working. >> >> Fixes: a266c180b398 ("arm64: dts: ti: k3-am68-sk: Add support for >> AM68 SK base board") >> Signed-off-by: Bhavya Kapoor >> --- >> >> rebased to next-20240807 >> >>   arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 1 + >>   1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts >> b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts >> index 90dbe31c5b81..d5ceab79536c 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts >> +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts >> @@ -204,6 +204,7 @@ main_mmc1_pins_default: main-mmc1-default-pins { >>           pinctrl-single,pins = < >>               J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ >>               J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ >> +            J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ >>               J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ >>               J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ >>               J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ > > How is this different from the P23 pinmux for MMC1_CLK? Could you > explain what CLKLB is, since it doesn't have a ball number I'm finding > it difficult to understand what it is? > This pin needs to be setup so that MMC_CLK is looped back at pad level for highspeed SDIO operations (has been same across K3 family). MMC0/1 has this pin configured as INPUT by reset default as these have boot media  These pinmuxes are derived from pinmux file shared by EVM team during wakeup/board bringup. Regards