* [PATCH v2 0/4] Versatile Express DT support
@ 2011-11-23 15:01 Pawel Moll
2011-11-23 15:01 ` [PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V Pawel Moll
` (4 more replies)
0 siblings, 5 replies; 24+ messages in thread
From: Pawel Moll @ 2011-11-23 15:01 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
Hello again,
This version of the series (hopefully) addresses all the suggestions
made by Dave, Rob and Russell.
The compatible values are specific for the tiles now and the memory
map variant is defined as a custom property in the motherboard node.
Tested on V2P-CA9 coretile both with ATAGs and DT and V2P-CA5s with DT.
All comments, as always, welcomed!
Pawel
Pawel Moll (4):
ARM: vexpress: Get rid of MMIO_P2V
ARM: vexpress: Add DT support in v2m
ARM: vexpress: Initial RS1 memory map support
ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
Documentation/devicetree/bindings/arm/vexpress | 101 ++++++++
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 192 +++++++++++++++
arch/arm/boot/dts/vexpress-v2m.dtsi | 191 +++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132 ++++++++++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 146 +++++++++++
arch/arm/include/asm/hardware/arm_timer.h | 5 +
arch/arm/mach-vexpress/Kconfig | 35 +++
arch/arm/mach-vexpress/Makefile | 1 +
arch/arm/mach-vexpress/Makefile.boot | 6 +
arch/arm/mach-vexpress/core.h | 21 ++-
arch/arm/mach-vexpress/ct-ca9x4.c | 52 +---
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++-
arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++--
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +-
arch/arm/mach-vexpress/platsmp.c | 4 +-
arch/arm/mach-vexpress/v2m.c | 265 ++++++++++++++++++---
arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115 +++++++++
18 files changed, 1272 insertions(+), 115 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V
2011-11-23 15:01 [PATCH v2 0/4] Versatile Express DT support Pawel Moll
@ 2011-11-23 15:01 ` Pawel Moll
[not found] ` <1322060508-11298-2-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-11-23 15:01 ` [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m Pawel Moll
` (3 subsequent siblings)
4 siblings, 1 reply; 24+ messages in thread
From: Pawel Moll @ 2011-11-23 15:01 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch gets rid of the MMIO_P2V and __MMPIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/include/asm/hardware/arm_timer.h | 5 ++
arch/arm/mach-vexpress/core.h | 11 ++-
arch/arm/mach-vexpress/ct-ca9x4.c | 52 +++-----------
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 ++--
arch/arm/mach-vexpress/include/mach/motherboard.h | 52 +++++++-------
arch/arm/mach-vexpress/platsmp.c | 4 +-
arch/arm/mach-vexpress/v2m.c | 76 +++++++++++++--------
7 files changed, 104 insertions(+), 109 deletions(-)
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7b..d6030ff 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
*
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
* can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
*/
+#define TIMER_1_BASE 0x00
+#define TIMER_2_BASE 0x20
+
#define TIMER_LOAD 0x00 /* ACVR rw */
#define TIMER_VALUE 0x04 /* ACVR ro */
#define TIMER_CTRL 0x08 /* ACVR rw */
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f439715..d3dd491 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x) (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
-#define MMIO_P2V(x) ((void __iomem *)__MMIO_P2V(x))
-
#define AMBA_DEVICE(name,busid,base,plat) \
struct amba_device name##_device = { \
.dev = { \
@@ -17,3 +14,11 @@ struct amba_device name##_device = { \
.irq = IRQ_##base, \
/* .dma = DMA_##base,*/ \
}
+
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH 0xf8000000
+#define V2M_PERIPH_P2V(offset) ((void __iomem *)(V2M_PERIPH | (offset)))
+
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH 0xf8200000
+#define V2T_PERIPH_P2V(offset) ((void __iomem *)(V2T_PERIPH | (offset)))
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836..bfd3919 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,26 @@
#include <plat/clcd.h>
-#define V2M_PA_CS7 0x10000000
-
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
{
- .virtual = __MMIO_P2V(CT_CA9X4_MPIC),
- .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
- .pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = __MMIO_P2V(CT_CA9X4_L2CC),
- .pfn = __phys_to_pfn(CT_CA9X4_L2CC),
- .length = SZ_4K,
- .type = MT_DEVICE,
+ .virtual = V2T_PERIPH,
+ .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
},
};
static void __init ct_ca9x4_map_io(void)
{
-#ifdef CONFIG_LOCAL_TIMERS
- twd_base = MMIO_P2V(A9_MPCORE_TWD);
-#endif
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
static void __init ct_ca9x4_init_irq(void)
{
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
- MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
- writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- "ct-timer0");
+ gic_init(0, 29, V2T_PERIPH_P2V(A9_MPCORE_GIC_DIST),
+ V2T_PERIPH_P2V(A9_MPCORE_GIC_CPU));
}
-static struct sys_timer ct_ca9x4_timer = {
- .init = ct_ca9x4_timer_init,
-};
-#endif
-
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -193,6 +162,9 @@ static struct platform_device pmu_device = {
static void __init ct_ca9x4_init_early(void)
{
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = V2T_PERIPH_P2V(A9_MPCORE_TWD);
+#endif
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
}
@@ -201,7 +173,7 @@ static void __init ct_ca9x4_init(void)
int i;
#ifdef CONFIG_CACHE_L2X0
- void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+ void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
/* set RAM latencies to 1 cycle for this core tile. */
writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -219,7 +191,7 @@ static void __init ct_ca9x4_init(void)
#ifdef CONFIG_SMP
static void ct_ca9x4_init_cpu_map(void)
{
- int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
+ int i, ncores = scu_get_core_count(V2T_PERIPH_P2V(A9_MPCORE_SCU));
if (ncores > nr_cpu_ids) {
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
@@ -235,7 +207,7 @@ static void ct_ca9x4_init_cpu_map(void)
static void ct_ca9x4_smp_enable(unsigned int max_cpus)
{
- scu_enable(MMIO_P2V(A9_MPCORE_SCU));
+ scu_enable(V2T_PERIPH_P2V(A9_MPCORE_SCU));
}
#endif
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index a34d3d4..8f962fb 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -22,14 +22,11 @@
#define CT_CA9X4_SYSWDT (0x1e007000)
#define CT_CA9X4_L2CC (0x1e00a000)
-#define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000)
-#define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020)
-
-#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
-#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
-#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
-#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600)
-#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
+#define A9_MPCORE_SCU 0x0000
+#define A9_MPCORE_GIC_CPU 0x0100
+#define A9_MPCORE_GIT 0x0200
+#define A9_MPCORE_TWD 0x0600
+#define A9_MPCORE_GIC_DIST 0x1000
/*
* Interrupts. Those in {} are for AMBA devices
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 0a3a375..b4c498c 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -39,33 +39,30 @@
#define V2M_CF (V2M_PA_CS7 + 0x0001a000)
#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000)
-#define V2M_SYS_ID (V2M_SYSREGS + 0x000)
-#define V2M_SYS_SW (V2M_SYSREGS + 0x004)
-#define V2M_SYS_LED (V2M_SYSREGS + 0x008)
-#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024)
-#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034)
-#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_MCI (V2M_SYSREGS + 0x048)
-#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058)
-#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c)
-#define V2M_SYS_MISC (V2M_SYSREGS + 0x060)
-#define V2M_SYS_DMA (V2M_SYSREGS + 0x064)
-#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084)
-#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088)
-#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
-#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
-#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
-
-#define V2M_TIMER0 (V2M_TIMER01 + 0x000)
-#define V2M_TIMER1 (V2M_TIMER01 + 0x020)
-
-#define V2M_TIMER2 (V2M_TIMER23 + 0x000)
-#define V2M_TIMER3 (V2M_TIMER23 + 0x020)
+/*
+ * Offsets from SYSREGS base
+ */
+#define V2M_SYS_ID 0x000
+#define V2M_SYS_SW 0x004
+#define V2M_SYS_LED 0x008
+#define V2M_SYS_100HZ 0x024
+#define V2M_SYS_FLAGS 0x030
+#define V2M_SYS_FLAGSSET 0x030
+#define V2M_SYS_FLAGSCLR 0x034
+#define V2M_SYS_NVFLAGS 0x038
+#define V2M_SYS_NVFLAGSSET 0x038
+#define V2M_SYS_NVFLAGSCLR 0x03c
+#define V2M_SYS_MCI 0x048
+#define V2M_SYS_FLASH 0x03c
+#define V2M_SYS_CFGSW 0x058
+#define V2M_SYS_24MHZ 0x05c
+#define V2M_SYS_MISC 0x060
+#define V2M_SYS_DMA 0x064
+#define V2M_SYS_PROCID0 0x084
+#define V2M_SYS_PROCID1 0x088
+#define V2M_SYS_CFGDATA 0x0a0
+#define V2M_SYS_CFGCTRL 0x0a4
+#define V2M_SYS_CFGSTAT 0x0a8
/*
@@ -117,6 +114,7 @@
int v2m_cfg_write(u32 devfn, u32 data);
int v2m_cfg_read(u32 devfn, u32 *data);
+void v2m_flags_set(u32 data);
/*
* Core tile IDs
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 2b5f7ac..e8be99d 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -45,7 +45,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
- writel(BSYM(virt_to_phys(versatile_secondary_startup)),
- MMIO_P2V(V2M_SYS_FLAGSSET));
+ v2m_flags_set(BSYM(virt_to_phys(versatile_secondary_startup)));
}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 1fafc32..ee52b35 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -39,29 +39,41 @@
static struct map_desc v2m_io_desc[] __initdata = {
{
- .virtual = __MMIO_P2V(V2M_PA_CS7),
+ .virtual = V2M_PERIPH,
.pfn = __phys_to_pfn(V2M_PA_CS7),
.length = SZ_128K,
.type = MT_DEVICE,
},
};
+static void __iomem *v2m_sysreg_base;
+
static void __init v2m_timer_init(void)
{
- u32 scctrl;
-
- /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
- scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
- scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
- scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
- writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
-
- writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
- sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
- "v2m-timer0");
+ void __iomem *sysctl_base;
+ void __iomem *timer01_base;
+
+ sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
+ WARN_ON(!sysctl_base);
+ if (sysctl_base) {
+ /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
+ u32 scctrl = readl(sysctl_base + SCCTRL);
+ scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
+ scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
+ writel(scctrl, sysctl_base + SCCTRL);
+ }
+
+ timer01_base = ioremap(V2M_TIMER01, SZ_4K);
+ WARN_ON(!timer01_base);
+ if (timer01_base) {
+ writel(0, timer01_base + TIMER_1_BASE + TIMER_CTRL);
+ writel(0, timer01_base + TIMER_2_BASE + TIMER_CTRL);
+
+ sp804_clocksource_init(timer01_base + TIMER_2_BASE,
+ "v2m-timer1");
+ sp804_clockevents_init(timer01_base + TIMER_1_BASE,
+ IRQ_V2M_TIMER0, "v2m-timer0");
+ }
}
static struct sys_timer v2m_timer = {
@@ -81,14 +93,14 @@ int v2m_cfg_write(u32 devfn, u32 data)
devfn |= SYS_CFG_START | SYS_CFG_WRITE;
spin_lock(&v2m_cfg_lock);
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
- writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
+ writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
- writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
- writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+ writel(data, v2m_sysreg_base + V2M_SYS_CFGDATA);
+ writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
do {
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
} while (val == 0);
spin_unlock(&v2m_cfg_lock);
@@ -102,22 +114,28 @@ int v2m_cfg_read(u32 devfn, u32 *data)
devfn |= SYS_CFG_START;
spin_lock(&v2m_cfg_lock);
- writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
- writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+ writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
+ writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
mb();
do {
cpu_relax();
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
} while (val == 0);
- *data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
+ *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
spin_unlock(&v2m_cfg_lock);
return !!(val & SYS_CFG_ERR);
}
+void __init v2m_flags_set(u32 data)
+{
+ writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
+ writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
+}
+
static struct resource v2m_pcie_i2c_resource = {
.start = V2M_SERIAL_BUS_PCI,
@@ -203,7 +221,7 @@ static struct platform_device v2m_usb_device = {
static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
{
- writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
+ writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
}
static struct physmap_flash_data v2m_flash_data = {
@@ -257,7 +275,7 @@ static struct platform_device v2m_cf_device = {
static unsigned int v2m_mmci_status(struct device *dev)
{
- return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
+ return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
}
static struct mmci_platform_data v2m_mmci_data = {
@@ -370,7 +388,7 @@ static void __init v2m_init_early(void)
{
ct_desc->init_early();
clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
- versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+ versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
}
static void v2m_power_off(void)
@@ -399,7 +417,8 @@ static void __init v2m_populate_ct_desc(void)
u32 current_tile_id;
ct_desc = NULL;
- current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
+ current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
+ & V2M_CT_ID_MASK;
for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
if (ct_descs[i]->id == current_tile_id)
@@ -413,6 +432,7 @@ static void __init v2m_populate_ct_desc(void)
static void __init v2m_map_io(void)
{
iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+ v2m_sysreg_base = V2M_PERIPH_P2V(V2M_SYSREGS);
v2m_populate_ct_desc();
ct_desc->map_io();
}
--
1.6.3.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m
2011-11-23 15:01 [PATCH v2 0/4] Versatile Express DT support Pawel Moll
2011-11-23 15:01 ` [PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V Pawel Moll
@ 2011-11-23 15:01 ` Pawel Moll
2011-11-23 16:10 ` Pawel Moll
[not found] ` <1322060508-11298-3-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-11-23 15:01 ` [PATCH v2 3/4] ARM: vexpress: Initial RS1 memory map support Pawel Moll
` (2 subsequent siblings)
4 siblings, 2 replies; 24+ messages in thread
From: Pawel Moll @ 2011-11-23 15:01 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch provides hooks for DT-based tile machine implementations
and adds Device Tree description for the motherboard.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
Documentation/devicetree/bindings/arm/vexpress | 101 +++++++++++
arch/arm/boot/dts/vexpress-v2m.dtsi | 191 +++++++++++++++++++++
arch/arm/mach-vexpress/Kconfig | 6 +
arch/arm/mach-vexpress/core.h | 10 +
arch/arm/mach-vexpress/include/mach/motherboard.h | 6 +
arch/arm/mach-vexpress/v2m.c | 141 ++++++++++++++-
6 files changed, 447 insertions(+), 8 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
diff --git a/Documentation/devicetree/bindings/arm/vexpress b/Documentation/devicetree/bindings/arm/vexpress
new file mode 100644
index 0000000..4b2c3bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress
@@ -0,0 +1,101 @@
+ARM Versatile Express boards family
+-----------------------------------
+
+ARM's Versatile Express platform consists of a motherboard
+and one or more daughterboards (tiles). The motherboard provides
+set of peripherals. Processor and RAM "live" on the tiles.
+Both parts of the system should be described in two separate
+Device Tree source files, with the tile's description including
+motherboard's file. As the motherboard can be initialized in one
+of different configurations ("memory maps"), care must be taken
+to include the correct one.
+
+Required properties in the root node:
+- compatible value:
+ compatible = "arm,vexpress-<model>";
+ where <model> is the full tile model name (as used in the tiles's
+ Technical Reference Manual), eg:
+ - for Coretile Express A5x2 (V2P-CA5s):
+ compatible = "arm,vexpress-v2p-ca5s";
+ - Coretile Express A9x4 (V2P-CA9):
+ compatible = "arm,vexpress-v2p-ca9";
+
+Current Linux implementation requires a "timer" alias pointing
+at one of the SP804 timer blocks to be used when tile is not using
+local timer source.
+
+Optional properties in the root node:
+- tile model name (use the same names as in the tile's Technical
+ Reference Manuals, eg. "V2P-CA5s")
+ model = "<model>";
+- tile's HBI number (unique ARM's board model ID, visible on the
+ PCB's silkscreen) in hexadecimal transcription:
+ arm,hbi = <0xhbi>
+ eg:
+ - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
+ arm,hbi = <0x191>;
+ - Coretile Express A9x4 (V2P-CA9) HBI-0225:
+ arm,hbi = <0x225>;
+
+The motherboard description file provides single "motherboard" node
+using 2 address cells corresponding to the Static Memory Bus used
+between the motherboard and the tile. First cell defines Chip Select
+(CS) line number, the second cell address offset within the CS.
+All interrupts lines between the motherboard and the tile are active
+high and are described using single cell.
+
+Optional properties of the "motherboard" node:
+- motherboard's memory map variant:
+ arm,v2m-memory-map = "<name>";
+ where name is one of:
+ - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
+ referred to as "ARM Cortex-A Series memory map":
+ arm,v2m-memory-map = "rs1";
+ When this property is missing, the motherboard is using original
+ memory map (also known as "Legacy memory map") with peripherals
+ on CS7.
+
+Motherboard .dtsi files provide set of phandles to peripherals that
+can be used in the tile's aliases node:
+- UARTs:
+ mb_serial0, mb_serial1, mb_serial2 and mb_serial3
+- I2C controllers:
+ mb_i2c_dvi and mb_i2c_pcie
+- SP804 timers:
+ mb_timer01 and mb_timer23
+
+The tile description must define "ranges", "interrupt-map-mask" and
+"interrupt-map" properties to translate the motherboard's address
+and interrupt space into one used by the tile's processor.
+
+Abbreviated example:
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA5s";
+ arm,hbi = <0x225>;
+ compatible = "arm,vexpress-v2p-ca5s";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &mb_serial0;
+ timer = &mb_timer01;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a9-gic";
+ };
+
+ motherboard {
+ /* CS0 is visible at 0x08000000 */
+ ranges = <0 0 0x08000000 0x04000000>;
+ interrupt-map-mask = <0 0 63>;
+ /* Active high IRQ 0 is connected to GIC's SPI0 */
+ interrupt-map = <0 0 0 &gic 0 0 4>;
+ };
+}
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
new file mode 100644
index 0000000..364e44c
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -0,0 +1,191 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * Original memory map ("Legacy memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m-rs1.dtsi!
+ */
+
+/ {
+ motherboard {
+ compatible = "simple-bus";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ flash@0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000>,
+ <1 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ psram@2,00000000 {
+ compatible = "mtd-ram";
+ reg = <2 0x00000000 0x02000000>;
+ bank-width = <4>;
+ };
+
+ ethernet@3,02000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <3 0x02000000 0x10000>;
+ interrupts = <15>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@3,03000000 {
+ compatible = "nxp,usb-isp1761";
+ reg = <3 0x03000000 0x20000>;
+ interrupts = <16>;
+ port1-otg;
+ };
+
+ iofpga@7,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 7 0 0x20000>;
+
+ sysreg@00000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x00000 0x1000>;
+ };
+
+ sysctl@01000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x01000 0x1000>;
+ };
+
+ /* PCI-E I2C bus */
+ mb_i2c_pcie: i2c@02000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x02000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie-switch@60 {
+ compatible = "idt,89hpes32h8";
+ reg = <0x60>;
+ };
+ };
+
+ aaci@04000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x04000 0x1000>;
+ interrupts = <11>;
+ };
+
+ mmci@05000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x05000 0x1000>;
+ interrupts = <9 10>;
+ };
+
+ kmi@06000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x06000 0x1000>;
+ interrupts = <12>;
+ };
+
+ kmi@07000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x07000 0x1000>;
+ interrupts = <13>;
+ };
+
+ mb_serial0: uart@09000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x09000 0x1000>;
+ interrupts = <5>;
+ };
+
+ mb_serial1: uart@0a000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a000 0x1000>;
+ interrupts = <6>;
+ };
+
+ mb_serial2: uart@0b000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b000 0x1000>;
+ interrupts = <7>;
+ };
+
+ mb_serial3: uart@0c000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c000 0x1000>;
+ interrupts = <8>;
+ };
+
+ wdt@0f000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f000 0x1000>;
+ interrupts = <0>;
+ };
+
+ mb_timer01: timer@11000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x11000 0x1000>;
+ interrupts = <2>;
+ };
+
+ mb_timer23: timer@12000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ };
+
+ /* DVI I2C bus */
+ mb_i2c_dvi: i2c@16000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x16000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dvi-transmitter@39 {
+ compatible = "sil,sii9022-tpi", "sil,sii9022";
+ reg = <0x39>;
+ };
+
+ dvi-transmitter@60 {
+ compatible = "sil,sii9022-cpi", "sil,sii9022";
+ reg = <0x60>;
+ };
+ };
+
+ rtc@17000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x17000 0x1000>;
+ interrupts = <4>;
+ };
+
+ compact-flash@1a000 {
+ compatible = "ata-generic";
+ reg = <0x1a000 0x100
+ 0x1a100 0xf00>;
+ reg-shift = <2>;
+ };
+
+ clcd@1f000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f000 0x1000>;
+ interrupts = <14>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 9311484..6a6fa22 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -9,4 +9,10 @@ config ARCH_VEXPRESS_CA9X4
select ARM_ERRATA_751472
select ARM_ERRATA_753970
+config ARCH_VEXPRESS_DT
+ bool
+ select OF
+ help
+ VE platform *requiring* Flattened Device Tree to boot.
+
endmenu
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index d3dd491..21cc48b 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -22,3 +22,13 @@ struct amba_device name##_device = { \
/* Tile's peripherals static mappings should start here */
#define V2T_PERIPH 0xf8200000
#define V2T_PERIPH_P2V(offset) ((void __iomem *)(V2T_PERIPH | (offset)))
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+extern struct sys_timer v2m_timer;
+
+void __init v2m_dt_map_io(void);
+void __init v2m_dt_init_early(void);
+struct of_dev_auxdata * __init v2m_dt_get_auxdata(void);
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index b4c498c..31a9289 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -117,6 +117,12 @@ int v2m_cfg_read(u32 devfn, u32 *data);
void v2m_flags_set(u32 data);
/*
+ * Miscellaneous
+ */
+#define SYS_MISC_MASTERSITE (1 << 14)
+#define SYS_PROCIDx_HBI_MASK 0xfff
+
+/*
* Core tile IDs
*/
#define V2M_CT_ID_CA9 0x0c000191
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index ee52b35..fd7ee1f 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -6,6 +6,10 @@
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/smsc911x.h>
@@ -17,6 +21,7 @@
#include <asm/mach-types.h>
#include <asm/sizes.h>
+#include <asm/system.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
@@ -50,10 +55,34 @@ static void __iomem *v2m_sysreg_base;
static void __init v2m_timer_init(void)
{
- void __iomem *sysctl_base;
- void __iomem *timer01_base;
+ void __iomem *sysctl_base = NULL;
+ void __iomem *timer01_base = NULL;
+ unsigned int timer01_irq = NO_IRQ;
+
+ if (of_have_populated_dt()) {
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+ int err;
+ const char *path;
+ struct device_node *node;
+
+ node = of_find_compatible_node(NULL, NULL, "arm,sp810");
+ if (node)
+ sysctl_base = of_iomap(node, 0);
+
+ err = of_property_read_string(of_aliases, "timer", &path);
+ if (!err)
+ node = of_find_node_by_path(path);
+ if (node) {
+ timer01_base = of_iomap(node, 0);
+ timer01_irq = irq_of_parse_and_map(node, 0);
+ }
+#endif
+ } else {
+ sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
+ timer01_base = ioremap(V2M_TIMER01, SZ_4K);
+ timer01_irq = IRQ_V2M_TIMER0;
+ }
- sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
WARN_ON(!sysctl_base);
if (sysctl_base) {
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
@@ -63,20 +92,20 @@ static void __init v2m_timer_init(void)
writel(scctrl, sysctl_base + SCCTRL);
}
- timer01_base = ioremap(V2M_TIMER01, SZ_4K);
- WARN_ON(!timer01_base);
- if (timer01_base) {
+ WARN_ON(!timer01_base || timer01_irq != NO_IRQ);
+ if (timer01_base && timer01_irq != NO_IRQ) {
writel(0, timer01_base + TIMER_1_BASE + TIMER_CTRL);
writel(0, timer01_base + TIMER_2_BASE + TIMER_CTRL);
sp804_clocksource_init(timer01_base + TIMER_2_BASE,
"v2m-timer1");
sp804_clockevents_init(timer01_base + TIMER_1_BASE,
- IRQ_V2M_TIMER0, "v2m-timer0");
+ timer01_irq, "v2m-timer0");
}
}
-static struct sys_timer v2m_timer = {
+/* Used also by DT-powered core tiles */
+struct sys_timer v2m_timer = {
.init = v2m_timer_init,
};
@@ -470,3 +499,99 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
.timer = &v2m_timer,
.init_machine = v2m_init,
MACHINE_END
+
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+void __init v2m_dt_map_io(void)
+{
+ iotable_init(v2m_rs1_io_desc, ARRAY_SIZE(v2m_rs1_io_desc));
+}
+
+static struct clk_lookup v2m_dt_lookups[] = {
+ { /* AMBA bus clock */
+ .con_id = "apb_pclk",
+ .clk = &dummy_apb_pclk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer0",
+ .clk = &v2m_sp804_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer1",
+ .clk = &v2m_sp804_clk,
+ }, { /* PL180 MMCI */
+ .dev_id = "mb:mmci", /* 10005000.mmci */
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI0 */
+ .dev_id = "10006000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI1 */
+ .dev_id = "10007000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART0 */
+ .dev_id = "10009000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART1 */
+ .dev_id = "1000a000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART2 */
+ .dev_id = "1000b000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART3 */
+ .dev_id = "1000c000.uart",
+ .clk = &osc2_clk,
+ }, { /* SP805 WDT */
+ .dev_id = "1000f000.wdt",
+ .clk = &v2m_ref_clk,
+ }, { /* PL111 CLCD */
+ .dev_id = "1001f000.clcd",
+ .clk = &osc1_clk,
+ },
+};
+
+void __init v2m_dt_init_early(void)
+{
+ struct device_node *node;
+ const __be32 *reg;
+ u32 dt_hbi;
+
+ node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
+ reg = of_get_property(node, "reg", NULL);
+ if (WARN_ON(!reg))
+ return;
+
+ v2m_sysreg_base = V2M_PERIPH_P2V(be32_to_cpup(reg));
+
+ /* Confirm board type against DT property, if available */
+ if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
+ u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
+ u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
+ V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
+ u32 hbi = id & SYS_PROCIDx_HBI_MASK;
+
+ if (WARN_ON(dt_hbi != hbi))
+ pr_warning("vexpress: DT HBI (%x) is not matching "
+ "hardware (%x)!\n", dt_hbi, hbi);
+ }
+
+ clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
+ versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+
+ pm_power_off = v2m_power_off;
+ arm_pm_restart = v2m_restart;
+}
+
+static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
+ &v2m_flash_data),
+ OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+ {}
+};
+
+struct of_dev_auxdata * __init v2m_dt_get_auxdata(void)
+{
+ return v2m_dt_auxdata_lookup;
+}
+
+#endif
--
1.6.3.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 3/4] ARM: vexpress: Initial RS1 memory map support
2011-11-23 15:01 [PATCH v2 0/4] Versatile Express DT support Pawel Moll
2011-11-23 15:01 ` [PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V Pawel Moll
2011-11-23 15:01 ` [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m Pawel Moll
@ 2011-11-23 15:01 ` Pawel Moll
2011-11-23 15:01 ` [PATCH v2 4/4] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4 Pawel Moll
[not found] ` <1322060508-11298-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
4 siblings, 0 replies; 24+ messages in thread
From: Pawel Moll @ 2011-11-23 15:01 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch adds support for RS1 memory map based Versatile Express
motherboard.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 192 +++++++++++++++++++++
arch/arm/mach-vexpress/Kconfig | 8 +
arch/arm/mach-vexpress/Makefile.boot | 6 +
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 ++++-
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/v2m.c | 64 +++++++-
6 files changed, 314 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 0000000..c8af670
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,192 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+ motherboard {
+ compatible = "simple-bus";
+ arm,v2m-memory-map = "rs1";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ flash@0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000>,
+ <4 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ psram@1,00000000 {
+ compatible = "mtd-ram";
+ reg = <1 0x00000000 0x02000000>;
+ bank-width = <4>;
+ };
+
+ ethernet@2,02000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <2 0x02000000 0x10000>;
+ interrupts = <15>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@2,03000000 {
+ compatible = "nxp,usb-isp1761";
+ reg = <2 0x03000000 0x20000>;
+ interrupts = <16>;
+ port1-otg;
+ };
+
+ iofpga@3,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 3 0 0x200000>;
+
+ sysreg@010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x010000 0x1000>;
+ };
+
+ sysctl@020000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ };
+
+ /* PCI-E I2C bus */
+ mb_i2c_pcie: i2c@030000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x030000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie-switch@60 {
+ compatible = "idt,89hpes32h8";
+ reg = <0x60>;
+ };
+ };
+
+ aaci@040000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x040000 0x1000>;
+ interrupts = <11>;
+ };
+
+ mmci@050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x050000 0x1000>;
+ interrupts = <9 10>;
+ };
+
+ kmi@060000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x060000 0x1000>;
+ interrupts = <12>;
+ };
+
+ kmi@070000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x070000 0x1000>;
+ interrupts = <13>;
+ };
+
+ mb_serial0: uart@090000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x090000 0x1000>;
+ interrupts = <5>;
+ };
+
+ mb_serial1: uart@0a0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a0000 0x1000>;
+ interrupts = <6>;
+ };
+
+ mb_serial2: uart@0b0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b0000 0x1000>;
+ interrupts = <7>;
+ };
+
+ mb_serial3: uart@0c0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c0000 0x1000>;
+ interrupts = <8>;
+ };
+
+ wdt@0f0000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f0000 0x1000>;
+ interrupts = <0>;
+ };
+
+ mb_timer01: timer@110000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x110000 0x1000>;
+ interrupts = <2>;
+ };
+
+ mb_timer23: timer@120000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x120000 0x1000>;
+ };
+
+ /* DVI I2C bus */
+ mb_i2c_dvi: i2c@160000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x160000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dvi-transmitter@39 {
+ compatible = "sil,sii9022-tpi", "sil,sii9022";
+ reg = <0x39>;
+ };
+
+ dvi-transmitter@60 {
+ compatible = "sil,sii9022-cpi", "sil,sii9022";
+ reg = <0x60>;
+ };
+ };
+
+ rtc@170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x170000 0x1000>;
+ interrupts = <4>;
+ };
+
+ compact-flash@1a0000 {
+ compatible = "ata-generic";
+ reg = <0x1a0000 0x100
+ 0x1a0100 0xf00>;
+ reg-shift = <2>;
+ };
+
+ clcd@1f0000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f0000 0x1000>;
+ interrupts = <14>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 6a6fa22..2180888 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -15,4 +15,12 @@ config ARCH_VEXPRESS_DT
help
VE platform *requiring* Flattened Device Tree to boot.
+config ARCH_VEXPRESS_RS1
+ bool
+ select AUTO_ZRELADDR
+ select ARM_PATCH_PHYS_VIRT
+ help
+ RS1 VE memory map (i.a. motherboard peripherals at
+ 0x1c000000, RAM at 0x80000000).
+
endmenu
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 8630b3d..05b77a5 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -1,3 +1,9 @@
+ifeq ($(CONFIG_ARCH_VEXPRESS_RS1),y)
+ zreladdr-y += 0x80008000
+params_phys-y := 0x80000100
+initrd_phys-y := 0x80800000
+else
zreladdr-y += 0x60008000
params_phys-y := 0x60000100
initrd_phys-y := 0x60800000
+endif
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fd9e6c7..8010ff9 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -10,12 +10,41 @@
* published by the Free Software Foundation.
*/
-#define DEBUG_LL_UART_OFFSET 0x00009000
+#define DEBUG_LL_PHYS_BASE 0x10000000
+#define DEBUG_LL_UART_OFFSET 0x00009000
+
+#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
+#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
+
+#define DEBUG_LL_VIRT_BASE 0xf8000000
.macro addruart,rp,rv,tmp
- mov \rp, #DEBUG_LL_UART_OFFSET
- orr \rv, \rp, #0xf8000000 @ virtual base
- orr \rp, \rp, #0x10000000 @ physical base
+
+ @ Check the MMU state
+#if defined(CONFIG_MMU)
+ mrc p15, 0, \tmp, c1, c0 @ SCTRL
+ tst \tmp, #1 @ MMU enabled?
+ moveq \tmp, #DEBUG_LL_PHYS_BASE
+ movne \tmp, #DEBUG_LL_VIRT_BASE
+#else
+ mov \tmp, #DEBUG_LL_PHYS_BASE
+#endif
+
+ @ PL011 present in "original" place?
+ orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
+ ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
+ teq \tmp, #0x11 @ PL011
+
+ @ Original memory map
+ moveq \rp, #DEBUG_LL_UART_OFFSET
+ orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
+ orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
+
+ @ RS1 memory map
+ movne \rp, #DEBUG_LL_UART_OFFSET_RS1
+ orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
+ orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+
.endm
#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7972c57..c491565 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -22,7 +22,18 @@
#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
-#define get_uart_base() (0x10000000 + 0x00009000)
+#define AMBA_PERIPH_ID0(base) (*(volatile unsigned char *)((base) + 0xfe0))
+
+#define UART_BASE 0x10009000
+#define UART_BASE_RS1 0x1c090000
+
+static unsigned long get_uart_base(void)
+{
+ if (AMBA_PERIPH_ID0(UART_BASE) == 0x11)
+ return UART_BASE;
+ else
+ return UART_BASE_RS1;
+}
/*
* This does not append a newline
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index fd7ee1f..7af6f36 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -92,7 +92,7 @@ static void __init v2m_timer_init(void)
writel(scctrl, sysctl_base + SCCTRL);
}
- WARN_ON(!timer01_base || timer01_irq != NO_IRQ);
+ WARN_ON(!timer01_base || timer01_irq == NO_IRQ);
if (timer01_base && timer01_irq != NO_IRQ) {
writel(0, timer01_base + TIMER_1_BASE + TIMER_CTRL);
writel(0, timer01_base + TIMER_2_BASE + TIMER_CTRL);
@@ -503,9 +503,38 @@ MACHINE_END
#if defined(CONFIG_ARCH_VEXPRESS_DT)
+static struct map_desc v2m_rs1_io_desc[] __initdata = {
+ {
+ .virtual = V2M_PERIPH,
+ .pfn = __phys_to_pfn(0x1c000000),
+ .length = SZ_2M,
+ .type = MT_DEVICE,
+ },
+};
+
+static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ const char **map = data;
+
+ if (strcmp(uname, "motherboard") != 0)
+ return 0;
+
+ *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
+
+ return 1;
+}
+
void __init v2m_dt_map_io(void)
{
+ const char *map = NULL;
+
+ of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
+
+ if (map && strcmp(map, "rs1") == 0)
iotable_init(v2m_rs1_io_desc, ARRAY_SIZE(v2m_rs1_io_desc));
+ else
+ iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
}
static struct clk_lookup v2m_dt_lookups[] = {
@@ -548,6 +577,35 @@ static struct clk_lookup v2m_dt_lookups[] = {
.dev_id = "1001f000.clcd",
.clk = &osc1_clk,
},
+ /* RS1 memory map */
+ { /* PL180 MMCI */
+ .dev_id = "mb:mmci", /* 1c050000.mmci */
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI0 */
+ .dev_id = "1c060000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI1 */
+ .dev_id = "1c070000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART0 */
+ .dev_id = "1c090000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART1 */
+ .dev_id = "1c0a0000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART2 */
+ .dev_id = "1c0b0000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART3 */
+ .dev_id = "1c0c0000.uart",
+ .clk = &osc2_clk,
+ }, { /* SP805 WDT */
+ .dev_id = "1c0f0000.wdt",
+ .clk = &v2m_ref_clk,
+ }, { /* PL111 CLCD */
+ .dev_id = "1c1f0000.clcd",
+ .clk = &osc1_clk,
+ },
};
void __init v2m_dt_init_early(void)
@@ -586,6 +644,10 @@ static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
&v2m_flash_data),
OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+ /* RS1 memory map */
+ OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
+ &v2m_flash_data),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
{}
};
--
1.6.3.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 4/4] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
2011-11-23 15:01 [PATCH v2 0/4] Versatile Express DT support Pawel Moll
` (2 preceding siblings ...)
2011-11-23 15:01 ` [PATCH v2 3/4] ARM: vexpress: Initial RS1 memory map support Pawel Moll
@ 2011-11-23 15:01 ` Pawel Moll
[not found] ` <1322060508-11298-5-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
[not found] ` <1322060508-11298-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
4 siblings, 1 reply; 24+ messages in thread
From: Pawel Moll @ 2011-11-23 15:01 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch adds Device Trees for ARM Ltd. CoreTile Express A5x2
and CoreTile Express A9x4 used with V2M motherboard and an initial
implementation of the DT machine support (this code is separate
from the current core tile code).
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132 ++++++++++++++++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 146 +++++++++++++++++++++++++++++++
arch/arm/mach-vexpress/Kconfig | 21 +++++
arch/arm/mach-vexpress/Makefile | 1 +
arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115 ++++++++++++++++++++++++
5 files changed, 415 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 0000000..84e05cd
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,132 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA5s";
+ arm,hbi = <0x225>;
+ compatible = "arm,vexpress-v2p-ca5s";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &mb_serial0;
+ serial1 = &mb_serial1;
+ serial2 = &mb_serial2;
+ serial3 = &mb_serial3;
+ i2c0 = &mb_i2c_dvi;
+ i2c1 = &mb_i2c_pcie;
+ timer = &mb_timer01;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ hdlcd@2a110000 {
+ compatible = "arm,hdlcd";
+ reg = <0x2a110000 0x1000>;
+ interrupts = <0 85 4>;
+ };
+
+ memory-controller@2a150000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x2a150000 0x1000>;
+ };
+
+ memory-controller@2a190000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x2a190000 0x1000>;
+ interrupts = <0 86 4>,
+ <0 87 4>;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2c001000 0x1000>,
+ <0x2c000100 0x100>;
+ };
+
+ L2: cache-controller@2c0f0000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x2c0f0000 0x1000>;
+ interrupts = <0 84 4>;
+ cache-level = <2>;
+ arm,data-latency = <0>;
+ arm,tag-latency = <0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 68 4>,
+ <0 69 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x08000000 0x04000000>,
+ <1 0 0x14000000 0x04000000>,
+ <2 0 0x18000000 0x04000000>,
+ <3 0 0x1c000000 0x04000000>,
+ <4 0 0x0c000000 0x04000000>,
+ <5 0 0x10000000 0x04000000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 0000000..ae6b70c
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,146 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA9";
+ arm,hbi = <0x191>;
+ compatible = "arm,vexpress-v2p-ca9";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &mb_serial0;
+ serial1 = &mb_serial1;
+ serial2 = &mb_serial2;
+ serial3 = &mb_serial3;
+ i2c0 = &mb_i2c_dvi;
+ i2c1 = &mb_i2c_pcie;
+ timer = &mb_timer01;
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ clcd@10020000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x10020000 0x1000>;
+ interrupts = <0 44 4>;
+ };
+
+ memory-controller@100e0000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x100e0000 0x1000>;
+ };
+
+ memory-controller@100e1000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x100e1000 0x1000>;
+ interrupts = <0 45 4>,
+ <0 46 4>;
+ };
+
+ timer@100e4000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x100e4000 0x1000>;
+ interrupts = <0 48 4>,
+ <0 49 4>;
+ };
+
+ watchdog@100e5000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x100e5000 0x1000>;
+ interrupts = <0 51 4>;
+ };
+
+ gic: interrupt-controller@1e001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1e001000 0x1000>,
+ <0x1e000100 0x100>;
+ };
+
+ L2: cache-controller@1e00a000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1e00a000 0x1000>;
+ interrupts = <0 43 4>;
+ cache-level = <2>;
+ arm,data-latency = <0>;
+ arm,tag-latency = <0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 60 4>,
+ <0 61 4>,
+ <0 62 4>,
+ <0 63 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x40000000 0x04000000>,
+ <1 0 0x44000000 0x04000000>,
+ <2 0 0x48000000 0x04000000>,
+ <3 0 0x4c000000 0x04000000>,
+ <7 0 0x10000000 0x00020000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m.dtsi"
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 2180888..0f31125 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -23,4 +23,25 @@ config ARCH_VEXPRESS_RS1
RS1 VE memory map (i.a. motherboard peripherals at
0x1c000000, RAM at 0x80000000).
+config ARCH_VEXPRESS_V2P_CA5S_CA9
+ bool "CoreTile Express A5x2 and A9x4 based platform support"
+ select ARCH_VEXPRESS_RS1
+ select ARCH_VEXPRESS_DT
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_751472
+ select ARM_ERRATA_753970
+ help
+ This option enables support for systems using any of the following
+ ARM core tiles on the Versatile Express motherboard:
+
+ - CoreTile Express A5x2 (V2P-CA5s)
+ - CoreTile Express A9x4 (V2P-CA9)
+
+ You must boot using a Flattened Device Tree in order to use these
+ platforms. The traditional (ATAGs) boot method is not usable on
+ these boards with this option.
+
+ If you want your kernel to run on one of these platforms and your
+ bootloader supports Flattened Device Tree based booting, say Y.
+
endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 90551b9..06e3687 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -4,5 +4,6 @@
obj-y := v2m.o
obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
+obj-$(CONFIG_ARCH_VEXPRESS_V2P_CA5S_CA9) += v2p-ca5s_ca9.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-vexpress/v2p-ca5s_ca9.c b/arch/arm/mach-vexpress/v2p-ca5s_ca9.c
new file mode 100644
index 0000000..5a1e1ea
--- /dev/null
+++ b/arch/arm/mach-vexpress/v2p-ca5s_ca9.c
@@ -0,0 +1,115 @@
+/*
+ * Device Tree based support for ARM Versatile Express platform using:
+ * - CoreTile Express A5x2 (V2P-CA5s)
+ * - CoreTile Express A9x4 (V2P-CA9)
+ */
+
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/motherboard.h>
+
+#include "core.h"
+
+#define A5_A9_MPCORE_SCU 0x0000
+#define A5_A9_MPCORE_TWD 0x0600
+
+static struct map_desc v2p_ca5s_ca9_io_desc[] __initdata = {
+ {
+ .virtual = V2T_PERIPH,
+ /* .pfn set in v2p_ca5s_ca9_map_io() */
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+ },
+};
+
+#ifdef CONFIG_SMP
+static void __init v2p_ca5s_ca9_init_cpu_map(void)
+{
+ int i, ncores = scu_get_core_count(V2T_PERIPH_P2V(A5_A9_MPCORE_SCU));
+
+ if (ncores > nr_cpu_ids) {
+ pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+ ncores, nr_cpu_ids);
+ ncores = nr_cpu_ids;
+ }
+
+ for (i = 0; i < ncores; ++i)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+static void __init v2p_ca5s_ca9_smp_enable(unsigned int max_cpus)
+{
+ scu_enable(V2T_PERIPH_P2V(A5_A9_MPCORE_SCU));
+}
+
+static struct ct_desc v2p_ca5s_ca9_smp_callbacks __initdata = {
+ .init_cpu_map = v2p_ca5s_ca9_init_cpu_map,
+ .smp_enable = v2p_ca5s_ca9_smp_enable,
+};
+#endif
+
+static void __init v2p_ca5s_ca9_map_io(void)
+{
+ u32 mpcore_periph;
+
+ asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (mpcore_periph));
+ v2p_ca5s_ca9_io_desc[0].pfn = __phys_to_pfn(mpcore_periph);
+ iotable_init(v2p_ca5s_ca9_io_desc, ARRAY_SIZE(v2p_ca5s_ca9_io_desc));
+
+ v2m_dt_map_io();
+
+#ifdef CONFIG_SMP
+ ct_desc = &v2p_ca5s_ca9_smp_callbacks;
+#endif
+}
+
+static void __init v2p_ca5s_ca9_init_early(void)
+{
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = V2T_PERIPH_P2V(A5_A9_MPCORE_TWD);
+#endif
+ v2m_dt_init_early();
+}
+
+static struct of_device_id v2p_ca5s_ca9_irq_match[] __initdata = {
+ { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ {}
+};
+
+static void __init v2p_ca5s_ca9_init_irq(void)
+{
+ of_irq_init(v2p_ca5s_ca9_irq_match);
+}
+
+static void __init v2p_ca5s_ca9_init(void)
+{
+ l2x0_of_init(0x00400000, 0xfe0fffff);
+ of_platform_populate(NULL, of_default_bus_match_table,
+ v2m_dt_get_auxdata(), NULL);
+}
+
+static const char *v2p_ca5s_ca9_dt_match[] __initdata = {
+ "arm,vexpress-v2p-ca5s",
+ "arm,vexpress-v2p-ca9",
+ NULL,
+};
+
+DT_MACHINE_START(VEXPRESS_V2P_CA5S_CA9, "ARM Versatile Express")
+ .map_io = v2p_ca5s_ca9_map_io,
+ .init_early = v2p_ca5s_ca9_init_early,
+ .init_irq = v2p_ca5s_ca9_init_irq,
+ .timer = &v2m_timer,
+ .init_machine = v2p_ca5s_ca9_init,
+ .dt_compat = v2p_ca5s_ca9_dt_match,
+MACHINE_END
--
1.6.3.3
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m
2011-11-23 15:01 ` [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m Pawel Moll
@ 2011-11-23 16:10 ` Pawel Moll
[not found] ` <1322060508-11298-3-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
1 sibling, 0 replies; 24+ messages in thread
From: Pawel Moll @ 2011-11-23 16:10 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel
On Wed, 2011-11-23 at 15:01 +0000, Pawel Moll wrote:
> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
> index ee52b35..fd7ee1f 100644
> --- a/arch/arm/mach-vexpress/v2m.c
> +++ b/arch/arm/mach-vexpress/v2m.c
[...]
> + node = of_find_compatible_node(NULL, NULL, "arm,sp810");
> + if (node)
> + sysctl_base = of_iomap(node, 0);
> +
> + err = of_property_read_string(of_aliases, "timer", &path);
> + if (!err)
> + node = of_find_node_by_path(path);
> + if (node) {
> + timer01_base = of_iomap(node, 0);
> + timer01_irq = irq_of_parse_and_map(node, 0);
> + }
I've just realized that this fragment should actually look like that:
node = of_find_compatible_node(NULL, NULL, "arm,sp810");
sysctl_base = of_iomap(node, 0);
err = of_property_read_string(of_aliases, "timer", &path);
if (!err) {
node = of_find_node_by_path(path);
timer01_base = of_iomap(node, 0);
timer01_irq = irq_of_parse_and_map(node, 0);
}
I will change that.
Cheers!
Pawel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V
[not found] ` <1322060508-11298-2-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
@ 2011-11-25 16:15 ` Dave Martin
2011-11-28 10:40 ` Pawel Moll
[not found] ` <20111125161500.GD2098-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
0 siblings, 2 replies; 24+ messages in thread
From: Dave Martin @ 2011-11-25 16:15 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wed, Nov 23, 2011 at 03:01:45PM +0000, Pawel Moll wrote:
> This patch gets rid of the MMIO_P2V and __MMPIO_P2V macros,
> defining constant virtual base for motherboard and tile
> peripherals instead.
>
> Additionally, in preparation for the new motherboard memory
> map, the motherboard peripherals are using base pointers
> calculated in runtime, instead of compile-time calculated
> values.
>
> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm/include/asm/hardware/arm_timer.h | 5 ++
> arch/arm/mach-vexpress/core.h | 11 ++-
> arch/arm/mach-vexpress/ct-ca9x4.c | 52 +++-----------
> arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 ++--
> arch/arm/mach-vexpress/include/mach/motherboard.h | 52 +++++++-------
> arch/arm/mach-vexpress/platsmp.c | 4 +-
> arch/arm/mach-vexpress/v2m.c | 76 +++++++++++++--------
> 7 files changed, 104 insertions(+), 109 deletions(-)
>
> diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
> index c0f4e7b..d6030ff 100644
> --- a/arch/arm/include/asm/hardware/arm_timer.h
> +++ b/arch/arm/include/asm/hardware/arm_timer.h
> @@ -9,7 +9,12 @@
> *
> * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
> * can have 16-bit or 32-bit selectable via a bit in the control register.
> + *
> + * Every SP804 contains two identical timers.
> */
> +#define TIMER_1_BASE 0x00
> +#define TIMER_2_BASE 0x20
> +
> #define TIMER_LOAD 0x00 /* ACVR rw */
> #define TIMER_VALUE 0x04 /* ACVR ro */
> #define TIMER_CTRL 0x08 /* ACVR rw */
> diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
> index f439715..d3dd491 100644
> --- a/arch/arm/mach-vexpress/core.h
> +++ b/arch/arm/mach-vexpress/core.h
> @@ -1,6 +1,3 @@
> -#define __MMIO_P2V(x) (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
> -#define MMIO_P2V(x) ((void __iomem *)__MMIO_P2V(x))
> -
> #define AMBA_DEVICE(name,busid,base,plat) \
> struct amba_device name##_device = { \
> .dev = { \
> @@ -17,3 +14,11 @@ struct amba_device name##_device = { \
> .irq = IRQ_##base, \
> /* .dma = DMA_##base,*/ \
> }
> +
> +/* 2MB large area for motherboard's peripherals static mapping */
> +#define V2M_PERIPH 0xf8000000
> +#define V2M_PERIPH_P2V(offset) ((void __iomem *)(V2M_PERIPH | (offset)))
> +
> +/* Tile's peripherals static mappings should start here */
> +#define V2T_PERIPH 0xf8200000
> +#define V2T_PERIPH_P2V(offset) ((void __iomem *)(V2T_PERIPH | (offset)))
> diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
> index 2b1e836..bfd3919 100644
> --- a/arch/arm/mach-vexpress/ct-ca9x4.c
> +++ b/arch/arm/mach-vexpress/ct-ca9x4.c
> @@ -30,57 +30,26 @@
>
> #include <plat/clcd.h>
>
> -#define V2M_PA_CS7 0x10000000
> -
> static struct map_desc ct_ca9x4_io_desc[] __initdata = {
> {
> - .virtual = __MMIO_P2V(CT_CA9X4_MPIC),
> - .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
> - .length = SZ_16K,
> - .type = MT_DEVICE,
> - }, {
> - .virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
> - .pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
> - .length = SZ_4K,
> - .type = MT_DEVICE,
> - }, {
> - .virtual = __MMIO_P2V(CT_CA9X4_L2CC),
> - .pfn = __phys_to_pfn(CT_CA9X4_L2CC),
> - .length = SZ_4K,
> - .type = MT_DEVICE,
> + .virtual = V2T_PERIPH,
> + .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
> + .length = SZ_8K,
> + .type = MT_DEVICE,
> },
> };
>
> static void __init ct_ca9x4_map_io(void)
> {
> -#ifdef CONFIG_LOCAL_TIMERS
> - twd_base = MMIO_P2V(A9_MPCORE_TWD);
> -#endif
> iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
> }
>
> static void __init ct_ca9x4_init_irq(void)
> {
> - gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
> - MMIO_P2V(A9_MPCORE_GIC_CPU));
> -}
> -
> -#if 0
> -static void __init ct_ca9x4_timer_init(void)
> -{
> - writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
> - writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
> -
> - sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
> - sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
> - "ct-timer0");
> + gic_init(0, 29, V2T_PERIPH_P2V(A9_MPCORE_GIC_DIST),
> + V2T_PERIPH_P2V(A9_MPCORE_GIC_CPU));
> }
>
> -static struct sys_timer ct_ca9x4_timer = {
> - .init = ct_ca9x4_timer_init,
> -};
> -#endif
> -
> static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
> {
> v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
> @@ -193,6 +162,9 @@ static struct platform_device pmu_device = {
>
> static void __init ct_ca9x4_init_early(void)
> {
> +#ifdef CONFIG_LOCAL_TIMERS
> + twd_base = V2T_PERIPH_P2V(A9_MPCORE_TWD);
> +#endif
> clkdev_add_table(lookups, ARRAY_SIZE(lookups));
> }
>
> @@ -201,7 +173,7 @@ static void __init ct_ca9x4_init(void)
> int i;
>
> #ifdef CONFIG_CACHE_L2X0
> - void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
> + void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
>
> /* set RAM latencies to 1 cycle for this core tile. */
> writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
> @@ -219,7 +191,7 @@ static void __init ct_ca9x4_init(void)
> #ifdef CONFIG_SMP
> static void ct_ca9x4_init_cpu_map(void)
> {
> - int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
> + int i, ncores = scu_get_core_count(V2T_PERIPH_P2V(A9_MPCORE_SCU));
>
> if (ncores > nr_cpu_ids) {
> pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
> @@ -235,7 +207,7 @@ static void ct_ca9x4_init_cpu_map(void)
>
> static void ct_ca9x4_smp_enable(unsigned int max_cpus)
> {
> - scu_enable(MMIO_P2V(A9_MPCORE_SCU));
> + scu_enable(V2T_PERIPH_P2V(A9_MPCORE_SCU));
> }
> #endif
>
> diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
> index a34d3d4..8f962fb 100644
> --- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
> +++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
> @@ -22,14 +22,11 @@
> #define CT_CA9X4_SYSWDT (0x1e007000)
> #define CT_CA9X4_L2CC (0x1e00a000)
>
> -#define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000)
> -#define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020)
> -
> -#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
> -#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
> -#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
> -#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600)
> -#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
> +#define A9_MPCORE_SCU 0x0000
> +#define A9_MPCORE_GIC_CPU 0x0100
> +#define A9_MPCORE_GIT 0x0200
> +#define A9_MPCORE_TWD 0x0600
> +#define A9_MPCORE_GIC_DIST 0x1000
>
> /*
> * Interrupts. Those in {} are for AMBA devices
> diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
> index 0a3a375..b4c498c 100644
> --- a/arch/arm/mach-vexpress/include/mach/motherboard.h
> +++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
> @@ -39,33 +39,30 @@
> #define V2M_CF (V2M_PA_CS7 + 0x0001a000)
> #define V2M_CLCD (V2M_PA_CS7 + 0x0001f000)
>
> -#define V2M_SYS_ID (V2M_SYSREGS + 0x000)
> -#define V2M_SYS_SW (V2M_SYSREGS + 0x004)
> -#define V2M_SYS_LED (V2M_SYSREGS + 0x008)
> -#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024)
> -#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030)
> -#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030)
> -#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034)
> -#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038)
> -#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038)
> -#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c)
> -#define V2M_SYS_MCI (V2M_SYSREGS + 0x048)
> -#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c)
> -#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058)
> -#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c)
> -#define V2M_SYS_MISC (V2M_SYSREGS + 0x060)
> -#define V2M_SYS_DMA (V2M_SYSREGS + 0x064)
> -#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084)
> -#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088)
> -#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
> -#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
> -#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
> -
> -#define V2M_TIMER0 (V2M_TIMER01 + 0x000)
> -#define V2M_TIMER1 (V2M_TIMER01 + 0x020)
> -
> -#define V2M_TIMER2 (V2M_TIMER23 + 0x000)
> -#define V2M_TIMER3 (V2M_TIMER23 + 0x020)
> +/*
> + * Offsets from SYSREGS base
> + */
> +#define V2M_SYS_ID 0x000
> +#define V2M_SYS_SW 0x004
> +#define V2M_SYS_LED 0x008
> +#define V2M_SYS_100HZ 0x024
> +#define V2M_SYS_FLAGS 0x030
> +#define V2M_SYS_FLAGSSET 0x030
> +#define V2M_SYS_FLAGSCLR 0x034
> +#define V2M_SYS_NVFLAGS 0x038
> +#define V2M_SYS_NVFLAGSSET 0x038
> +#define V2M_SYS_NVFLAGSCLR 0x03c
> +#define V2M_SYS_MCI 0x048
> +#define V2M_SYS_FLASH 0x03c
> +#define V2M_SYS_CFGSW 0x058
> +#define V2M_SYS_24MHZ 0x05c
> +#define V2M_SYS_MISC 0x060
> +#define V2M_SYS_DMA 0x064
> +#define V2M_SYS_PROCID0 0x084
> +#define V2M_SYS_PROCID1 0x088
> +#define V2M_SYS_CFGDATA 0x0a0
> +#define V2M_SYS_CFGCTRL 0x0a4
> +#define V2M_SYS_CFGSTAT 0x0a8
>
>
> /*
> @@ -117,6 +114,7 @@
>
> int v2m_cfg_write(u32 devfn, u32 data);
> int v2m_cfg_read(u32 devfn, u32 *data);
> +void v2m_flags_set(u32 data);
>
> /*
> * Core tile IDs
> diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
> index 2b5f7ac..e8be99d 100644
> --- a/arch/arm/mach-vexpress/platsmp.c
> +++ b/arch/arm/mach-vexpress/platsmp.c
> @@ -45,7 +45,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
> * until it receives a soft interrupt, and then the
> * secondary CPU branches to this address.
> */
> - writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
> - writel(BSYM(virt_to_phys(versatile_secondary_startup)),
> - MMIO_P2V(V2M_SYS_FLAGSSET));
> + v2m_flags_set(BSYM(virt_to_phys(versatile_secondary_startup)));
This isn't a new issue, but BSYM() should only be used in assembler
(mostly because gas is too stupid to know whether local symbols are ARM
or Thumb in a systematic way). Here, it's needed because headsmp.S is
missing an ENDPROC directive, so the assembler does not properly mark
the type of that symbol.
Try this (untested):
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index d397a1f..0be2efc 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -28,6 +28,7 @@ ENTRY(versatile_secondary_startup)
pen: ldr r7, [r6]
cmp r7, r0
bne pen
+ENDPROC(versatile_secondary_startup)
/*
* we've been released from the holding pen: secondary_stack
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 2b5f7ac..124ffb1 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -13,8 +13,6 @@
#include <linux/smp.h>
#include <linux/io.h>
-#include <asm/unified.h>
-
#include <mach/motherboard.h>
#define V2M_PA_CS7 0x10000000
@@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* secondary CPU branches to this address.
*/
writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
- writel(BSYM(virt_to_phys(versatile_secondary_startup)),
+ writel(virt_to_phys(versatile_secondary_startup),
MMIO_P2V(V2M_SYS_FLAGSSET));
}
Obviously, this doesn't make a difference unless you build with
CONFIG_THUMB2_KERNEL=y.
> }
> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
> index 1fafc32..ee52b35 100644
> --- a/arch/arm/mach-vexpress/v2m.c
> +++ b/arch/arm/mach-vexpress/v2m.c
> @@ -39,29 +39,41 @@
>
> static struct map_desc v2m_io_desc[] __initdata = {
> {
> - .virtual = __MMIO_P2V(V2M_PA_CS7),
> + .virtual = V2M_PERIPH,
> .pfn = __phys_to_pfn(V2M_PA_CS7),
> .length = SZ_128K,
> .type = MT_DEVICE,
> },
> };
>
> +static void __iomem *v2m_sysreg_base;
> +
> static void __init v2m_timer_init(void)
> {
> - u32 scctrl;
> -
> - /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
> - scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
> - scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
> - scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
> - writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
> -
> - writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
> - writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
> -
> - sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
> - sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
> - "v2m-timer0");
> + void __iomem *sysctl_base;
> + void __iomem *timer01_base;
> +
> + sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
> + WARN_ON(!sysctl_base);
> + if (sysctl_base) {
> + /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
> + u32 scctrl = readl(sysctl_base + SCCTRL);
> + scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
> + scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
> + writel(scctrl, sysctl_base + SCCTRL);
> + }
> +
> + timer01_base = ioremap(V2M_TIMER01, SZ_4K);
> + WARN_ON(!timer01_base);
> + if (timer01_base) {
> + writel(0, timer01_base + TIMER_1_BASE + TIMER_CTRL);
> + writel(0, timer01_base + TIMER_2_BASE + TIMER_CTRL);
> +
> + sp804_clocksource_init(timer01_base + TIMER_2_BASE,
> + "v2m-timer1");
> + sp804_clockevents_init(timer01_base + TIMER_1_BASE,
> + IRQ_V2M_TIMER0, "v2m-timer0");
> + }
> }
>
> static struct sys_timer v2m_timer = {
> @@ -81,14 +93,14 @@ int v2m_cfg_write(u32 devfn, u32 data)
> devfn |= SYS_CFG_START | SYS_CFG_WRITE;
>
> spin_lock(&v2m_cfg_lock);
> - val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
> - writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
> + val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
> + writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
>
> - writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
> - writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
> + writel(data, v2m_sysreg_base + V2M_SYS_CFGDATA);
> + writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
>
> do {
> - val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
> + val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
> } while (val == 0);
> spin_unlock(&v2m_cfg_lock);
>
> @@ -102,22 +114,28 @@ int v2m_cfg_read(u32 devfn, u32 *data)
> devfn |= SYS_CFG_START;
>
> spin_lock(&v2m_cfg_lock);
> - writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
> - writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
> + writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
> + writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
>
> mb();
>
> do {
> cpu_relax();
> - val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
> + val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
> } while (val == 0);
>
> - *data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
> + *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
> spin_unlock(&v2m_cfg_lock);
>
> return !!(val & SYS_CFG_ERR);
> }
>
> +void __init v2m_flags_set(u32 data)
> +{
> + writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
> + writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
> +}
> +
>
> static struct resource v2m_pcie_i2c_resource = {
> .start = V2M_SERIAL_BUS_PCI,
> @@ -203,7 +221,7 @@ static struct platform_device v2m_usb_device = {
>
> static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
> {
> - writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
> + writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
> }
>
> static struct physmap_flash_data v2m_flash_data = {
> @@ -257,7 +275,7 @@ static struct platform_device v2m_cf_device = {
>
> static unsigned int v2m_mmci_status(struct device *dev)
> {
> - return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
> + return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
> }
>
> static struct mmci_platform_data v2m_mmci_data = {
> @@ -370,7 +388,7 @@ static void __init v2m_init_early(void)
> {
> ct_desc->init_early();
> clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
> - versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
> + versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
> }
>
> static void v2m_power_off(void)
> @@ -399,7 +417,8 @@ static void __init v2m_populate_ct_desc(void)
> u32 current_tile_id;
>
> ct_desc = NULL;
> - current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
> + current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
> + & V2M_CT_ID_MASK;
>
> for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
> if (ct_descs[i]->id == current_tile_id)
> @@ -413,6 +432,7 @@ static void __init v2m_populate_ct_desc(void)
> static void __init v2m_map_io(void)
> {
> iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
> + v2m_sysreg_base = V2M_PERIPH_P2V(V2M_SYSREGS);
> v2m_populate_ct_desc();
> ct_desc->map_io();
> }
> --
> 1.6.3.3
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m
[not found] ` <1322060508-11298-3-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
@ 2011-11-25 16:18 ` Dave Martin
2011-11-28 10:54 ` Pawel Moll
0 siblings, 1 reply; 24+ messages in thread
From: Dave Martin @ 2011-11-25 16:18 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wed, Nov 23, 2011 at 03:01:46PM +0000, Pawel Moll wrote:
> This patch provides hooks for DT-based tile machine implementations
> and adds Device Tree description for the motherboard.
>
> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> ---
> Documentation/devicetree/bindings/arm/vexpress | 101 +++++++++++
> arch/arm/boot/dts/vexpress-v2m.dtsi | 191 +++++++++++++++++++++
> arch/arm/mach-vexpress/Kconfig | 6 +
> arch/arm/mach-vexpress/core.h | 10 +
> arch/arm/mach-vexpress/include/mach/motherboard.h | 6 +
> arch/arm/mach-vexpress/v2m.c | 141 ++++++++++++++-
> 6 files changed, 447 insertions(+), 8 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/vexpress
> create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/vexpress b/Documentation/devicetree/bindings/arm/vexpress
> new file mode 100644
> index 0000000..4b2c3bf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/vexpress
> @@ -0,0 +1,101 @@
> +ARM Versatile Express boards family
> +-----------------------------------
> +
> +ARM's Versatile Express platform consists of a motherboard
> +and one or more daughterboards (tiles). The motherboard provides
> +set of peripherals. Processor and RAM "live" on the tiles.
[Since this text is now stable enough to be proofread, I'll list minor
pedantic nits along with the other comments -- they aren't vital to the
meaning though, and the documentation still "works" if they aren't
acted on.]
s/set of/a set of/
> +Both parts of the system should be described in two separate
> +Device Tree source files, with the tile's description including
The motherboard and each core tile should be described by a separate Device Tree source file, with [...]
> +motherboard's file. As the motherboard can be initialized in one
[...] including the motherboard file using a /include directive. [...]
> +of different configurations ("memory maps"), care must be taken
s/of different/of two different/
> +to include the correct one.
> +
> +Required properties in the root node:
> +- compatible value:
> + compatible = "arm,vexpress-<model>";
> + where <model> is the full tile model name (as used in the tiles's
> + Technical Reference Manual), eg:
> + - for Coretile Express A5x2 (V2P-CA5s):
> + compatible = "arm,vexpress-v2p-ca5s";
> + - Coretile Express A9x4 (V2P-CA9):
> + compatible = "arm,vexpress-v2p-ca9";
Should the bindings for the tiles be formally documented here? If this
is the only place they are mentioned, this is the real list and not just
examples, so lose the "eg".
I suspect that we won't see enough platforms getting added to lead to
non-trivial merge conflicts in this file, but if that's a concern we
could split those bindings out.
> +
> +Current Linux implementation requires a "timer" alias pointing
> +at one of the SP804 timer blocks to be used when tile is not using
> +local timer source.
"local timer source" might be confusing terminology.
Is this supposed to encompass sp804 or other timer blocks which may
be present on the coretile, or just the architected timers? Or is
this supposed to identify a fallback timer used by the motherboard
code in case the coretile code doesn't set up its own timer source?
> +
> +Optional properties in the root node:
> +- tile model name (use the same names as in the tile's Technical
> + Reference Manuals, eg. "V2P-CA5s")
> + model = "<model>";
> +- tile's HBI number (unique ARM's board model ID, visible on the
> + PCB's silkscreen) in hexadecimal transcription:
> + arm,hbi = <0xhbi>
> + eg:
> + - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
> + arm,hbi = <0x191>;
> + - Coretile Express A9x4 (V2P-CA9) HBI-0225:
> + arm,hbi = <0x225>;
> +
> +The motherboard description file provides single "motherboard" node
s/provides single/provides a single/
> +using 2 address cells corresponding to the Static Memory Bus used
> +between the motherboard and the tile. First cell defines Chip Select
s/First/The first/
s/Chip Select/the Chip Select/
> +(CS) line number, the second cell address offset within the CS.
> +All interrupts lines between the motherboard and the tile are active
s/interrupts/interrupt/
> +high and are described using single cell.
> +
> +Optional properties of the "motherboard" node:
> +- motherboard's memory map variant:
> + arm,v2m-memory-map = "<name>";
> + where name is one of:
> + - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
> + referred to as "ARM Cortex-A Series memory map":
> + arm,v2m-memory-map = "rs1";
> + When this property is missing, the motherboard is using original
> + memory map (also known as "Legacy memory map") with peripherals
> + on CS7.
It could be helpful to clarify where the original memory map applies:
"This memory map is primarily used by the original CoreTile Express A9x4."
> +
> +Motherboard .dtsi files provide set of phandles to peripherals that
s/provide set/provide a set/
I think strictly speaking, those .dtsi files define labels, not phandles.
A phandle is a numerical identifier for a node (also derivable symbolically
from a label using the &label syntax in the DT source.
> +can be used in the tile's aliases node:
> +- UARTs:
> + mb_serial0, mb_serial1, mb_serial2 and mb_serial3
> +- I2C controllers:
> + mb_i2c_dvi and mb_i2c_pcie
> +- SP804 timers:
> + mb_timer01 and mb_timer23
For the UARTs, it may be worth adding a comment that the numbers
correspond to the labelled physical UARTs on the motherboard.
The I2C and timer names are probably sufficiently obvious, though.
> +
> +The tile description must define "ranges", "interrupt-map-mask" and
> +"interrupt-map" properties to translate the motherboard's address
> +and interrupt space into one used by the tile's processor.
> +
> +Abbreviated example:
> +
> +/dts-v1/;
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + model = "V2P-CA5s";
> + arm,hbi = <0x225>;
> + compatible = "arm,vexpress-v2p-ca5s";
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &mb_serial0;
> + timer = &mb_timer01;
> + };
> +
> + gic: interrupt-controller@2c001000 {
> + compatible = "arm,cortex-a9-gic";
> + };
> +
> + motherboard {
> + /* CS0 is visible at 0x08000000 */
> + ranges = <0 0 0x08000000 0x04000000>;
> + interrupt-map-mask = <0 0 63>;
> + /* Active high IRQ 0 is connected to GIC's SPI0 */
> + interrupt-map = <0 0 0 &gic 0 0 4>;
> + };
> +}
> +
> +/include/ "vexpress-v2m-rs1.dtsi"
> diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
> new file mode 100644
> index 0000000..364e44c
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
> @@ -0,0 +1,191 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * Motherboard Express uATX
> + * V2M-P1
> + *
> + * HBI-0190D
> + *
> + * Original memory map ("Legacy memory map" in the board's
> + * Technical Reference Manual)
> + *
> + * WARNING! The hardware described in this file is independent from the
> + * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
> + * correspondence between the two configurations.
> + *
> + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
> + * CHANGES TO vexpress-v2m-rs1.dtsi!
> + */
> +
> +/ {
> + motherboard {
> + compatible = "simple-bus";
> + #address-cells = <2>; /* SMB chipselect number and offset */
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + flash@0,00000000 {
> + compatible = "arm,vexpress-flash", "cfi-flash";
> + reg = <0 0x00000000 0x04000000>,
> + <1 0x00000000 0x04000000>;
> + bank-width = <4>;
> + };
> +
> + psram@2,00000000 {
> + compatible = "mtd-ram";
> + reg = <2 0x00000000 0x02000000>;
> + bank-width = <4>;
> + };
> +
> + ethernet@3,02000000 {
> + compatible = "smsc,lan9118", "smsc,lan9115";
> + reg = <3 0x02000000 0x10000>;
> + interrupts = <15>;
> + phy-mode = "mii";
> + reg-io-width = <4>;
> + smsc,irq-active-high;
> + smsc,irq-push-pull;
> + };
> +
> + usb@3,03000000 {
> + compatible = "nxp,usb-isp1761";
> + reg = <3 0x03000000 0x20000>;
> + interrupts = <16>;
> + port1-otg;
> + };
> +
> + iofpga@7,00000000 {
> + compatible = "arm,amba-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 7 0 0x20000>;
> +
> + sysreg@00000 {
> + compatible = "arm,vexpress-sysreg";
> + reg = <0x00000 0x1000>;
> + };
> +
> + sysctl@01000 {
> + compatible = "arm,sp810", "arm,primecell";
> + reg = <0x01000 0x1000>;
> + };
> +
> + /* PCI-E I2C bus */
> + mb_i2c_pcie: i2c@02000 {
> + compatible = "arm,versatile-i2c";
> + reg = <0x02000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pcie-switch@60 {
> + compatible = "idt,89hpes32h8";
> + reg = <0x60>;
> + };
> + };
> +
> + aaci@04000 {
> + compatible = "arm,pl041", "arm,primecell";
> + reg = <0x04000 0x1000>;
> + interrupts = <11>;
> + };
> +
> + mmci@05000 {
> + compatible = "arm,pl180", "arm,primecell";
> + reg = <0x05000 0x1000>;
> + interrupts = <9 10>;
> + };
> +
> + kmi@06000 {
> + compatible = "arm,pl050", "arm,primecell";
> + reg = <0x06000 0x1000>;
> + interrupts = <12>;
> + };
> +
> + kmi@07000 {
> + compatible = "arm,pl050", "arm,primecell";
> + reg = <0x07000 0x1000>;
> + interrupts = <13>;
> + };
> +
> + mb_serial0: uart@09000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x09000 0x1000>;
> + interrupts = <5>;
> + };
> +
> + mb_serial1: uart@0a000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0a000 0x1000>;
> + interrupts = <6>;
> + };
> +
> + mb_serial2: uart@0b000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0b000 0x1000>;
> + interrupts = <7>;
> + };
> +
> + mb_serial3: uart@0c000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0c000 0x1000>;
> + interrupts = <8>;
> + };
> +
> + wdt@0f000 {
> + compatible = "arm,sp805", "arm,primecell";
> + reg = <0x0f000 0x1000>;
> + interrupts = <0>;
> + };
> +
> + mb_timer01: timer@11000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x11000 0x1000>;
> + interrupts = <2>;
> + };
> +
> + mb_timer23: timer@12000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x12000 0x1000>;
> + };
> +
> + /* DVI I2C bus */
> + mb_i2c_dvi: i2c@16000 {
> + compatible = "arm,versatile-i2c";
> + reg = <0x16000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dvi-transmitter@39 {
> + compatible = "sil,sii9022-tpi", "sil,sii9022";
> + reg = <0x39>;
> + };
> +
> + dvi-transmitter@60 {
> + compatible = "sil,sii9022-cpi", "sil,sii9022";
> + reg = <0x60>;
> + };
> + };
> +
> + rtc@17000 {
> + compatible = "arm,pl031", "arm,primecell";
> + reg = <0x17000 0x1000>;
> + interrupts = <4>;
> + };
> +
> + compact-flash@1a000 {
> + compatible = "ata-generic";
> + reg = <0x1a000 0x100
> + 0x1a100 0xf00>;
> + reg-shift = <2>;
> + };
> +
> + clcd@1f000 {
> + compatible = "arm,pl111", "arm,primecell";
> + reg = <0x1f000 0x1000>;
> + interrupts = <14>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 9311484..6a6fa22 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -9,4 +9,10 @@ config ARCH_VEXPRESS_CA9X4
> select ARM_ERRATA_751472
> select ARM_ERRATA_753970
>
> +config ARCH_VEXPRESS_DT
> + bool
> + select OF
> + help
> + VE platform *requiring* Flattened Device Tree to boot.
> +
> endmenu
> diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
> index d3dd491..21cc48b 100644
> --- a/arch/arm/mach-vexpress/core.h
> +++ b/arch/arm/mach-vexpress/core.h
> @@ -22,3 +22,13 @@ struct amba_device name##_device = { \
> /* Tile's peripherals static mappings should start here */
> #define V2T_PERIPH 0xf8200000
> #define V2T_PERIPH_P2V(offset) ((void __iomem *)(V2T_PERIPH | (offset)))
> +
> +#if defined(CONFIG_ARCH_VEXPRESS_DT)
> +
> +extern struct sys_timer v2m_timer;
> +
> +void __init v2m_dt_map_io(void);
> +void __init v2m_dt_init_early(void);
> +struct of_dev_auxdata * __init v2m_dt_get_auxdata(void);
> +
> +#endif
> diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
> index b4c498c..31a9289 100644
> --- a/arch/arm/mach-vexpress/include/mach/motherboard.h
> +++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
> @@ -117,6 +117,12 @@ int v2m_cfg_read(u32 devfn, u32 *data);
> void v2m_flags_set(u32 data);
>
> /*
> + * Miscellaneous
> + */
> +#define SYS_MISC_MASTERSITE (1 << 14)
> +#define SYS_PROCIDx_HBI_MASK 0xfff
> +
> +/*
> * Core tile IDs
> */
> #define V2M_CT_ID_CA9 0x0c000191
> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
> index ee52b35..fd7ee1f 100644
> --- a/arch/arm/mach-vexpress/v2m.c
> +++ b/arch/arm/mach-vexpress/v2m.c
> @@ -6,6 +6,10 @@
> #include <linux/amba/mmci.h>
> #include <linux/io.h>
> #include <linux/init.h>
> +#include <linux/of_address.h>
> +#include <linux/of_fdt.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/ata_platform.h>
> #include <linux/smsc911x.h>
> @@ -17,6 +21,7 @@
>
> #include <asm/mach-types.h>
> #include <asm/sizes.h>
> +#include <asm/system.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> #include <asm/mach/time.h>
> @@ -50,10 +55,34 @@ static void __iomem *v2m_sysreg_base;
>
> static void __init v2m_timer_init(void)
> {
> - void __iomem *sysctl_base;
> - void __iomem *timer01_base;
> + void __iomem *sysctl_base = NULL;
> + void __iomem *timer01_base = NULL;
> + unsigned int timer01_irq = NO_IRQ;
> +
> + if (of_have_populated_dt()) {
> +#if defined(CONFIG_ARCH_VEXPRESS_DT)
> + int err;
> + const char *path;
> + struct device_node *node;
> +
> + node = of_find_compatible_node(NULL, NULL, "arm,sp810");
> + if (node)
> + sysctl_base = of_iomap(node, 0);
> +
> + err = of_property_read_string(of_aliases, "timer", &path);
> + if (!err)
> + node = of_find_node_by_path(path);
> + if (node) {
> + timer01_base = of_iomap(node, 0);
> + timer01_irq = irq_of_parse_and_map(node, 0);
> + }
> +#endif
> + } else {
> + sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
> + timer01_base = ioremap(V2M_TIMER01, SZ_4K);
> + timer01_irq = IRQ_V2M_TIMER0;
> + }
Do we even have of_have_populated_dt() in a non-DT kernel?
Maybe change this to
#if defined(CONFIG_ARCH_VEXPRESS_DT)
if (of_have_populated_dt()) {
/* ... */
} else
#endif
/* follow on from previous else */
{
/* ... */
}
...or if that feels a little unclear, maybe do this:
#if defined(CONFIG_ARCH_VEXPRESS_DT)
if (of_have_populated_dt()) {
/* ... */
} else {
#else
{
#endif
/* ... */
}
>
> - sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
> WARN_ON(!sysctl_base);
> if (sysctl_base) {
> /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
> @@ -63,20 +92,20 @@ static void __init v2m_timer_init(void)
> writel(scctrl, sysctl_base + SCCTRL);
> }
>
> - timer01_base = ioremap(V2M_TIMER01, SZ_4K);
> - WARN_ON(!timer01_base);
> - if (timer01_base) {
> + WARN_ON(!timer01_base || timer01_irq != NO_IRQ);
Is that supposed to be !timer01_base || timer01_irq == NO_IRQ ?
If so, is might be better to write
WARN_ON(!(expr));
if (expr) {
...
so that the conditions are clear inverses.
> + if (timer01_base && timer01_irq != NO_IRQ) {
> writel(0, timer01_base + TIMER_1_BASE + TIMER_CTRL);
> writel(0, timer01_base + TIMER_2_BASE + TIMER_CTRL);
>
> sp804_clocksource_init(timer01_base + TIMER_2_BASE,
> "v2m-timer1");
> sp804_clockevents_init(timer01_base + TIMER_1_BASE,
> - IRQ_V2M_TIMER0, "v2m-timer0");
> + timer01_irq, "v2m-timer0");
> }
> }
>
> -static struct sys_timer v2m_timer = {
> +/* Used also by DT-powered core tiles */
> +struct sys_timer v2m_timer = {
> .init = v2m_timer_init,
> };
>
> @@ -470,3 +499,99 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
> .timer = &v2m_timer,
> .init_machine = v2m_init,
> MACHINE_END
It would be useful to have a comment somewhere indicating that the
DT_MACHINE_START() entries live in the corresponding ct-*.c files for
DT-enabled coretiles.
Not essential, though ... most people do know how to use grep.
> +
> +
> +#if defined(CONFIG_ARCH_VEXPRESS_DT)
> +
> +void __init v2m_dt_map_io(void)
> +{
> + iotable_init(v2m_rs1_io_desc, ARRAY_SIZE(v2m_rs1_io_desc));
> +}
> +
> +static struct clk_lookup v2m_dt_lookups[] = {
> + { /* AMBA bus clock */
> + .con_id = "apb_pclk",
> + .clk = &dummy_apb_pclk,
> + }, { /* SP804 timers */
> + .dev_id = "sp804",
> + .con_id = "v2m-timer0",
> + .clk = &v2m_sp804_clk,
> + }, { /* SP804 timers */
> + .dev_id = "sp804",
> + .con_id = "v2m-timer1",
> + .clk = &v2m_sp804_clk,
> + }, { /* PL180 MMCI */
> + .dev_id = "mb:mmci", /* 10005000.mmci */
> + .clk = &osc2_clk,
> + }, { /* PL050 KMI0 */
> + .dev_id = "10006000.kmi",
> + .clk = &osc2_clk,
> + }, { /* PL050 KMI1 */
> + .dev_id = "10007000.kmi",
> + .clk = &osc2_clk,
> + }, { /* PL011 UART0 */
> + .dev_id = "10009000.uart",
> + .clk = &osc2_clk,
> + }, { /* PL011 UART1 */
> + .dev_id = "1000a000.uart",
> + .clk = &osc2_clk,
> + }, { /* PL011 UART2 */
> + .dev_id = "1000b000.uart",
> + .clk = &osc2_clk,
> + }, { /* PL011 UART3 */
> + .dev_id = "1000c000.uart",
> + .clk = &osc2_clk,
> + }, { /* SP805 WDT */
> + .dev_id = "1000f000.wdt",
> + .clk = &v2m_ref_clk,
> + }, { /* PL111 CLCD */
> + .dev_id = "1001f000.clcd",
> + .clk = &osc1_clk,
> + },
> +};
> +
> +void __init v2m_dt_init_early(void)
> +{
> + struct device_node *node;
> + const __be32 *reg;
> + u32 dt_hbi;
> +
> + node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
> + reg = of_get_property(node, "reg", NULL);
> + if (WARN_ON(!reg))
> + return;
> +
> + v2m_sysreg_base = V2M_PERIPH_P2V(be32_to_cpup(reg));
> +
> + /* Confirm board type against DT property, if available */
> + if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
> + u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
> + u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
> + V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
> + u32 hbi = id & SYS_PROCIDx_HBI_MASK;
> +
> + if (WARN_ON(dt_hbi != hbi))
> + pr_warning("vexpress: DT HBI (%x) is not matching "
> + "hardware (%x)!\n", dt_hbi, hbi);
> + }
> +
> + clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
> + versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
> +
> + pm_power_off = v2m_power_off;
> + arm_pm_restart = v2m_restart;
> +}
> +
> +static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
> + OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
> + &v2m_flash_data),
> + OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
> + {}
> +};
> +
> +struct of_dev_auxdata * __init v2m_dt_get_auxdata(void)
> +{
> + return v2m_dt_auxdata_lookup;
> +}
> +
> +#endif
> --
> 1.6.3.3
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V
2011-11-25 16:15 ` Dave Martin
@ 2011-11-28 10:40 ` Pawel Moll
[not found] ` <20111125161500.GD2098-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
1 sibling, 0 replies; 24+ messages in thread
From: Pawel Moll @ 2011-11-28 10:40 UTC (permalink / raw)
To: Dave Martin
Cc: devicetree-discuss@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
On Fri, 2011-11-25 at 16:15 +0000, Dave Martin wrote:
> Try this (untested):
>
> diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
> index d397a1f..0be2efc 100644
> --- a/arch/arm/plat-versatile/headsmp.S
> +++ b/arch/arm/plat-versatile/headsmp.S
> @@ -28,6 +28,7 @@ ENTRY(versatile_secondary_startup)
> pen: ldr r7, [r6]
> cmp r7, r0
> bne pen
> +ENDPROC(versatile_secondary_startup)
>
> /*
> * we've been released from the holding pen: secondary_stack
> diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
> index 2b5f7ac..124ffb1 100644
> --- a/arch/arm/mach-vexpress/platsmp.c
> +++ b/arch/arm/mach-vexpress/platsmp.c
> @@ -13,8 +13,6 @@
> #include <linux/smp.h>
> #include <linux/io.h>
>
> -#include <asm/unified.h>
> -
> #include <mach/motherboard.h>
> #define V2M_PA_CS7 0x10000000
>
> @@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
> * secondary CPU branches to this address.
> */
> writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
> - writel(BSYM(virt_to_phys(versatile_secondary_startup)),
> + writel(virt_to_phys(versatile_secondary_startup),
> MMIO_P2V(V2M_SYS_FLAGSSET));
> }
Sure thing, will try that.
Cheers!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V
[not found] ` <20111125161500.GD2098-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
@ 2011-11-28 10:44 ` Russell King - ARM Linux
[not found] ` <20111128104416.GD9581-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Russell King - ARM Linux @ 2011-11-28 10:44 UTC (permalink / raw)
To: Dave Martin
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Pawel Moll
On Fri, Nov 25, 2011 at 04:15:00PM +0000, Dave Martin wrote:
> diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
> index d397a1f..0be2efc 100644
> --- a/arch/arm/plat-versatile/headsmp.S
> +++ b/arch/arm/plat-versatile/headsmp.S
> @@ -28,6 +28,7 @@ ENTRY(versatile_secondary_startup)
> pen: ldr r7, [r6]
> cmp r7, r0
> bne pen
> +ENDPROC(versatile_secondary_startup)
This is wrong. You're telling the assembler that this function ends here.
It doesn't, it continues on. Put the ENDPROC at the end of the function.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V
[not found] ` <20111128104416.GD9581-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
@ 2011-11-28 10:53 ` Dave Martin
0 siblings, 0 replies; 24+ messages in thread
From: Dave Martin @ 2011-11-28 10:53 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Pawel Moll
On Mon, Nov 28, 2011 at 10:44:16AM +0000, Russell King - ARM Linux wrote:
> On Fri, Nov 25, 2011 at 04:15:00PM +0000, Dave Martin wrote:
> > diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
> > index d397a1f..0be2efc 100644
> > --- a/arch/arm/plat-versatile/headsmp.S
> > +++ b/arch/arm/plat-versatile/headsmp.S
> > @@ -28,6 +28,7 @@ ENTRY(versatile_secondary_startup)
> > pen: ldr r7, [r6]
> > cmp r7, r0
> > bne pen
> > +ENDPROC(versatile_secondary_startup)
>
> This is wrong. You're telling the assembler that this function ends here.
> It doesn't, it continues on. Put the ENDPROC at the end of the function.
Dunno what I was thinking of there -- agreed, the ENDPROC() should move
to the end of the file.
(I'm assuming that literals should be included in the size of the
relevant function symbol here -- that's the convention the compiler
follows.)
Cheers
---Dave
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m
2011-11-25 16:18 ` Dave Martin
@ 2011-11-28 10:54 ` Pawel Moll
[not found] ` <1322477662.3164.30.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Pawel Moll @ 2011-11-28 10:54 UTC (permalink / raw)
To: Dave Martin
Cc: devicetree-discuss@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
On Fri, 2011-11-25 at 16:18 +0000, Dave Martin wrote:
> [Since this text is now stable enough to be proofread, I'll list minor
> pedantic nits along with the other comments -- they aren't vital to the
> meaning though, and the documentation still "works" if they aren't
> acted on.]
[snip]
Most appreciated! I'll "process" all your suggestions, thanks!
> > @@ -50,10 +55,34 @@ static void __iomem *v2m_sysreg_base;
> >
> > static void __init v2m_timer_init(void)
> > {
> > - void __iomem *sysctl_base;
> > - void __iomem *timer01_base;
> > + void __iomem *sysctl_base = NULL;
> > + void __iomem *timer01_base = NULL;
> > + unsigned int timer01_irq = NO_IRQ;
> > +
> > + if (of_have_populated_dt()) {
> > +#if defined(CONFIG_ARCH_VEXPRESS_DT)
> > + int err;
> > + const char *path;
> > + struct device_node *node;
> > +
> > + node = of_find_compatible_node(NULL, NULL, "arm,sp810");
> > + if (node)
> > + sysctl_base = of_iomap(node, 0);
> > +
> > + err = of_property_read_string(of_aliases, "timer", &path);
> > + if (!err)
> > + node = of_find_node_by_path(path);
> > + if (node) {
> > + timer01_base = of_iomap(node, 0);
> > + timer01_irq = irq_of_parse_and_map(node, 0);
> > + }
> > +#endif
> > + } else {
> > + sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
> > + timer01_base = ioremap(V2M_TIMER01, SZ_4K);
> > + timer01_irq = IRQ_V2M_TIMER0;
> > + }
>
> Do we even have of_have_populated_dt() in a non-DT kernel?
>
> Maybe change this to
>
> #if defined(CONFIG_ARCH_VEXPRESS_DT)
> if (of_have_populated_dt()) {
> /* ... */
> } else
> #endif
> /* follow on from previous else */
> {
> /* ... */
> }
>
> ...or if that feels a little unclear, maybe do this:
>
> #if defined(CONFIG_ARCH_VEXPRESS_DT)
> if (of_have_populated_dt()) {
> /* ... */
> } else {
> #else
> {
> #endif
> /* ... */
> }
of_have_populated_dt() is safe, see "include/linux/of.h":
#ifdef CONFIG_OF
static inline bool of_have_populated_dt(void)
{
return allnodes != NULL;
}
#else /* CONFIG_OF */
static inline bool of_have_populated_dt(void)
{
return false;
}
#endif /* CONFIG_OF */
> > @@ -63,20 +92,20 @@ static void __init v2m_timer_init(void)
> > writel(scctrl, sysctl_base + SCCTRL);
> > }
> >
> > - timer01_base = ioremap(V2M_TIMER01, SZ_4K);
> > - WARN_ON(!timer01_base);
> > - if (timer01_base) {
> > + WARN_ON(!timer01_base || timer01_irq != NO_IRQ);
>
> Is that supposed to be !timer01_base || timer01_irq == NO_IRQ ?
Yes, I spotted and fixed this in the mean time.
> If so, is might be better to write
>
> WARN_ON(!(expr));
> if (expr) {
> ...
>
> so that the conditions are clear inverses.
Good point, will do.
> > @@ -470,3 +499,99 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
> > .timer = &v2m_timer,
> > .init_machine = v2m_init,
> > MACHINE_END
>
> It would be useful to have a comment somewhere indicating that the
> DT_MACHINE_START() entries live in the corresponding ct-*.c files for
> DT-enabled coretiles.
>
> Not essential, though ... most people do know how to use grep.
Where exactly would you see that comment?
Thanks for the review!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m
[not found] ` <1322477662.3164.30.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
@ 2011-11-28 11:38 ` Dave Martin
0 siblings, 0 replies; 24+ messages in thread
From: Dave Martin @ 2011-11-28 11:38 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
On Mon, Nov 28, 2011 at 10:54:22AM +0000, Pawel Moll wrote:
> On Fri, 2011-11-25 at 16:18 +0000, Dave Martin wrote:
> > [Since this text is now stable enough to be proofread, I'll list minor
> > pedantic nits along with the other comments -- they aren't vital to the
> > meaning though, and the documentation still "works" if they aren't
> > acted on.]
>
> [snip]
>
> Most appreciated! I'll "process" all your suggestions, thanks!
>
> > > @@ -50,10 +55,34 @@ static void __iomem *v2m_sysreg_base;
> > >
> > > static void __init v2m_timer_init(void)
> > > {
> > > - void __iomem *sysctl_base;
> > > - void __iomem *timer01_base;
> > > + void __iomem *sysctl_base = NULL;
> > > + void __iomem *timer01_base = NULL;
> > > + unsigned int timer01_irq = NO_IRQ;
> > > +
> > > + if (of_have_populated_dt()) {
> > > +#if defined(CONFIG_ARCH_VEXPRESS_DT)
> > > + int err;
> > > + const char *path;
> > > + struct device_node *node;
> > > +
> > > + node = of_find_compatible_node(NULL, NULL, "arm,sp810");
> > > + if (node)
> > > + sysctl_base = of_iomap(node, 0);
> > > +
> > > + err = of_property_read_string(of_aliases, "timer", &path);
> > > + if (!err)
> > > + node = of_find_node_by_path(path);
> > > + if (node) {
> > > + timer01_base = of_iomap(node, 0);
> > > + timer01_irq = irq_of_parse_and_map(node, 0);
> > > + }
> > > +#endif
> > > + } else {
> > > + sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
> > > + timer01_base = ioremap(V2M_TIMER01, SZ_4K);
> > > + timer01_irq = IRQ_V2M_TIMER0;
> > > + }
> >
> > Do we even have of_have_populated_dt() in a non-DT kernel?
> >
> > Maybe change this to
> >
> > #if defined(CONFIG_ARCH_VEXPRESS_DT)
> > if (of_have_populated_dt()) {
> > /* ... */
> > } else
> > #endif
> > /* follow on from previous else */
> > {
> > /* ... */
> > }
> >
> > ...or if that feels a little unclear, maybe do this:
> >
> > #if defined(CONFIG_ARCH_VEXPRESS_DT)
> > if (of_have_populated_dt()) {
> > /* ... */
> > } else {
> > #else
> > {
> > #endif
> > /* ... */
> > }
>
> of_have_populated_dt() is safe, see "include/linux/of.h":
You're right, but this code is still making assumptions about the
relationship between a build-time option (defined(
CONFIG_ARCH_VEXPRESS_DT)) and a run-time condition
(of_have_populated_dt()). The relationship between the two is far from
transparent.
The effective condition we want is if(of_have_populated_dt()
&& defined(CONFIG_ARCH_VEXPRESS_DT)). This is implemented in my
versions, but in your case the code can compile as
if(of_have_populated_dt()) { } else {
sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
...
}
I don't believe we should be writing code which can compile as
if(condition) { } else { do something useful; } unless there are
scenarios under which executing that empty block (and skipping the else)
would be the correct thing to do. In this code, that's never the
right thing.
I don't know how likely this is to be an issue, but we should avoid
putting too many booby-traps in the code for future maintainers.
Since you have the #ifdef anyway, I don't see a strong argument against
moving it into the correct place.
> #ifdef CONFIG_OF
> static inline bool of_have_populated_dt(void)
> {
> return allnodes != NULL;
> }
> #else /* CONFIG_OF */
> static inline bool of_have_populated_dt(void)
> {
> return false;
> }
> #endif /* CONFIG_OF */
>
> > > @@ -63,20 +92,20 @@ static void __init v2m_timer_init(void)
> > > writel(scctrl, sysctl_base + SCCTRL);
> > > }
> > >
> > > - timer01_base = ioremap(V2M_TIMER01, SZ_4K);
> > > - WARN_ON(!timer01_base);
> > > - if (timer01_base) {
> > > + WARN_ON(!timer01_base || timer01_irq != NO_IRQ);
> >
> > Is that supposed to be !timer01_base || timer01_irq == NO_IRQ ?
>
> Yes, I spotted and fixed this in the mean time.
>
> > If so, is might be better to write
> >
> > WARN_ON(!(expr));
> > if (expr) {
> > ...
> >
> > so that the conditions are clear inverses.
>
> Good point, will do.
>
> > > @@ -470,3 +499,99 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
> > > .timer = &v2m_timer,
> > > .init_machine = v2m_init,
> > > MACHINE_END
> >
> > It would be useful to have a comment somewhere indicating that the
> > DT_MACHINE_START() entries live in the corresponding ct-*.c files for
> > DT-enabled coretiles.
> >
> > Not essential, though ... most people do know how to use grep.
>
> Where exactly would you see that comment?
Next to the MACHINE_START() probably makes sense. That was the point at
which I wondered where the DT equivalent(s) were.
Cheers
---Dave
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/4] Versatile Express DT support
[not found] ` <1322060508-11298-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
@ 2011-11-28 14:25 ` Rob Herring
[not found] ` <4ED399C8.9080908-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-28 15:20 ` Pawel Moll
0 siblings, 2 replies; 24+ messages in thread
From: Rob Herring @ 2011-11-28 14:25 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 11/23/2011 09:01 AM, Pawel Moll wrote:
> Hello again,
>
> This version of the series (hopefully) addresses all the suggestions
> made by Dave, Rob and Russell.
>
> The compatible values are specific for the tiles now and the memory
> map variant is defined as a custom property in the motherboard node.
>
> Tested on V2P-CA9 coretile both with ATAGs and DT and V2P-CA5s with DT.
>
> All comments, as always, welcomed!
>
> Pawel
>
>
>
> Pawel Moll (4):
> ARM: vexpress: Get rid of MMIO_P2V
> ARM: vexpress: Add DT support in v2m
> ARM: vexpress: Initial RS1 memory map support
> ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
>
> Documentation/devicetree/bindings/arm/vexpress | 101 ++++++++
> arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 192 +++++++++++++++
> arch/arm/boot/dts/vexpress-v2m.dtsi | 191 +++++++++++++++
> arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132 ++++++++++
> arch/arm/boot/dts/vexpress-v2p-ca9.dts | 146 +++++++++++
> arch/arm/include/asm/hardware/arm_timer.h | 5 +
> arch/arm/mach-vexpress/Kconfig | 35 +++
> arch/arm/mach-vexpress/Makefile | 1 +
> arch/arm/mach-vexpress/Makefile.boot | 6 +
> arch/arm/mach-vexpress/core.h | 21 ++-
> arch/arm/mach-vexpress/ct-ca9x4.c | 52 +---
> arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
> arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++-
> arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++--
> arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +-
> arch/arm/mach-vexpress/platsmp.c | 4 +-
> arch/arm/mach-vexpress/v2m.c | 265 ++++++++++++++++++---
> arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115 +++++++++
> 18 files changed, 1272 insertions(+), 115 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/vexpress
> create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
> create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
> create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c
Other than Dave's comments, looks good. For the series:
Acked-by: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
There are a number of compatible strings for various peripherals defined
without documentation, but you're not really using them so I think it's
fine for now. BTW, I believe Dave said he was going to document some of
the primecell peripherals. :)
Rob
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/4] Versatile Express DT support
[not found] ` <4ED399C8.9080908-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2011-11-28 14:42 ` Dave Martin
2011-11-28 14:57 ` Dave Martin
1 sibling, 0 replies; 24+ messages in thread
From: Dave Martin @ 2011-11-28 14:42 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Pawel Moll
On Mon, Nov 28, 2011 at 08:25:12AM -0600, Rob Herring wrote:
> On 11/23/2011 09:01 AM, Pawel Moll wrote:
> > Hello again,
> >
> > This version of the series (hopefully) addresses all the suggestions
> > made by Dave, Rob and Russell.
> >
> > The compatible values are specific for the tiles now and the memory
> > map variant is defined as a custom property in the motherboard node.
> >
> > Tested on V2P-CA9 coretile both with ATAGs and DT and V2P-CA5s with DT.
> >
> > All comments, as always, welcomed!
> >
> > Pawel
> >
> >
> >
> > Pawel Moll (4):
> > ARM: vexpress: Get rid of MMIO_P2V
> > ARM: vexpress: Add DT support in v2m
> > ARM: vexpress: Initial RS1 memory map support
> > ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
> >
> > Documentation/devicetree/bindings/arm/vexpress | 101 ++++++++
> > arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 192 +++++++++++++++
> > arch/arm/boot/dts/vexpress-v2m.dtsi | 191 +++++++++++++++
> > arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132 ++++++++++
> > arch/arm/boot/dts/vexpress-v2p-ca9.dts | 146 +++++++++++
> > arch/arm/include/asm/hardware/arm_timer.h | 5 +
> > arch/arm/mach-vexpress/Kconfig | 35 +++
> > arch/arm/mach-vexpress/Makefile | 1 +
> > arch/arm/mach-vexpress/Makefile.boot | 6 +
> > arch/arm/mach-vexpress/core.h | 21 ++-
> > arch/arm/mach-vexpress/ct-ca9x4.c | 52 +---
> > arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
> > arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++-
> > arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++--
> > arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +-
> > arch/arm/mach-vexpress/platsmp.c | 4 +-
> > arch/arm/mach-vexpress/v2m.c | 265 ++++++++++++++++++---
> > arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115 +++++++++
> > 18 files changed, 1272 insertions(+), 115 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/arm/vexpress
> > create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> > create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
> > create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> > create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
> > create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c
>
> Other than Dave's comments, looks good. For the series:
>
> Acked-by: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
>
> There are a number of compatible strings for various peripherals defined
> without documentation, but you're not really using them so I think it's
> fine for now. BTW, I believe Dave said he was going to document some of
> the primecell peripherals. :)
I hadn't forgotten ... I was going to follow up on those shortly :)
Cheers
---Dave
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/4] Versatile Express DT support
[not found] ` <4ED399C8.9080908-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-28 14:42 ` Dave Martin
@ 2011-11-28 14:57 ` Dave Martin
2011-11-28 15:09 ` Pawel Moll
1 sibling, 1 reply; 24+ messages in thread
From: Dave Martin @ 2011-11-28 14:57 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Pawel Moll
On Mon, Nov 28, 2011 at 08:25:12AM -0600, Rob Herring wrote:
> On 11/23/2011 09:01 AM, Pawel Moll wrote:
> > Hello again,
> >
> > This version of the series (hopefully) addresses all the suggestions
> > made by Dave, Rob and Russell.
> >
> > The compatible values are specific for the tiles now and the memory
> > map variant is defined as a custom property in the motherboard node.
> >
> > Tested on V2P-CA9 coretile both with ATAGs and DT and V2P-CA5s with DT.
> >
> > All comments, as always, welcomed!
> >
> > Pawel
> >
> >
> >
> > Pawel Moll (4):
> > ARM: vexpress: Get rid of MMIO_P2V
> > ARM: vexpress: Add DT support in v2m
> > ARM: vexpress: Initial RS1 memory map support
> > ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
> >
> > Documentation/devicetree/bindings/arm/vexpress | 101 ++++++++
> > arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 192 +++++++++++++++
> > arch/arm/boot/dts/vexpress-v2m.dtsi | 191 +++++++++++++++
> > arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132 ++++++++++
> > arch/arm/boot/dts/vexpress-v2p-ca9.dts | 146 +++++++++++
> > arch/arm/include/asm/hardware/arm_timer.h | 5 +
> > arch/arm/mach-vexpress/Kconfig | 35 +++
> > arch/arm/mach-vexpress/Makefile | 1 +
> > arch/arm/mach-vexpress/Makefile.boot | 6 +
> > arch/arm/mach-vexpress/core.h | 21 ++-
> > arch/arm/mach-vexpress/ct-ca9x4.c | 52 +---
> > arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
> > arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++-
> > arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++--
> > arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +-
> > arch/arm/mach-vexpress/platsmp.c | 4 +-
> > arch/arm/mach-vexpress/v2m.c | 265 ++++++++++++++++++---
> > arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115 +++++++++
> > 18 files changed, 1272 insertions(+), 115 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/arm/vexpress
> > create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> > create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
> > create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> > create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
> > create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c
>
> Other than Dave's comments, looks good. For the series:
>
> Acked-by: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
>
> There are a number of compatible strings for various peripherals defined
> without documentation, but you're not really using them so I think it's
> fine for now. BTW, I believe Dave said he was going to document some of
> the primecell peripherals. :)
Oh, btw, git am reports a few whitespace errors on the last full post of
the series (v2).
Can you shove the series through checkpatch.pl and/or git am and fix any
minor issues, now that the series is relatively stable?
Thanks
---Dave
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/4] Versatile Express DT support
2011-11-28 14:57 ` Dave Martin
@ 2011-11-28 15:09 ` Pawel Moll
[not found] ` <1322492947.3164.44.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Pawel Moll @ 2011-11-28 15:09 UTC (permalink / raw)
To: Dave Martin
Cc: devicetree-discuss@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
On Mon, 2011-11-28 at 14:57 +0000, Dave Martin wrote:
> Oh, btw, git am reports a few whitespace errors on the last full post of
> the series (v2).
>
> Can you shove the series through checkpatch.pl and/or git am and fix any
> minor issues, now that the series is relatively stable?
I did, actually:
8<--------------------------------------------------------------------
$ scripts/checkpatch.pl 0001-ARM-vexpress-Get-rid-of-MMIO_P2V.patch
total: 0 errors, 0 warnings, 363 lines checked
0001-ARM-vexpress-Get-rid-of-MMIO_P2V.patch has no obvious style problems and is ready for submission.
$ scripts/checkpatch.pl 0002-ARM-vexpress-Add-DT-support-in-v2m.patch
total: 0 errors, 0 warnings, 505 lines checked
0002-ARM-vexpress-Add-DT-support-in-v2m.patch has no obvious style problems and is ready for submission.
$ scripts/checkpatch.pl 0003-ARM-vexpress-Initial-RS1-memory-map-support.patch
WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
#308: FILE: arch/arm/mach-vexpress/include/mach/uncompress.h:25:
+#define AMBA_PERIPH_ID0(base) (*(volatile unsigned char *)((base) + 0xfe0))
total: 0 errors, 1 warnings, 368 lines checked
0003-ARM-vexpress-Initial-RS1-memory-map-support.patch has style problems, please review.
If any of these errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.
$ scripts/checkpatch.pl 0004-ARM-vexpress-DT-based-support-for-CoreTiles-Express-.patch
total: 0 errors, 0 warnings, 424 lines checked
0004-ARM-vexpress-DT-based-support-for-CoreTiles-Express-.patch has no obvious style problems and is ready for submission.
8<--------------------------------------------------------------------
In the past I noticed that same - sometimes git am is complaining when
chechpatch is clean. I never was determined to figure out why, though...
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/4] Versatile Express DT support
[not found] ` <1322492947.3164.44.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
@ 2011-11-28 15:14 ` Dave Martin
0 siblings, 0 replies; 24+ messages in thread
From: Dave Martin @ 2011-11-28 15:14 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
On Mon, Nov 28, 2011 at 03:09:07PM +0000, Pawel Moll wrote:
> On Mon, 2011-11-28 at 14:57 +0000, Dave Martin wrote:
> > Oh, btw, git am reports a few whitespace errors on the last full post of
> > the series (v2).
> >
> > Can you shove the series through checkpatch.pl and/or git am and fix any
> > minor issues, now that the series is relatively stable?
>
> I did, actually:
>
> 8<--------------------------------------------------------------------
> $ scripts/checkpatch.pl 0001-ARM-vexpress-Get-rid-of-MMIO_P2V.patch
> total: 0 errors, 0 warnings, 363 lines checked
>
> 0001-ARM-vexpress-Get-rid-of-MMIO_P2V.patch has no obvious style problems and is ready for submission.
> $ scripts/checkpatch.pl 0002-ARM-vexpress-Add-DT-support-in-v2m.patch
> total: 0 errors, 0 warnings, 505 lines checked
>
> 0002-ARM-vexpress-Add-DT-support-in-v2m.patch has no obvious style problems and is ready for submission.
> $ scripts/checkpatch.pl 0003-ARM-vexpress-Initial-RS1-memory-map-support.patch
> WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
> #308: FILE: arch/arm/mach-vexpress/include/mach/uncompress.h:25:
> +#define AMBA_PERIPH_ID0(base) (*(volatile unsigned char *)((base) + 0xfe0))
>
> total: 0 errors, 1 warnings, 368 lines checked
>
> 0003-ARM-vexpress-Initial-RS1-memory-map-support.patch has style problems, please review.
>
> If any of these errors are false positives, please report
> them to the maintainer, see CHECKPATCH in MAINTAINERS.
> $ scripts/checkpatch.pl 0004-ARM-vexpress-DT-based-support-for-CoreTiles-Express-.patch
> total: 0 errors, 0 warnings, 424 lines checked
>
> 0004-ARM-vexpress-DT-based-support-for-CoreTiles-Express-.patch has no obvious style problems and is ready for submission.
> 8<--------------------------------------------------------------------
>
>
> In the past I noticed that same - sometimes git am is complaining when
> chechpatch is clean. I never was determined to figure out why, though...
Maybe those whitespace issues are only being reported by git am.
We can still fix them though, no?
Cheers
---Dave
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/4] Versatile Express DT support
2011-11-28 14:25 ` [PATCH v2 0/4] Versatile Express DT support Rob Herring
[not found] ` <4ED399C8.9080908-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2011-11-28 15:20 ` Pawel Moll
[not found] ` <1322493617.3164.56.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
1 sibling, 1 reply; 24+ messages in thread
From: Pawel Moll @ 2011-11-28 15:20 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-discuss@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
On Mon, 2011-11-28 at 14:25 +0000, Rob Herring wrote:
> Other than Dave's comments, looks good. For the series:
>
> Acked-by: Rob Herring <rob.herring@calxeda.com>
Thanks!
> There are a number of compatible strings for various peripherals defined
> without documentation, but you're not really using them so I think it's
> fine for now. BTW, I believe Dave said he was going to document some of
> the primecell peripherals. :)
Yep, we agreed with Dave that the ones I'll take care of soon are MMCI
(PL180) and the VE sysregs, the rest is his :-)
On that subject - some time ago I sent a patch adding "sil" vendor
string, as this one the only non-documented one I used:
http://article.gmane.org/gmane.linux.drivers.devicetree/9362/
Cheers!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/4] Versatile Express DT support
[not found] ` <1322493617.3164.56.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
@ 2011-11-28 15:39 ` Rob Herring
2011-11-28 16:02 ` Pawel Moll
0 siblings, 1 reply; 24+ messages in thread
From: Rob Herring @ 2011-11-28 15:39 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
On 11/28/2011 09:20 AM, Pawel Moll wrote:
> On Mon, 2011-11-28 at 14:25 +0000, Rob Herring wrote:
>> Other than Dave's comments, looks good. For the series:
>>
>> Acked-by: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
>
> Thanks!
>
>> There are a number of compatible strings for various peripherals defined
>> without documentation, but you're not really using them so I think it's
>> fine for now. BTW, I believe Dave said he was going to document some of
>> the primecell peripherals. :)
>
> Yep, we agreed with Dave that the ones I'll take care of soon are MMCI
> (PL180) and the VE sysregs, the rest is his :-)
>
> On that subject - some time ago I sent a patch adding "sil" vendor
> string, as this one the only non-documented one I used:
>
> http://article.gmane.org/gmane.linux.drivers.devicetree/9362/
Okay. I'll apply.
But that's just a vendor. There's still binding docs needed for the
actual sil9022 device and some others.
Rob
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/4] Versatile Express DT support
2011-11-28 15:39 ` Rob Herring
@ 2011-11-28 16:02 ` Pawel Moll
0 siblings, 0 replies; 24+ messages in thread
From: Pawel Moll @ 2011-11-28 16:02 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-discuss@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
On Mon, 2011-11-28 at 15:39 +0000, Rob Herring wrote:
> Okay. I'll apply.
>
> But that's just a vendor. There's still binding docs needed for the
> actual sil9022 device and some others.
I think the sil one is the only undocumented device we use now, except
for the primecells that Dave and I will take care of?
I will also cover the sii9022, if only I get clearance from our legals
(the datasheet we got is under NDA) to write a driver for it (the device
is quite complex, so I wouldn't like to define bindings without testing
them first).
Cheers!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 4/4] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
[not found] ` <1322060508-11298-5-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
@ 2011-11-28 16:29 ` Dave Martin
2011-11-28 17:00 ` Pawel Moll
0 siblings, 1 reply; 24+ messages in thread
From: Dave Martin @ 2011-11-28 16:29 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wed, Nov 23, 2011 at 03:01:48PM +0000, Pawel Moll wrote:
> This patch adds Device Trees for ARM Ltd. CoreTile Express A5x2
> and CoreTile Express A9x4 used with V2M motherboard and an initial
> implementation of the DT machine support (this code is separate
> from the current core tile code).
>
> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132 ++++++++++++++++++++++++++++
> arch/arm/boot/dts/vexpress-v2p-ca9.dts | 146 +++++++++++++++++++++++++++++++
> arch/arm/mach-vexpress/Kconfig | 21 +++++
> arch/arm/mach-vexpress/Makefile | 1 +
> arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115 ++++++++++++++++++++++++
> 5 files changed, 415 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
> create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c
>
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> new file mode 100644
> index 0000000..84e05cd
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> @@ -0,0 +1,132 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * CoreTile Express A5x2
> + * Cortex-A5 MPCore (V2P-CA5s)
> + *
> + * HBI-0225B
> + */
> +
> +/dts-v1/;
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + model = "V2P-CA5s";
> + arm,hbi = <0x225>;
> + compatible = "arm,vexpress-v2p-ca5s";
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &mb_serial0;
> + serial1 = &mb_serial1;
> + serial2 = &mb_serial2;
> + serial3 = &mb_serial3;
> + i2c0 = &mb_i2c_dvi;
> + i2c1 = &mb_i2c_pcie;
> + timer = &mb_timer01;
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x40000000>;
> + };
> +
> + hdlcd@2a110000 {
> + compatible = "arm,hdlcd";
> + reg = <0x2a110000 0x1000>;
> + interrupts = <0 85 4>;
> + };
> +
> + memory-controller@2a150000 {
> + compatible = "arm,pl341", "arm,primecell";
> + reg = <0x2a150000 0x1000>;
> + };
> +
> + memory-controller@2a190000 {
> + compatible = "arm,pl354", "arm,primecell";
> + reg = <0x2a190000 0x1000>;
> + interrupts = <0 86 4>,
> + <0 87 4>;
> + };
> +
> + gic: interrupt-controller@2c001000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x2c001000 0x1000>,
> + <0x2c000100 0x100>;
> + };
> +
> + L2: cache-controller@2c0f0000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x2c0f0000 0x1000>;
> + interrupts = <0 84 4>;
> + cache-level = <2>;
> + arm,data-latency = <0>;
> + arm,tag-latency = <0>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a9-pmu";
> + interrupts = <0 68 4>,
> + <0 69 4>;
> + };
> +
> + motherboard {
> + ranges = <0 0 0x08000000 0x04000000>,
> + <1 0 0x14000000 0x04000000>,
> + <2 0 0x18000000 0x04000000>,
> + <3 0 0x1c000000 0x04000000>,
> + <4 0 0x0c000000 0x04000000>,
> + <5 0 0x10000000 0x04000000>;
> +
> + interrupt-map-mask = <0 0 63>;
> + interrupt-map = <0 0 0 &gic 0 0 4>,
> + <0 0 1 &gic 0 1 4>,
> + <0 0 2 &gic 0 2 4>,
> + <0 0 3 &gic 0 3 4>,
> + <0 0 4 &gic 0 4 4>,
> + <0 0 5 &gic 0 5 4>,
> + <0 0 6 &gic 0 6 4>,
> + <0 0 7 &gic 0 7 4>,
> + <0 0 8 &gic 0 8 4>,
> + <0 0 9 &gic 0 9 4>,
> + <0 0 10 &gic 0 10 4>,
> + <0 0 11 &gic 0 11 4>,
> + <0 0 12 &gic 0 12 4>,
> + <0 0 13 &gic 0 13 4>,
> + <0 0 14 &gic 0 14 4>,
> + <0 0 15 &gic 0 15 4>,
> + <0 0 16 &gic 0 16 4>,
> + <0 0 17 &gic 0 17 4>,
> + <0 0 18 &gic 0 18 4>,
> + <0 0 19 &gic 0 19 4>,
> + <0 0 20 &gic 0 20 4>,
> + <0 0 21 &gic 0 21 4>,
> + <0 0 22 &gic 0 22 4>,
> + <0 0 23 &gic 0 23 4>,
> + <0 0 24 &gic 0 24 4>,
> + <0 0 25 &gic 0 25 4>,
> + <0 0 26 &gic 0 26 4>,
> + <0 0 27 &gic 0 27 4>,
> + <0 0 28 &gic 0 28 4>,
> + <0 0 29 &gic 0 29 4>,
> + <0 0 30 &gic 0 30 4>,
> + <0 0 31 &gic 0 31 4>,
> + <0 0 32 &gic 0 32 4>,
> + <0 0 33 &gic 0 33 4>,
> + <0 0 34 &gic 0 34 4>,
> + <0 0 35 &gic 0 35 4>,
> + <0 0 36 &gic 0 36 4>,
> + <0 0 37 &gic 0 37 4>,
> + <0 0 38 &gic 0 38 4>,
> + <0 0 39 &gic 0 39 4>,
> + <0 0 40 &gic 0 40 4>,
> + <0 0 41 &gic 0 41 4>,
> + <0 0 42 &gic 0 42 4>;
> + };
> +};
> +
> +/include/ "vexpress-v2m-rs1.dtsi"
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> new file mode 100644
> index 0000000..ae6b70c
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> @@ -0,0 +1,146 @@
> +/*
> + * ARM Ltd. Versatile Express
> + *
> + * CoreTile Express A9x4
> + * Cortex-A9 MPCore (V2P-CA9)
> + *
> + * HBI-0191B
> + */
> +
> +/dts-v1/;
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + model = "V2P-CA9";
> + arm,hbi = <0x191>;
> + compatible = "arm,vexpress-v2p-ca9";
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &mb_serial0;
> + serial1 = &mb_serial1;
> + serial2 = &mb_serial2;
> + serial3 = &mb_serial3;
> + i2c0 = &mb_i2c_dvi;
> + i2c1 = &mb_i2c_pcie;
> + timer = &mb_timer01;
> + };
> +
> + memory@60000000 {
> + device_type = "memory";
> + reg = <0x60000000 0x40000000>;
> + };
> +
> + clcd@10020000 {
> + compatible = "arm,pl111", "arm,primecell";
> + reg = <0x10020000 0x1000>;
> + interrupts = <0 44 4>;
> + };
> +
> + memory-controller@100e0000 {
> + compatible = "arm,pl341", "arm,primecell";
> + reg = <0x100e0000 0x1000>;
> + };
> +
> + memory-controller@100e1000 {
> + compatible = "arm,pl354", "arm,primecell";
> + reg = <0x100e1000 0x1000>;
> + interrupts = <0 45 4>,
> + <0 46 4>;
> + };
> +
> + timer@100e4000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x100e4000 0x1000>;
> + interrupts = <0 48 4>,
> + <0 49 4>;
> + };
> +
> + watchdog@100e5000 {
> + compatible = "arm,sp805", "arm,primecell";
> + reg = <0x100e5000 0x1000>;
> + interrupts = <0 51 4>;
> + };
> +
> + gic: interrupt-controller@1e001000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x1e001000 0x1000>,
> + <0x1e000100 0x100>;
> + };
> +
> + L2: cache-controller@1e00a000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x1e00a000 0x1000>;
> + interrupts = <0 43 4>;
> + cache-level = <2>;
> + arm,data-latency = <0>;
> + arm,tag-latency = <0>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a9-pmu";
> + interrupts = <0 60 4>,
> + <0 61 4>,
> + <0 62 4>,
> + <0 63 4>;
> + };
> +
> + motherboard {
> + ranges = <0 0 0x40000000 0x04000000>,
> + <1 0 0x44000000 0x04000000>,
> + <2 0 0x48000000 0x04000000>,
> + <3 0 0x4c000000 0x04000000>,
> + <7 0 0x10000000 0x00020000>;
> +
> + interrupt-map-mask = <0 0 63>;
> + interrupt-map = <0 0 0 &gic 0 0 4>,
> + <0 0 1 &gic 0 1 4>,
> + <0 0 2 &gic 0 2 4>,
> + <0 0 3 &gic 0 3 4>,
> + <0 0 4 &gic 0 4 4>,
> + <0 0 5 &gic 0 5 4>,
> + <0 0 6 &gic 0 6 4>,
> + <0 0 7 &gic 0 7 4>,
> + <0 0 8 &gic 0 8 4>,
> + <0 0 9 &gic 0 9 4>,
> + <0 0 10 &gic 0 10 4>,
> + <0 0 11 &gic 0 11 4>,
> + <0 0 12 &gic 0 12 4>,
> + <0 0 13 &gic 0 13 4>,
> + <0 0 14 &gic 0 14 4>,
> + <0 0 15 &gic 0 15 4>,
> + <0 0 16 &gic 0 16 4>,
> + <0 0 17 &gic 0 17 4>,
> + <0 0 18 &gic 0 18 4>,
> + <0 0 19 &gic 0 19 4>,
> + <0 0 20 &gic 0 20 4>,
> + <0 0 21 &gic 0 21 4>,
> + <0 0 22 &gic 0 22 4>,
> + <0 0 23 &gic 0 23 4>,
> + <0 0 24 &gic 0 24 4>,
> + <0 0 25 &gic 0 25 4>,
> + <0 0 26 &gic 0 26 4>,
> + <0 0 27 &gic 0 27 4>,
> + <0 0 28 &gic 0 28 4>,
> + <0 0 29 &gic 0 29 4>,
> + <0 0 30 &gic 0 30 4>,
> + <0 0 31 &gic 0 31 4>,
> + <0 0 32 &gic 0 32 4>,
> + <0 0 33 &gic 0 33 4>,
> + <0 0 34 &gic 0 34 4>,
> + <0 0 35 &gic 0 35 4>,
> + <0 0 36 &gic 0 36 4>,
> + <0 0 37 &gic 0 37 4>,
> + <0 0 38 &gic 0 38 4>,
> + <0 0 39 &gic 0 39 4>,
> + <0 0 40 &gic 0 40 4>,
> + <0 0 41 &gic 0 41 4>,
> + <0 0 42 &gic 0 42 4>;
> + };
> +};
> +
> +/include/ "vexpress-v2m.dtsi"
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 2180888..0f31125 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -23,4 +23,25 @@ config ARCH_VEXPRESS_RS1
> RS1 VE memory map (i.a. motherboard peripherals at
> 0x1c000000, RAM at 0x80000000).
>
> +config ARCH_VEXPRESS_V2P_CA5S_CA9
> + bool "CoreTile Express A5x2 and A9x4 based platform support"
> + select ARCH_VEXPRESS_RS1
> + select ARCH_VEXPRESS_DT
Shouldn't we depend on CPU_V7, ARM_GIC and CACHE_PL310 here? I get a lot of
moaning from Kconfig about unmet dependencies. I think the coretiles do have
a CPU etc. on them...
> + select ARM_ERRATA_720789
> + select ARM_ERRATA_751472
The workarounds for these errata both erroneously depend on CONFIG_SMP; however,
I don't think that's a bug in these patches -- selecting those options here
feels correct.
I'll follow up with some separate patches to fix these.
> + select ARM_ERRATA_753970
Will has a patch, now in Russell's fixes branch, which renames this to
PL310_ERRATA_753970 for compatibility with other people's patches.
This erratum workaround depends on CACHE_PL310, but since the PL310 is
a property of the CoreTile which must be configured in, that dependency
seems reasonable.
Cheers
---Dave
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 4/4] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
2011-11-28 16:29 ` Dave Martin
@ 2011-11-28 17:00 ` Pawel Moll
[not found] ` <1322499602.3164.73.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
0 siblings, 1 reply; 24+ messages in thread
From: Pawel Moll @ 2011-11-28 17:00 UTC (permalink / raw)
To: Dave Martin
Cc: devicetree-discuss@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
On Mon, 2011-11-28 at 16:29 +0000, Dave Martin wrote:
> > +config ARCH_VEXPRESS_V2P_CA5S_CA9
> > + bool "CoreTile Express A5x2 and A9x4 based platform support"
> > + select ARCH_VEXPRESS_RS1
> > + select ARCH_VEXPRESS_DT
>
> Shouldn't we depend on CPU_V7, ARM_GIC and CACHE_PL310 here? I get a lot of
> moaning from Kconfig about unmet dependencies. I think the coretiles do have
> a CPU etc. on them...
CPU_V7 and ARM_GIC - definitely, thanks for spotting that.
CACHE_PL310 - I don't think so, as it's just a special case of
CACHE_L2X0, which is optional. The tile works fine with the L2 cache
disabled.
> > + select ARM_ERRATA_720789
> > + select ARM_ERRATA_751472
>
> The workarounds for these errata both erroneously depend on CONFIG_SMP; however,
> I don't think that's a bug in these patches -- selecting those options here
> feels correct.
Yes, I've just mirrored what the ARCH_VEXPRESS_CA9X4 selects.
> > + select ARM_ERRATA_753970
>
> Will has a patch, now in Russell's fixes branch, which renames this to
> PL310_ERRATA_753970 for compatibility with other people's patches.
> This erratum workaround depends on CACHE_PL310, but since the PL310 is
> a property of the CoreTile which must be configured in, that dependency
> seems reasonable.
As the PL310 is optional I think I'll just do:
select PL310_ERRATA_753970 if CACHE_PL310
Cheers!
Pawel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 4/4] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
[not found] ` <1322499602.3164.73.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
@ 2011-11-28 17:08 ` Dave Martin
0 siblings, 0 replies; 24+ messages in thread
From: Dave Martin @ 2011-11-28 17:08 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
On Mon, Nov 28, 2011 at 05:00:02PM +0000, Pawel Moll wrote:
> On Mon, 2011-11-28 at 16:29 +0000, Dave Martin wrote:
> > > +config ARCH_VEXPRESS_V2P_CA5S_CA9
> > > + bool "CoreTile Express A5x2 and A9x4 based platform support"
> > > + select ARCH_VEXPRESS_RS1
> > > + select ARCH_VEXPRESS_DT
> >
> > Shouldn't we depend on CPU_V7, ARM_GIC and CACHE_PL310 here? I get a lot of
> > moaning from Kconfig about unmet dependencies. I think the coretiles do have
> > a CPU etc. on them...
>
> CPU_V7 and ARM_GIC - definitely, thanks for spotting that.
>
> CACHE_PL310 - I don't think so, as it's just a special case of
> CACHE_L2X0, which is optional. The tile works fine with the L2 cache
> disabled.
>
> > > + select ARM_ERRATA_720789
> > > + select ARM_ERRATA_751472
> >
> > The workarounds for these errata both erroneously depend on CONFIG_SMP; however,
> > I don't think that's a bug in these patches -- selecting those options here
> > feels correct.
>
> Yes, I've just mirrored what the ARCH_VEXPRESS_CA9X4 selects.
>
> > > + select ARM_ERRATA_753970
> >
> > Will has a patch, now in Russell's fixes branch, which renames this to
> > PL310_ERRATA_753970 for compatibility with other people's patches.
> > This erratum workaround depends on CACHE_PL310, but since the PL310 is
> > a property of the CoreTile which must be configured in, that dependency
> > seems reasonable.
>
> As the PL310 is optional I think I'll just do:
>
> select PL310_ERRATA_753970 if CACHE_PL310
OK, I think that's appropriate in this case.
Cheers
---Dave
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2011-11-28 17:08 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-11-23 15:01 [PATCH v2 0/4] Versatile Express DT support Pawel Moll
2011-11-23 15:01 ` [PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V Pawel Moll
[not found] ` <1322060508-11298-2-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-11-25 16:15 ` Dave Martin
2011-11-28 10:40 ` Pawel Moll
[not found] ` <20111125161500.GD2098-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2011-11-28 10:44 ` Russell King - ARM Linux
[not found] ` <20111128104416.GD9581-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2011-11-28 10:53 ` Dave Martin
2011-11-23 15:01 ` [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m Pawel Moll
2011-11-23 16:10 ` Pawel Moll
[not found] ` <1322060508-11298-3-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-11-25 16:18 ` Dave Martin
2011-11-28 10:54 ` Pawel Moll
[not found] ` <1322477662.3164.30.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2011-11-28 11:38 ` Dave Martin
2011-11-23 15:01 ` [PATCH v2 3/4] ARM: vexpress: Initial RS1 memory map support Pawel Moll
2011-11-23 15:01 ` [PATCH v2 4/4] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4 Pawel Moll
[not found] ` <1322060508-11298-5-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-11-28 16:29 ` Dave Martin
2011-11-28 17:00 ` Pawel Moll
[not found] ` <1322499602.3164.73.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2011-11-28 17:08 ` Dave Martin
[not found] ` <1322060508-11298-1-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-11-28 14:25 ` [PATCH v2 0/4] Versatile Express DT support Rob Herring
[not found] ` <4ED399C8.9080908-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-28 14:42 ` Dave Martin
2011-11-28 14:57 ` Dave Martin
2011-11-28 15:09 ` Pawel Moll
[not found] ` <1322492947.3164.44.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2011-11-28 15:14 ` Dave Martin
2011-11-28 15:20 ` Pawel Moll
[not found] ` <1322493617.3164.56.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2011-11-28 15:39 ` Rob Herring
2011-11-28 16:02 ` Pawel Moll
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