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* [PATCH v2 01/20] fdt: Add function to locate an array in the device tree
       [not found] ` <1326490535-3461-1-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
@ 2012-01-13 21:35   ` Simon Glass
  2012-01-13 21:35   ` [PATCH v2 17/20] fdt: tegra: Add EMC node to " Simon Glass
  2012-01-13 21:35   ` [PATCH v2 19/20] tegra: fdt: Add EMC data for Tegra2 Seaboard Simon Glass
  2 siblings, 0 replies; 4+ messages in thread
From: Simon Glass @ 2012-01-13 21:35 UTC (permalink / raw)
  To: U-Boot Mailing List; +Cc: Devicetree Discuss, Tom Warren, Jerry Van Baren

fdtdec_locate_array() locates an integer array but does not copy it. This
saves the caller having to allocated wasted space.

Access to array elements should be through the fdt32_to_cpu() macro.

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v2:
- Add new fdtdec_locate_array() function

 include/fdtdec.h |   19 +++++++++++++++++++
 lib/fdtdec.c     |   11 +++++++++++
 2 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 82264d4..42744f9 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -251,6 +251,25 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
 		u32 *array, int count);
 
 /**
+ * Look up a property in a node and return a pointer to its contents as a
+ * unsigned int array of given length. The property must have at least enough
+ * data for the array ('count' cells). It may have more, but this will be
+ * ignored. The data is not copied.
+ *
+ * Note that you must access elements of the array with fdt32_to_cpu(),
+ * since the elements will be big endian even on a little endian machine.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param count		number of array elements
+ * @return pointer to array if found, or NULL if the property is not
+ *		found or there is not enough data
+ */
+const u32 *fdtdec_locate_array(const void *blob, int node,
+			       const char *prop_name, int count);
+
+/**
  * Look up a boolean property in a node and return it.
  *
  * A boolean properly is true if present in the device tree and false if not
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 3330edf..f1af878 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -341,6 +341,17 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
 	return err;
 }
 
+const u32 *fdtdec_locate_array(const void *blob, int node,
+			       const char *prop_name, int count)
+{
+	const u32 *cell;
+	int err;
+
+	cell = get_prop_check_min_len(blob, node, prop_name,
+				      sizeof(u32) * count, &err);
+	return err ? NULL : cell;
+}
+
 int fdtdec_get_bool(const void *blob, int node, const char *prop_name)
 {
 	const s32 *cell;
-- 
1.7.7.3

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH v2 17/20] fdt: tegra: Add EMC node to device tree
       [not found] ` <1326490535-3461-1-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
  2012-01-13 21:35   ` [PATCH v2 01/20] fdt: Add function to locate an array in the device tree Simon Glass
@ 2012-01-13 21:35   ` Simon Glass
  2012-01-13 21:35   ` [PATCH v2 19/20] tegra: fdt: Add EMC data for Tegra2 Seaboard Simon Glass
  2 siblings, 0 replies; 4+ messages in thread
From: Simon Glass @ 2012-01-13 21:35 UTC (permalink / raw)
  To: U-Boot Mailing List
  Cc: Albert ARIBAUD, Devicetree Discuss, Jerry Van Baren, Tom Warren

Add a definition of the memory controller node according to the bindings
here:

http://patchwork.ozlabs.org/patch/132928/

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---

 arch/arm/dts/tegra20.dtsi |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 963cf27..c009f16 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -203,5 +203,12 @@
 		clocks = <&periph_clk 59>;	// PERIPH_ID_USB3
 	};
 
+	emc@7000f400 {
+		#address-cells = < 1 >;
+		#size-cells = < 0 >;
+		compatible = "nvidia,tegra20-emc";
+		reg = <0x7000f400 0x200>;
+	};
+
 };
 
-- 
1.7.7.3

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH v2 19/20] tegra: fdt: Add EMC data for Tegra2 Seaboard
       [not found] ` <1326490535-3461-1-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
  2012-01-13 21:35   ` [PATCH v2 01/20] fdt: Add function to locate an array in the device tree Simon Glass
  2012-01-13 21:35   ` [PATCH v2 17/20] fdt: tegra: Add EMC node to " Simon Glass
@ 2012-01-13 21:35   ` Simon Glass
  2012-01-13 21:51     ` Simon Glass
  2 siblings, 1 reply; 4+ messages in thread
From: Simon Glass @ 2012-01-13 21:35 UTC (permalink / raw)
  To: U-Boot Mailing List
  Cc: Albert ARIBAUD, Devicetree Discuss, Jerry Van Baren, Tom Warren

This adds timings for T20 and T25 Seaboards, using the bindings found here:

http://patchwork.ozlabs.org/patch/132928/

We supply both full speed options for normal running, and half speed options
for testing / development.

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---

 board/nvidia/dts/tegra2-seaboard.dts |   73 ++++++++++++++++++++++++++++++++++
 1 files changed, 73 insertions(+), 0 deletions(-)

diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts
index d2cc428..b114f5f 100644
--- a/board/nvidia/dts/tegra2-seaboard.dts
+++ b/board/nvidia/dts/tegra2-seaboard.dts
@@ -54,4 +54,77 @@
 		status = "disabled";
 	};
 
+	emc@7000f400 {
+		emc-table@166500 {
+			reg = <166500>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 166500 >;
+			nvidia,emc-registers = < 0x0000000a 0x00000021
+				0x00000008 0x00000003 0x00000004 0x00000004
+				0x00000002 0x0000000c 0x00000003 0x00000003
+				0x00000002 0x00000001 0x00000004 0x00000005
+				0x00000004 0x00000009 0x0000000d 0x000004df
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000003 0x00000001 0x0000000a 0x000000c8
+				0x00000003 0x00000006 0x00000004 0x0000000f
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0xa04004ae
+				0x007fd010 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@333000 {
+			reg = <333000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 333000 >;
+			nvidia,emc-registers = < 0x00000014 0x00000041
+				0x0000000f 0x00000005 0x00000004 0x00000005
+				0x00000003 0x0000000c 0x00000005 0x00000005
+				0x00000003 0x00000001 0x00000004 0x00000005
+				0x00000004 0x00000009 0x0000000d 0x000009ff
+				0x00000000 0x00000003 0x00000003 0x00000005
+				0x00000005 0x00000001 0x0000000f 0x000000c8
+				0x00000003 0x0000000c 0x00000006 0x0000000f
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0xe034048b
+				0x007e8010 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
+
+		emc-table@190000 {
+			reg = < 190000 >;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 190000 >;
+			nvidia,emc-registers = < 0x0000000c 0x00000026
+				0x00000009 0x00000003 0x00000004 0x00000004
+				0x00000002 0x0000000c 0x00000003 0x00000003
+				0x00000002 0x00000001 0x00000004 0x00000005
+				0x00000004 0x00000009 0x0000000d 0x0000059f
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000003 0x00000001 0x0000000b 0x000000c8
+				0x00000003 0x00000007 0x00000004 0x0000000f
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0xa06204ae
+				0x007dc010 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@380000 {
+			reg = < 380000 >;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 380000 >;
+			nvidia,emc-registers = < 0x00000017 0x0000004b
+				0x00000012 0x00000006 0x00000004 0x00000005
+				0x00000003 0x0000000c 0x00000006 0x00000006
+				0x00000003 0x00000001 0x00000004 0x00000005
+				0x00000004 0x00000009 0x0000000d 0x00000b5f
+				0x00000000 0x00000003 0x00000003 0x00000006
+				0x00000006 0x00000001 0x00000011 0x000000c8
+				0x00000003 0x0000000e 0x00000007 0x0000000f
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0xe044048b
+				0x007d8010 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;		emc-table@190000 {
+		};
+	};
+};
+
 };
-- 
1.7.7.3

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH v2 19/20] tegra: fdt: Add EMC data for Tegra2 Seaboard
  2012-01-13 21:35   ` [PATCH v2 19/20] tegra: fdt: Add EMC data for Tegra2 Seaboard Simon Glass
@ 2012-01-13 21:51     ` Simon Glass
  0 siblings, 0 replies; 4+ messages in thread
From: Simon Glass @ 2012-01-13 21:51 UTC (permalink / raw)
  To: U-Boot Mailing List; +Cc: Devicetree Discuss, Jerry Van Baren, Tom Warren

On Fri, Jan 13, 2012 at 1:35 PM, Simon Glass <sjg@chromium.org> wrote:
> This adds timings for T20 and T25 Seaboards, using the bindings found here:
>
> http://patchwork.ozlabs.org/patch/132928/
>
> We supply both full speed options for normal running, and half speed options
> for testing / development.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  board/nvidia/dts/tegra2-seaboard.dts |   73 ++++++++++++++++++++++++++++++++++
>  1 files changed, 73 insertions(+), 0 deletions(-)
>
> diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts
> index d2cc428..b114f5f 100644
> --- a/board/nvidia/dts/tegra2-seaboard.dts
> +++ b/board/nvidia/dts/tegra2-seaboard.dts
> @@ -54,4 +54,77 @@
>                status = "disabled";
>        };
>
> +       emc@7000f400 {
> +               emc-table@166500 {
> +                       reg = <166500>;
> +                       compatible = "nvidia,tegra20-emc-table";
> +                       clock-frequency = < 166500 >;
> +                       nvidia,emc-registers = < 0x0000000a 0x00000021
> +                               0x00000008 0x00000003 0x00000004 0x00000004
> +                               0x00000002 0x0000000c 0x00000003 0x00000003
> +                               0x00000002 0x00000001 0x00000004 0x00000005
> +                               0x00000004 0x00000009 0x0000000d 0x000004df
> +                               0x00000000 0x00000003 0x00000003 0x00000003
> +                               0x00000003 0x00000001 0x0000000a 0x000000c8
> +                               0x00000003 0x00000006 0x00000004 0x0000000f
> +                               0x00000002 0x00000000 0x00000000 0x00000002
> +                               0x00000000 0x00000000 0x00000083 0xa04004ae
> +                               0x007fd010 0x00000000 0x00000000 0x00000000
> +                               0x00000000 0x00000000 0x00000000 0x00000000 >;
> +               };
> +               emc-table@333000 {
> +                       reg = <333000>;
> +                       compatible = "nvidia,tegra20-emc-table";
> +                       clock-frequency = < 333000 >;
> +                       nvidia,emc-registers = < 0x00000014 0x00000041
> +                               0x0000000f 0x00000005 0x00000004 0x00000005
> +                               0x00000003 0x0000000c 0x00000005 0x00000005
> +                               0x00000003 0x00000001 0x00000004 0x00000005
> +                               0x00000004 0x00000009 0x0000000d 0x000009ff
> +                               0x00000000 0x00000003 0x00000003 0x00000005
> +                               0x00000005 0x00000001 0x0000000f 0x000000c8
> +                               0x00000003 0x0000000c 0x00000006 0x0000000f
> +                               0x00000002 0x00000000 0x00000000 0x00000002
> +                               0x00000000 0x00000000 0x00000083 0xe034048b
> +                               0x007e8010 0x00000000 0x00000000 0x00000000
> +                               0x00000000 0x00000000 0x00000000 0x00000000>;
> +               };
> +
> +               emc-table@190000 {
> +                       reg = < 190000 >;
> +                       compatible = "nvidia,tegra20-emc-table";
> +                       clock-frequency = < 190000 >;
> +                       nvidia,emc-registers = < 0x0000000c 0x00000026
> +                               0x00000009 0x00000003 0x00000004 0x00000004
> +                               0x00000002 0x0000000c 0x00000003 0x00000003
> +                               0x00000002 0x00000001 0x00000004 0x00000005
> +                               0x00000004 0x00000009 0x0000000d 0x0000059f
> +                               0x00000000 0x00000003 0x00000003 0x00000003
> +                               0x00000003 0x00000001 0x0000000b 0x000000c8
> +                               0x00000003 0x00000007 0x00000004 0x0000000f
> +                               0x00000002 0x00000000 0x00000000 0x00000002
> +                               0x00000000 0x00000000 0x00000083 0xa06204ae
> +                               0x007dc010 0x00000000 0x00000000 0x00000000
> +                               0x00000000 0x00000000 0x00000000 0x00000000 >;
> +               };
> +               emc-table@380000 {
> +                       reg = < 380000 >;
> +                       compatible = "nvidia,tegra20-emc-table";
> +                       clock-frequency = < 380000 >;
> +                       nvidia,emc-registers = < 0x00000017 0x0000004b
> +                               0x00000012 0x00000006 0x00000004 0x00000005
> +                               0x00000003 0x0000000c 0x00000006 0x00000006
> +                               0x00000003 0x00000001 0x00000004 0x00000005
> +                               0x00000004 0x00000009 0x0000000d 0x00000b5f
> +                               0x00000000 0x00000003 0x00000003 0x00000006
> +                               0x00000006 0x00000001 0x00000011 0x000000c8
> +                               0x00000003 0x0000000e 0x00000007 0x0000000f
> +                               0x00000002 0x00000000 0x00000000 0x00000002
> +                               0x00000000 0x00000000 0x00000083 0xe044048b
> +                               0x007d8010 0x00000000 0x00000000 0x00000000
> +                               0x00000000 0x00000000 0x00000000 0x00000000 >;          emc-table@190000 {

Oh dear. I will fix this next revision...

> +               };
> +       };
> +};
> +
>  };
> --
> 1.7.7.3
>

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2012-01-13 21:51 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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     [not found] <1326490535-3461-1-git-send-email-sjg@chromium.org>
     [not found] ` <1326490535-3461-1-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2012-01-13 21:35   ` [PATCH v2 01/20] fdt: Add function to locate an array in the device tree Simon Glass
2012-01-13 21:35   ` [PATCH v2 17/20] fdt: tegra: Add EMC node to " Simon Glass
2012-01-13 21:35   ` [PATCH v2 19/20] tegra: fdt: Add EMC data for Tegra2 Seaboard Simon Glass
2012-01-13 21:51     ` Simon Glass

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