[PATCH 0/6] AT91 more DT bindings

[PATCH 0/6] AT91 more DT bindings

[Jean-Christophe PLAGNIOL-VILLARD]

HI,

	The following patch series add the bindings for:
	 - PMC
	 - SDRAM/DDR Controller
	 - Reset Controller
	 - Shutdown Controller

The following changes since commit c5ec01650adb1976f928177cd7e71afcb82026c5:

  ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5 (2012-03-02 00:46:37 +0800)

are available in the git repository at:
  git://github.com/at91linux/linux-at91.git ..BRANCH.NOT.VERIFIED..

Jean-Christophe PLAGNIOL-VILLARD (6):
      ARM: at91/dt: add specific DT soc init
      ARM: at91: add pmc DT support
      ARM: at91: always enable sam9 restart
      ARM: at91: add RSTC (Reset Controller) dt support
      ARM: at91: add ram controller DT support
      ARM: at91: add Shutdown Controller (SHDWC) DT support

 .../devicetree/bindings/arm/atmel-at91.txt         |   60 ++++++++
 .../devicetree/bindings/arm/atmel-pmc.txt          |   11 ++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |   20 +++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |   21 +++
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |   11 ++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   20 +++
 arch/arm/boot/dts/at91sam9x5cm.dtsi                |   11 ++
 arch/arm/boot/dts/usb_a9g20.dts                    |   11 ++
 arch/arm/mach-at91/Kconfig                         |   10 +-
 arch/arm/mach-at91/at91sam9x5.c                    |    7 -
 arch/arm/mach-at91/board-dt.c                      |    8 +-
 arch/arm/mach-at91/clock.c                         |   54 ++++++-
 arch/arm/mach-at91/generic.h                       |    2 +
 arch/arm/mach-at91/include/mach/at91_shdwc.h       |    4 +-
 arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 -
 arch/arm/mach-at91/setup.c                         |  158 ++++++++++++++++++++
 16 files changed, 380 insertions(+), 33 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt

Best Regards,
J.

[PATCH 1/6] ARM: at91/dt: add specific DT soc init

[Jean-Christophe PLAGNIOL-VILLARD]

This will allow to have static Device mapping and DT probe mapping for the
System Controller.

Temporary keep the call to ioremap_registers() until we have the binding
for the SDRAM/DDR Controller.

Temporary keep the main clock hardcoded to 12MHz until we have the binding
for the PMC.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj-sclMFOaUSTBWk0Htik3J/w@public.gmane.org>
Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
---
 arch/arm/mach-at91/board-dt.c |    8 +-------
 arch/arm/mach-at91/generic.h  |    1 +
 arch/arm/mach-at91/setup.c    |   18 ++++++++++++++++++
 3 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index 9f729d6..c18d4d3 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -30,12 +30,6 @@
 #include "generic.h"
 
 
-static void __init ek_init_early(void)
-{
-	/* Initialize processor: 12.000 MHz crystal */
-	at91_initialize(12000000);
-}
-
 static const struct of_device_id irq_of_match[] __initconst = {
 
 	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
@@ -65,7 +59,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 	/* Maintainer: Atmel */
 	.timer		= &at91sam926x_timer,
 	.map_io		= at91_map_io,
-	.init_early	= ek_init_early,
+	.init_early	= at91_dt_initialize,
 	.init_irq	= at91_dt_init_irq,
 	.init_machine	= at91_dt_device_init,
 	.dt_compat	= at91_dt_board_compat,
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 459f01a..d5f5083 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -20,6 +20,7 @@ extern void __init at91_init_sram(int bank, unsigned long base,
 extern void __init at91rm9200_set_type(int type);
 extern void __init at91_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
+extern void __init at91_dt_initialize(void);
 
  /* Interrupts */
 extern void __init at91_init_irq_default(void);
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 372396c..c0bd5a6 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -9,6 +9,7 @@
 #include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/pm.h>
+#include <linux/of_address.h>
 
 #include <asm/mach/map.h>
 
@@ -285,6 +286,23 @@ void __init at91_ioremap_matrix(u32 base_addr)
 		panic("Impossible to ioremap at91_matrix_base\n");
 }
 
+#if defined(CONFIG_OF)
+void __init at91_dt_initialize(void)
+{
+	/* temporary until have the ramc binding*/
+	at91_boot_soc.ioremap_registers();
+
+	/* temporary until have the pmc binding */
+	/* Init clock subsystem */
+	at91_clock_init(12000000);
+
+	/* Register the processor-specific clocks */
+	at91_boot_soc.register_clocks();
+
+	at91_boot_soc.init();
+}
+#endif
+
 void __init at91_initialize(unsigned long main_clock)
 {
 	at91_boot_soc.ioremap_registers();
-- 
1.7.7

[PATCH 2/6] ARM: at91: add pmc DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Specified the main Oscillator via clock binding.
This will allow to do not hardcode it anymore in the DT board at 12MHz.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj-sclMFOaUSTBWk0Htik3J/w@public.gmane.org>
Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
---
 .../devicetree/bindings/arm/atmel-pmc.txt          |   11 ++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    5 ++
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |   11 ++++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 ++
 arch/arm/boot/dts/at91sam9x5cm.dtsi                |   11 ++++
 arch/arm/boot/dts/usb_a9g20.dts                    |   11 ++++
 arch/arm/mach-at91/clock.c                         |   56 ++++++++++++++++++--
 arch/arm/mach-at91/generic.h                       |    1 +
 arch/arm/mach-at91/setup.c                         |    3 +-
 10 files changed, 112 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt

diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
new file mode 100644
index 0000000..389bed5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
@@ -0,0 +1,11 @@
+* Power Management Controller (PMC)
+
+Required properties:
+- compatible: Should be "atmel,at91rm9200-pmc"
+- reg: Should contain PMC registers location and length
+
+Examples:
+	pmc: pmc@fffffc00 {
+		compatible = "atmel,at91rm9200-pmc";
+		reg = <0xfffffc00 0x100>;
+	};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index c030703..ee94828 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -59,6 +59,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pmc: pmc@fffffc00 {
+				compatible = "atmel,at91rm9200-pmc";
+				reg = <0xfffffc00 0x100>;
+			};
+
 			pit: timer@fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 4b54424..dfb71d5 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -60,6 +60,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pmc: pmc@fffffc00 {
+				compatible = "atmel,at91rm9200-pmc";
+				reg = <0xfffffc00 0x100>;
+			};
+
 			pit: timer@fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 4b1eb36..7147588 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -21,6 +21,17 @@
 		reg = <0x70000000 0x4000000>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		main_clock: clock@0 {
+			compatible = "atmel,osc", "fixed-clock";
+			clock-frequency = <12000000>;
+		};
+	};
+
 	ahb {
 		apb {
 			dbgu: serial@ffffee00 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index ac3c96c..a7d7107 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -58,6 +58,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pmc: pmc@fffffc00 {
+				compatible = "atmel,at91rm9200-pmc";
+				reg = <0xfffffc00 0x100>;
+			};
+
 			pit: timer@fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 3f84585..03116b2 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -12,6 +12,17 @@
 		reg = <0x20000000 0x8000000>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		main_clock: clock@0 {
+			compatible = "atmel,osc", "fixed-clock";
+			clock-frequency = <12000000>;
+		};
+	};
+
 	ahb {
 		nand0: nand@40000000 {
 			nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index e4a732f..390c481 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -20,6 +20,17 @@
 		reg = <0x20000000 0x4000000>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		main_clock: clock@0 {
+			compatible = "atmel,osc", "fixed-clock";
+			clock-frequency = <12000000>;
+		};
+	};
+
 	ahb {
 		apb {
 			dbgu: serial@fffff200 {
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index be51ca7..a0f4d74 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
 
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
@@ -671,16 +672,12 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
 	uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 
-int __init at91_clock_init(unsigned long main_clock)
+static int __init at91_pmc_init(unsigned long main_clock)
 {
 	unsigned tmp, freq, mckr;
 	int i;
 	int pll_overclock = false;
 
-	at91_pmc_base = ioremap(AT91_PMC, 256);
-	if (!at91_pmc_base)
-		panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
-
 	/*
 	 * When the bootloader initialized the main oscillator correctly,
 	 * there's no problem using the cycle counter.  But if it didn't,
@@ -802,6 +799,55 @@ int __init at91_clock_init(unsigned long main_clock)
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static struct of_device_id pmc_ids[] = {
+	{ .compatible = "atmel,at91rm9200-pmc" },
+	{ /*sentinel*/ }
+};
+
+static struct of_device_id osc_ids[] = {
+	{ .compatible = "atmel,osc" },
+	{ /*sentinel*/ }
+};
+
+int __init at91_dt_clock_init(void)
+{
+	struct device_node *np;
+	u32 main_clock = 0;
+
+	np = of_find_matching_node(NULL, pmc_ids);
+	if (!np)
+		panic("unable to find compatible pmc node in dtb\n");
+
+	at91_pmc_base = of_iomap(np, 0);
+	if (!at91_pmc_base)
+		panic("unable to map pmc cpu registers\n");
+
+	of_node_put(np);
+
+	/* retrieve the freqency of fixed clocks from device tree */
+	np = of_find_matching_node(NULL, osc_ids);
+	if (np) {
+		u32 rate;
+		if (!of_property_read_u32(np, "clock-frequency", &rate))
+			main_clock = rate;
+	}
+
+	of_node_put(np);
+
+	return at91_pmc_init(main_clock);
+}
+#endif
+
+int __init at91_clock_init(unsigned long main_clock)
+{
+	at91_pmc_base = ioremap(AT91_PMC, 256);
+	if (!at91_pmc_base)
+		panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
+	return at91_pmc_init(main_clock);
+}
+
 /*
  * Several unused clocks may be active.  Turn them off.
  */
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index d5f5083..dd9b346 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -53,6 +53,7 @@ extern void __init at91sam9rl_set_console_clock(int id);
 extern void __init at91sam9g45_set_console_clock(int id);
 #ifdef CONFIG_AT91_PMC_UNIT
 extern int __init at91_clock_init(unsigned long main_clock);
+extern int __init at91_dt_clock_init(void);
 #else
 static int inline at91_clock_init(unsigned long main_clock) { return 0; }
 #endif
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index c0bd5a6..d7abc25 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -292,9 +292,8 @@ void __init at91_dt_initialize(void)
 	/* temporary until have the ramc binding*/
 	at91_boot_soc.ioremap_registers();
 
-	/* temporary until have the pmc binding */
 	/* Init clock subsystem */
-	at91_clock_init(12000000);
+	at91_dt_clock_init();
 
 	/* Register the processor-specific clocks */
 	at91_boot_soc.register_clocks();
-- 
1.7.7

Re: [PATCH 0/6] AT91 more DT bindings

[Jean-Christophe PLAGNIOL-VILLARD]

Hi,

	Rob is ok for you?

Best Regards,
J.
On 20:28 Fri 02 Mar     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> HI,
> 
> 	The following patch series add the bindings for:
> 	 - PMC
> 	 - SDRAM/DDR Controller
> 	 - Reset Controller
> 	 - Shutdown Controller
> 
> The following changes since commit c5ec01650adb1976f928177cd7e71afcb82026c5:
> 
>   ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5 (2012-03-02 00:46:37 +0800)
> 
> are available in the git repository at:
>   git://github.com/at91linux/linux-at91.git ..BRANCH.NOT.VERIFIED..
> 
> Jean-Christophe PLAGNIOL-VILLARD (6):
>       ARM: at91/dt: add specific DT soc init
>       ARM: at91: add pmc DT support
>       ARM: at91: always enable sam9 restart
>       ARM: at91: add RSTC (Reset Controller) dt support
>       ARM: at91: add ram controller DT support
>       ARM: at91: add Shutdown Controller (SHDWC) DT support
> 
>  .../devicetree/bindings/arm/atmel-at91.txt         |   60 ++++++++
>  .../devicetree/bindings/arm/atmel-pmc.txt          |   11 ++
>  arch/arm/boot/dts/at91sam9g20.dtsi                 |   20 +++
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |   21 +++
>  arch/arm/boot/dts/at91sam9m10g45ek.dts             |   11 ++
>  arch/arm/boot/dts/at91sam9x5.dtsi                  |   20 +++
>  arch/arm/boot/dts/at91sam9x5cm.dtsi                |   11 ++
>  arch/arm/boot/dts/usb_a9g20.dts                    |   11 ++
>  arch/arm/mach-at91/Kconfig                         |   10 +-
>  arch/arm/mach-at91/at91sam9x5.c                    |    7 -
>  arch/arm/mach-at91/board-dt.c                      |    8 +-
>  arch/arm/mach-at91/clock.c                         |   54 ++++++-
>  arch/arm/mach-at91/generic.h                       |    2 +
>  arch/arm/mach-at91/include/mach/at91_shdwc.h       |    4 +-
>  arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 -
>  arch/arm/mach-at91/setup.c                         |  158 ++++++++++++++++++++
>  16 files changed, 380 insertions(+), 33 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt
> 
> Best Regards,
> J.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/6] ARM: at91: always enable sam9 restart

[Jean-Christophe PLAGNIOL-VILLARD]

This is need for multiple SoC in the same kernel image and DT.
As we will chose the restart function via binding.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/mach-at91/Kconfig |   10 ++--------
 1 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index e55cdcb..45db05d 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -20,9 +20,11 @@ config HAVE_AT91_USART5
 
 config AT91_SAM9_ALT_RESET
 	bool
+	default !ARCH_AT91X40
 
 config AT91_SAM9G45_RESET
 	bool
+	default !ARCH_AT91X40
 
 menu "Atmel AT91 System-on-Chip"
 
@@ -45,7 +47,6 @@ config ARCH_AT91SAM9260
 	select HAVE_AT91_USART4
 	select HAVE_AT91_USART5
 	select HAVE_NET_MACB
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9261
 	bool "AT91SAM9261"
@@ -53,7 +54,6 @@ config ARCH_AT91SAM9261
 	select GENERIC_CLOCKEVENTS
 	select HAVE_FB_ATMEL
 	select HAVE_AT91_DBGU0
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G10
 	bool "AT91SAM9G10"
@@ -61,7 +61,6 @@ config ARCH_AT91SAM9G10
 	select GENERIC_CLOCKEVENTS
 	select HAVE_AT91_DBGU0
 	select HAVE_FB_ATMEL
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9263
 	bool "AT91SAM9263"
@@ -70,7 +69,6 @@ config ARCH_AT91SAM9263
 	select HAVE_FB_ATMEL
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU1
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9RL
 	bool "AT91SAM9RL"
@@ -79,7 +77,6 @@ config ARCH_AT91SAM9RL
 	select HAVE_AT91_USART3
 	select HAVE_FB_ATMEL
 	select HAVE_AT91_DBGU0
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G20
 	bool "AT91SAM9G20"
@@ -90,7 +87,6 @@ config ARCH_AT91SAM9G20
 	select HAVE_AT91_USART4
 	select HAVE_AT91_USART5
 	select HAVE_NET_MACB
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G45
 	bool "AT91SAM9G45"
@@ -100,7 +96,6 @@ config ARCH_AT91SAM9G45
 	select HAVE_FB_ATMEL
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU1
-	select AT91_SAM9G45_RESET
 
 config ARCH_AT91SAM9X5
 	bool "AT91SAM9x5 family"
@@ -109,7 +104,6 @@ config ARCH_AT91SAM9X5
 	select HAVE_FB_ATMEL
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU0
-	select AT91_SAM9G45_RESET
 
 config ARCH_AT91X40
 	bool "AT91x40"
-- 
1.7.7

[PATCH 4/6] ARM: at91: add RSTC (Reset Controller) dt support

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 .../devicetree/bindings/arm/atmel-at91.txt         |   12 ++++++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 +++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    5 +++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 +++
 arch/arm/mach-at91/at91sam9x5.c                    |    1 -
 arch/arm/mach-at91/setup.c                         |   30 ++++++++++++++++++++
 6 files changed, 57 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 1aeaf6f..a64f867 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -30,3 +30,15 @@ One interrupt per TC channel in a TC block:
 		reg = <0xfffdc000 0x100>;
 		interrupts = <26 4 27 4 28 4>;
 	};
+
+RSTC Reset Controller required properties:
+- compatible: Should be "atmel,<chip>-rstc".
+  <chip> can be "at91sam9260" or "at91sam9g45"
+- reg: Should contain registers location and length
+
+Example:
+
+	rstc@fffffd00 {
+		compatible = "atmel,at91sam9260-rstc";
+		reg = <0xfffffd00 0x10>;
+	};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index ee94828..5414347 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -64,6 +64,11 @@
 				reg = <0xfffffc00 0x100>;
 			};
 
+			rstc@fffffd00 {
+				compatible = "atmel,at91sam9260-rstc";
+				reg = <0xfffffd00 0x10>;
+			};
+
 			pit: timer@fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index dfb71d5..e2ccba5 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -65,6 +65,11 @@
 				reg = <0xfffffc00 0x100>;
 			};
 
+			rstc@fffffd00 {
+				compatible = "atmel,at91sam9g45-rstc";
+				reg = <0xfffffd00 0x10>;
+			};
+
 			pit: timer@fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index a7d7107..54e3030 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -63,6 +63,11 @@
 				reg = <0xfffffc00 0x100>;
 			};
 
+			rstc@fffffe00 {
+				compatible = "atmel,at91sam9g45-rstc";
+				reg = <0xfffffe00 0x10>;
+			};
+
 			pit: timer@fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 7333276..0b82c34 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -309,7 +309,6 @@ static void __init at91sam9x5_ioremap_registers(void)
 
 void __init at91sam9x5_initialize(void)
 {
-	arm_pm_restart = at91sam9g45_restart;
 	at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
 
 	/* Register GPIO subsystem (using DT) */
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index d7abc25..3e48b59 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -287,8 +287,38 @@ void __init at91_ioremap_matrix(u32 base_addr)
 }
 
 #if defined(CONFIG_OF)
+static struct of_device_id rstc_ids[] = {
+	{ .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
+	{ .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
+	{ /*sentinel*/ }
+};
+
+static void at91_dt_rstc(void)
+{
+	struct device_node *np;
+	const struct of_device_id *of_id;
+
+	np = of_find_matching_node(NULL, rstc_ids);
+	if (!np)
+		panic("unable to find compatible rstc node in dtb\n");
+
+	at91_rstc_base = of_iomap(np, 0);
+	if (!at91_rstc_base)
+		panic("unable to map rstc cpu registers\n");
+
+	of_id = of_match_node(rstc_ids, np);
+	if (!of_id)
+		panic("AT91: rtsc no restart function availlable\n");
+
+	arm_pm_restart = of_id->data;
+
+	of_node_put(np);
+}
+
 void __init at91_dt_initialize(void)
 {
+	at91_dt_rstc();
+
 	/* temporary until have the ramc binding*/
 	at91_boot_soc.ioremap_registers();
 
-- 
1.7.7

[PATCH 5/6] ARM: at91: add ram controller DT support

[Jean-Christophe PLAGNIOL-VILLARD]

We can now drop the call to ioremap_registers() as we have the binding for the
SDRAM/DDR Controller.

Drop ioremap_registers() for sam9x5 too.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 .../devicetree/bindings/arm/atmel-at91.txt         |   19 ++++++++++++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 +++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 +++
 arch/arm/mach-at91/at91sam9x5.c                    |    6 ----
 arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 ---
 arch/arm/mach-at91/setup.c                         |   27 +++++++++++++++++--
 7 files changed, 59 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index a64f867..1f87820 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -42,3 +42,22 @@ Example:
 		compatible = "atmel,at91sam9260-rstc";
 		reg = <0xfffffd00 0x10>;
 	};
+
+RAMC SDRAM/DDR Controller required properties:
+- compatible: Should be "atmel,at91sam9260-sdramc",
+			"atmel,at91sam9g45-ddramc",
+- reg: Should contain registers location and length
+  For at91sam9263 and at91sam9g45 you must specify 2 entries.
+
+Examples:
+
+	ramc0: ramc@ffffe800 {
+		compatible = "atmel,at91sam9g45-ddramc";
+		reg = <0xffffe800 0x200>;
+	};
+
+	ramc0: ramc@ffffe400 {
+		compatible = "atmel,at91sam9g45-ddramc";
+		reg = <0xffffe400 0x200
+		       0xffffe600 0x200>;
+	};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 5414347..573ac5a 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -59,6 +59,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			ramc0: ramc@ffffea00 {
+				compatible = "atmel,at91sam9260-sdramc";
+				reg = <0xffffea00 0x200>;
+			};
+
 			pmc: pmc@fffffc00 {
 				compatible = "atmel,at91rm9200-pmc";
 				reg = <0xfffffc00 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index e2ccba5..6da07a9 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -60,6 +60,12 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			ramc0: ramc@ffffe400 {
+				compatible = "atmel,at91sam9g45-ddramc";
+				reg = <0xffffe400 0x200
+				       0xffffe600 0x200>;
+			};
+
 			pmc: pmc@fffffc00 {
 				compatible = "atmel,at91rm9200-pmc";
 				reg = <0xfffffc00 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 54e3030..09bc806 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -58,6 +58,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			ramc0: ramc@ffffe800 {
+				compatible = "atmel,at91sam9g45-ddramc";
+				reg = <0xffffe800 0x200>;
+			};
+
 			pmc: pmc@fffffc00 {
 				compatible = "atmel,at91rm9200-pmc";
 				reg = <0xfffffc00 0x100>;
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 0b82c34..b6831ee 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -302,11 +302,6 @@ static void __init at91sam9x5_map_io(void)
 	at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
 }
 
-static void __init at91sam9x5_ioremap_registers(void)
-{
-	at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
-}
-
 void __init at91sam9x5_initialize(void)
 {
 	at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
@@ -359,7 +354,6 @@ static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9x5_soc = {
 	.map_io = at91sam9x5_map_io,
 	.default_irq_priority = at91sam9x5_default_irq_priority,
-	.ioremap_registers = at91sam9x5_ioremap_registers,
 	.register_clocks = at91sam9x5_register_clocks,
 	.init = at91sam9x5_initialize,
 };
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index a297a77..88e43d5 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -55,11 +55,6 @@
 #define AT91SAM9X5_BASE_USART2	0xf8024000
 
 /*
- * System Peripherals
- */
-#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
-
-/*
  * Base addresses for early serial code (uncompress.h)
  */
 #define AT91_DBGU	AT91_BASE_DBGU0
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 3e48b59..f86450d 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
 	of_node_put(np);
 }
 
+static struct of_device_id ramc_ids[] = {
+	{ .compatible = "atmel,at91sam9260-sdramc" },
+	{ .compatible = "atmel,at91sam9g45-ddramc" },
+	{ /*sentinel*/ }
+};
+
+static void at91_dt_ramc(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, ramc_ids);
+	if (!np)
+		panic("unable to find compatible ram conroller node in dtb\n");
+
+	at91_ramc_base[0] = of_iomap(np, 0);
+	if (!at91_ramc_base[0])
+		panic("unable to map ramc[0] cpu registers\n");
+	/* the controller may have 2 banks */
+	at91_ramc_base[1] = of_iomap(np, 1);
+
+	of_node_put(np);
+}
+
 void __init at91_dt_initialize(void)
 {
 	at91_dt_rstc();
-
-	/* temporary until have the ramc binding*/
-	at91_boot_soc.ioremap_registers();
+	at91_dt_ramc();
 
 	/* Init clock subsystem */
 	at91_dt_clock_init();
-- 
1.7.7

Re: [PATCH 5/6] ARM: at91: add ram controller DT support

[Rob Herring]

On 03/02/2012 01:54 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> We can now drop the call to ioremap_registers() as we have the binding for the
> SDRAM/DDR Controller.
> 
> Drop ioremap_registers() for sam9x5 too.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
>  .../devicetree/bindings/arm/atmel-at91.txt         |   19 ++++++++++++++
>  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 +++
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++++
>  arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 +++
>  arch/arm/mach-at91/at91sam9x5.c                    |    6 ----
>  arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 ---
>  arch/arm/mach-at91/setup.c                         |   27 +++++++++++++++++--
>  7 files changed, 59 insertions(+), 14 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> index a64f867..1f87820 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> @@ -42,3 +42,22 @@ Example:
>  		compatible = "atmel,at91sam9260-rstc";
>  		reg = <0xfffffd00 0x10>;
>  	};
> +
> +RAMC SDRAM/DDR Controller required properties:
> +- compatible: Should be "atmel,at91sam9260-sdramc",
> +			"atmel,at91sam9g45-ddramc",
> +- reg: Should contain registers location and length
> +  For at91sam9263 and at91sam9g45 you must specify 2 entries.
> +
> +Examples:
> +
> +	ramc0: ramc@ffffe800 {
> +		compatible = "atmel,at91sam9g45-ddramc";
> +		reg = <0xffffe800 0x200>;
> +	};
> +
> +	ramc0: ramc@ffffe400 {
> +		compatible = "atmel,at91sam9g45-ddramc";
> +		reg = <0xffffe400 0x200
> +		       0xffffe600 0x200>;
> +	};
> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> index 5414347..573ac5a 100644
> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> @@ -59,6 +59,11 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			ramc0: ramc@ffffea00 {
> +				compatible = "atmel,at91sam9260-sdramc";
> +				reg = <0xffffea00 0x200>;
> +			};
> +
>  			pmc: pmc@fffffc00 {
>  				compatible = "atmel,at91rm9200-pmc";
>  				reg = <0xfffffc00 0x100>;
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> index e2ccba5..6da07a9 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -60,6 +60,12 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			ramc0: ramc@ffffe400 {
> +				compatible = "atmel,at91sam9g45-ddramc";
> +				reg = <0xffffe400 0x200
> +				       0xffffe600 0x200>;
> +			};
> +
>  			pmc: pmc@fffffc00 {
>  				compatible = "atmel,at91rm9200-pmc";
>  				reg = <0xfffffc00 0x100>;
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index 54e3030..09bc806 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -58,6 +58,11 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			ramc0: ramc@ffffe800 {
> +				compatible = "atmel,at91sam9g45-ddramc";
> +				reg = <0xffffe800 0x200>;
> +			};
> +
>  			pmc: pmc@fffffc00 {
>  				compatible = "atmel,at91rm9200-pmc";
>  				reg = <0xfffffc00 0x100>;
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 0b82c34..b6831ee 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -302,11 +302,6 @@ static void __init at91sam9x5_map_io(void)
>  	at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
>  }
>  
> -static void __init at91sam9x5_ioremap_registers(void)
> -{
> -	at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
> -}
> -
>  void __init at91sam9x5_initialize(void)
>  {
>  	at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
> @@ -359,7 +354,6 @@ static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
>  struct at91_init_soc __initdata at91sam9x5_soc = {
>  	.map_io = at91sam9x5_map_io,
>  	.default_irq_priority = at91sam9x5_default_irq_priority,
> -	.ioremap_registers = at91sam9x5_ioremap_registers,
>  	.register_clocks = at91sam9x5_register_clocks,
>  	.init = at91sam9x5_initialize,
>  };
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> index a297a77..88e43d5 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> @@ -55,11 +55,6 @@
>  #define AT91SAM9X5_BASE_USART2	0xf8024000
>  
>  /*
> - * System Peripherals
> - */
> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
> -
> -/*
>   * Base addresses for early serial code (uncompress.h)
>   */
>  #define AT91_DBGU	AT91_BASE_DBGU0
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index 3e48b59..f86450d 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
>  	of_node_put(np);
>  }
>  
> +static struct of_device_id ramc_ids[] = {
> +	{ .compatible = "atmel,at91sam9260-sdramc" },
> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
> +	{ /*sentinel*/ }
> +};
> +
> +static void at91_dt_ramc(void)
> +{
> +	struct device_node *np;
> +
> +	np = of_find_matching_node(NULL, ramc_ids);
> +	if (!np)
> +		panic("unable to find compatible ram conroller node in dtb\n");

You really can't boot if this fails? A WARN is better if it allows you
to boot until at least your console is actually up.

> +
> +	at91_ramc_base[0] = of_iomap(np, 0);
> +	if (!at91_ramc_base[0])
> +		panic("unable to map ramc[0] cpu registers\n");
> +	/* the controller may have 2 banks */
> +	at91_ramc_base[1] = of_iomap(np, 1);
> +
> +	of_node_put(np);
> +}
> +
>  void __init at91_dt_initialize(void)
>  {
>  	at91_dt_rstc();
> -
> -	/* temporary until have the ramc binding*/
> -	at91_boot_soc.ioremap_registers();
> +	at91_dt_ramc();
>  
>  	/* Init clock subsystem */
>  	at91_dt_clock_init();

Re: [PATCH 5/6] ARM: at91: add ram controller DT support

[Jean-Christophe PLAGNIOL-VILLARD]

> > diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> > index a297a77..88e43d5 100644
> > --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> > +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> > @@ -55,11 +55,6 @@
> >  #define AT91SAM9X5_BASE_USART2	0xf8024000
> >  
> >  /*
> > - * System Peripherals
> > - */
> > -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
> > -
> > -/*
> >   * Base addresses for early serial code (uncompress.h)
> >   */
> >  #define AT91_DBGU	AT91_BASE_DBGU0
> > diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> > index 3e48b59..f86450d 100644
> > --- a/arch/arm/mach-at91/setup.c
> > +++ b/arch/arm/mach-at91/setup.c
> > @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
> >  	of_node_put(np);
> >  }
> >  
> > +static struct of_device_id ramc_ids[] = {
> > +	{ .compatible = "atmel,at91sam9260-sdramc" },
> > +	{ .compatible = "atmel,at91sam9g45-ddramc" },
> > +	{ /*sentinel*/ }
> > +};
> > +
> > +static void at91_dt_ramc(void)
> > +{
> > +	struct device_node *np;
> > +
> > +	np = of_find_matching_node(NULL, ramc_ids);
> > +	if (!np)
> > +		panic("unable to find compatible ram conroller node in dtb\n");
> 
> You really can't boot if this fails? A WARN is better if it allows you
> to boot until at least your console is actually up.
if the restart is called you will have a oops so no it's a basic mandatory
device on at91

Best Regards,
J.

Re: [PATCH 5/6] ARM: at91: add ram controller DT support

[Rob Herring]

On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>> index a297a77..88e43d5 100644
>>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>> @@ -55,11 +55,6 @@
>>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
>>>  
>>>  /*
>>> - * System Peripherals
>>> - */
>>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
>>> -
>>> -/*
>>>   * Base addresses for early serial code (uncompress.h)
>>>   */
>>>  #define AT91_DBGU	AT91_BASE_DBGU0
>>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
>>> index 3e48b59..f86450d 100644
>>> --- a/arch/arm/mach-at91/setup.c
>>> +++ b/arch/arm/mach-at91/setup.c
>>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
>>>  	of_node_put(np);
>>>  }
>>>  
>>> +static struct of_device_id ramc_ids[] = {
>>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
>>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
>>> +	{ /*sentinel*/ }
>>> +};
>>> +
>>> +static void at91_dt_ramc(void)
>>> +{
>>> +	struct device_node *np;
>>> +
>>> +	np = of_find_matching_node(NULL, ramc_ids);
>>> +	if (!np)
>>> +		panic("unable to find compatible ram conroller node in dtb\n");
>>
>> You really can't boot if this fails? A WARN is better if it allows you
>> to boot until at least your console is actually up.
> if the restart is called you will have a oops so no it's a basic mandatory
> device on at91
> 

But you may never see the panic message because your console is not up.
If you WARN and can continue to boot, then the user can see the problem
and fix it. Otherwise you get nothing and have to go rebuild and turn on
earlyprintk.

Rob

Re: [PATCH 5/6] ARM: at91: add ram controller DT support

[Jean-Christophe PLAGNIOL-VILLARD]

On 08:12 Thu 08 Mar     , Rob Herring wrote:
> On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>> index a297a77..88e43d5 100644
> >>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>> @@ -55,11 +55,6 @@
> >>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
> >>>  
> >>>  /*
> >>> - * System Peripherals
> >>> - */
> >>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
> >>> -
> >>> -/*
> >>>   * Base addresses for early serial code (uncompress.h)
> >>>   */
> >>>  #define AT91_DBGU	AT91_BASE_DBGU0
> >>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> >>> index 3e48b59..f86450d 100644
> >>> --- a/arch/arm/mach-at91/setup.c
> >>> +++ b/arch/arm/mach-at91/setup.c
> >>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
> >>>  	of_node_put(np);
> >>>  }
> >>>  
> >>> +static struct of_device_id ramc_ids[] = {
> >>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
> >>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
> >>> +	{ /*sentinel*/ }
> >>> +};
> >>> +
> >>> +static void at91_dt_ramc(void)
> >>> +{
> >>> +	struct device_node *np;
> >>> +
> >>> +	np = of_find_matching_node(NULL, ramc_ids);
> >>> +	if (!np)
> >>> +		panic("unable to find compatible ram conroller node in dtb\n");
> >>
> >> You really can't boot if this fails? A WARN is better if it allows you
> >> to boot until at least your console is actually up.
> > if the restart is called you will have a oops so no it's a basic mandatory
> > device on at91
> > 
> 
> But you may never see the panic message because your console is not up.
> If you WARN and can continue to boot, then the user can see the problem
> and fix it. Otherwise you get nothing and have to go rebuild and turn on
> earlyprintk.
yeah agreed but if the restart id use before the console is enable you will
have the same issue. the ramc controller are basic device so people usally
don't touch it except you add a SoC support.

so I prefer to panic

Best Regards,
J.

Re: [PATCH 5/6] ARM: at91: add ram controller DT support

[Rob Herring]

On 03/08/2012 08:10 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 08:12 Thu 08 Mar     , Rob Herring wrote:
>> On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>> index a297a77..88e43d5 100644
>>>>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>> @@ -55,11 +55,6 @@
>>>>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
>>>>>  
>>>>>  /*
>>>>> - * System Peripherals
>>>>> - */
>>>>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
>>>>> -
>>>>> -/*
>>>>>   * Base addresses for early serial code (uncompress.h)
>>>>>   */
>>>>>  #define AT91_DBGU	AT91_BASE_DBGU0
>>>>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
>>>>> index 3e48b59..f86450d 100644
>>>>> --- a/arch/arm/mach-at91/setup.c
>>>>> +++ b/arch/arm/mach-at91/setup.c
>>>>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
>>>>>  	of_node_put(np);
>>>>>  }
>>>>>  
>>>>> +static struct of_device_id ramc_ids[] = {
>>>>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
>>>>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
>>>>> +	{ /*sentinel*/ }
>>>>> +};
>>>>> +
>>>>> +static void at91_dt_ramc(void)
>>>>> +{
>>>>> +	struct device_node *np;
>>>>> +
>>>>> +	np = of_find_matching_node(NULL, ramc_ids);
>>>>> +	if (!np)
>>>>> +		panic("unable to find compatible ram conroller node in dtb\n");
>>>>
>>>> You really can't boot if this fails? A WARN is better if it allows you
>>>> to boot until at least your console is actually up.
>>> if the restart is called you will have a oops so no it's a basic mandatory
>>> device on at91
>>>
>>
>> But you may never see the panic message because your console is not up.
>> If you WARN and can continue to boot, then the user can see the problem
>> and fix it. Otherwise you get nothing and have to go rebuild and turn on
>> earlyprintk.
> yeah agreed but if the restart id use before the console is enable you will
> have the same issue. the ramc controller are basic device so people usally
> don't touch it except you add a SoC support.
> 
> so I prefer to panic
> 

Then panic in the restart code if it doesn't have something it needs.

Rob

Re: [PATCH 5/6] ARM: at91: add ram controller DT support

[Jean-Christophe PLAGNIOL-VILLARD]

On 09:24 Thu 08 Mar     , Rob Herring wrote:
> On 03/08/2012 08:10 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 08:12 Thu 08 Mar     , Rob Herring wrote:
> >> On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>>>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>>>> index a297a77..88e43d5 100644
> >>>>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>>>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>>>> @@ -55,11 +55,6 @@
> >>>>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
> >>>>>  
> >>>>>  /*
> >>>>> - * System Peripherals
> >>>>> - */
> >>>>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
> >>>>> -
> >>>>> -/*
> >>>>>   * Base addresses for early serial code (uncompress.h)
> >>>>>   */
> >>>>>  #define AT91_DBGU	AT91_BASE_DBGU0
> >>>>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> >>>>> index 3e48b59..f86450d 100644
> >>>>> --- a/arch/arm/mach-at91/setup.c
> >>>>> +++ b/arch/arm/mach-at91/setup.c
> >>>>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
> >>>>>  	of_node_put(np);
> >>>>>  }
> >>>>>  
> >>>>> +static struct of_device_id ramc_ids[] = {
> >>>>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
> >>>>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
> >>>>> +	{ /*sentinel*/ }
> >>>>> +};
> >>>>> +
> >>>>> +static void at91_dt_ramc(void)
> >>>>> +{
> >>>>> +	struct device_node *np;
> >>>>> +
> >>>>> +	np = of_find_matching_node(NULL, ramc_ids);
> >>>>> +	if (!np)
> >>>>> +		panic("unable to find compatible ram conroller node in dtb\n");
> >>>>
> >>>> You really can't boot if this fails? A WARN is better if it allows you
> >>>> to boot until at least your console is actually up.
> >>> if the restart is called you will have a oops so no it's a basic mandatory
> >>> device on at91
> >>>
> >>
> >> But you may never see the panic message because your console is not up.
> >> If you WARN and can continue to boot, then the user can see the problem
> >> and fix it. Otherwise you get nothing and have to go rebuild and turn on
> >> earlyprintk.
> > yeah agreed but if the restart id use before the console is enable you will
> > have the same issue. the ramc controller are basic device so people usally
> > don't touch it except you add a SoC support.
> > 
> > so I prefer to panic
> > 
> 
> Then panic in the restart code if it doesn't have something it needs.
The code is in assembly (mandatory) so difficult

The warn on other missing binding agreed but here please let go
It's basic device that except the maintainer will never touch

People will just include the dtsi and if you really need to debug soc init
enable earlyprintk is fine

Best Regards,
J.

Re: [PATCH 5/6] ARM: at91: add ram controller DT support

[Rob Herring]

On 03/08/2012 10:51 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 09:24 Thu 08 Mar     , Rob Herring wrote:
>> On 03/08/2012 08:10 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 08:12 Thu 08 Mar     , Rob Herring wrote:
>>>> On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>>>>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>>>> index a297a77..88e43d5 100644
>>>>>>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>>>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>>>> @@ -55,11 +55,6 @@
>>>>>>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
>>>>>>>  
>>>>>>>  /*
>>>>>>> - * System Peripherals
>>>>>>> - */
>>>>>>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
>>>>>>> -
>>>>>>> -/*
>>>>>>>   * Base addresses for early serial code (uncompress.h)
>>>>>>>   */
>>>>>>>  #define AT91_DBGU	AT91_BASE_DBGU0
>>>>>>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
>>>>>>> index 3e48b59..f86450d 100644
>>>>>>> --- a/arch/arm/mach-at91/setup.c
>>>>>>> +++ b/arch/arm/mach-at91/setup.c
>>>>>>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
>>>>>>>  	of_node_put(np);
>>>>>>>  }
>>>>>>>  
>>>>>>> +static struct of_device_id ramc_ids[] = {
>>>>>>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
>>>>>>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
>>>>>>> +	{ /*sentinel*/ }
>>>>>>> +};
>>>>>>> +
>>>>>>> +static void at91_dt_ramc(void)
>>>>>>> +{
>>>>>>> +	struct device_node *np;
>>>>>>> +
>>>>>>> +	np = of_find_matching_node(NULL, ramc_ids);
>>>>>>> +	if (!np)
>>>>>>> +		panic("unable to find compatible ram conroller node in dtb\n");
>>>>>>
>>>>>> You really can't boot if this fails? A WARN is better if it allows you
>>>>>> to boot until at least your console is actually up.
>>>>> if the restart is called you will have a oops so no it's a basic mandatory
>>>>> device on at91
>>>>>
>>>>
>>>> But you may never see the panic message because your console is not up.
>>>> If you WARN and can continue to boot, then the user can see the problem
>>>> and fix it. Otherwise you get nothing and have to go rebuild and turn on
>>>> earlyprintk.
>>> yeah agreed but if the restart id use before the console is enable you will
>>> have the same issue. the ramc controller are basic device so people usally
>>> don't touch it except you add a SoC support.
>>>
>>> so I prefer to panic
>>>
>>
>> Then panic in the restart code if it doesn't have something it needs.
> The code is in assembly (mandatory) so difficult
> 
> The warn on other missing binding agreed but here please let go
> It's basic device that except the maintainer will never touch
> 
> People will just include the dtsi and if you really need to debug soc init
> enable earlyprintk is fine

Okay.

Acked-by: Rob Herring <rob.herring@calxeda.com>

[PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support

[Jean-Christophe PLAGNIOL-VILLARD]

Use a string to specific the wakeup mode to make it more readable.

Add the Real-time Clock Wake-up support too for sam9g45 and sam9x5.
Add AT91_SHDW_CPTWK0_MAX to specific the Max of the Wakeup Counter.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 .../devicetree/bindings/arm/atmel-at91.txt         |   29 +++++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 +
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    5 +
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 +
 arch/arm/mach-at91/include/mach/at91_shdwc.h       |    4 +-
 arch/arm/mach-at91/setup.c                         |   89 ++++++++++++++++++++
 6 files changed, 136 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 1f87820..ecc81e3 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -61,3 +61,32 @@ Examples:
 		reg = <0xffffe400 0x200
 		       0xffffe600 0x200>;
 	};
+
+SHDWC Shutdown Controller
+
+required properties:
+- compatible: Should be "atmel,<chip>-shdwc".
+  <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
+- reg: Should contain registers location and length
+
+optional properties:
+- atmel,wakeup-mode: String, operation mode of the wakeup mode.
+  Supported values are: "none", "high", "low", "any".
+- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
+
+optional at91sam9260 properties:
+- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
+
+optional at91sam9rl properties:
+- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
+- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
+
+optional at91sam9x5 properties:
+- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
+
+Example:
+
+	rstc@fffffd00 {
+		compatible = "atmel,at91sam9260-rstc";
+		reg = <0xfffffd00 0x10>;
+	};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 573ac5a..62c85ac 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -74,6 +74,11 @@
 				reg = <0xfffffd00 0x10>;
 			};
 
+			shdwc@fffffd10 {
+				compatible = "atmel,at91sam9260-shdwc";
+				reg = <0xfffffd10 0x10>;
+			};
+
 			pit: timer@fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 6da07a9..e655d01 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -83,6 +83,11 @@
 			};
 
 
+			shdwc@fffffd10 {
+				compatible = "atmel,at91sam9rl-shdwc";
+				reg = <0xfffffd10 0x10>;
+			};
+
 			tcb0: timer@fff7c000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfff7c000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 09bc806..8a68f33 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -73,6 +73,11 @@
 				reg = <0xfffffe00 0x10>;
 			};
 
+			shdwc@fffffe10 {
+				compatible = "atmel,at91sam9x5-shdwc";
+				reg = <0xfffffe10 0x10>;
+			};
+
 			pit: timer@fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
index 1d4fe82..60478ea 100644
--- a/arch/arm/mach-at91/include/mach/at91_shdwc.h
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -36,9 +36,11 @@ extern void __iomem *at91_shdwc_base;
 #define			AT91_SHDW_WKMODE0_HIGH		1
 #define			AT91_SHDW_WKMODE0_LOW		2
 #define			AT91_SHDW_WKMODE0_ANYLEVEL	3
-#define		AT91_SHDW_CPTWK0	(0xf << 4)		/* Counter On Wake Up 0 */
+#define		AT91_SHDW_CPTWK0_MAX	0xf			/* Maximum Counter On Wake Up 0 */
+#define		AT91_SHDW_CPTWK0	(AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
 #define			AT91_SHDW_CPTWK0_(x)	((x) << 4)
 #define		AT91_SHDW_RTTWKEN	(1   << 16)		/* Real Time Timer Wake-up Enable */
+#define		AT91_SHDW_RTCWKEN	(1   << 17)		/* Real Time Clock Wake-up Enable */
 
 #define AT91_SHDW_SR		0x08			/* Shut Down Status Register */
 #define		AT91_SHDW_WAKEUP0	(1 <<  0)		/* Wake-up 0 Status */
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index f86450d..9206a67 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -338,10 +338,99 @@ static void at91_dt_ramc(void)
 	of_node_put(np);
 }
 
+static struct of_device_id shdwc_ids[] = {
+	{ .compatible = "atmel,at91sam9260-shdwc", },
+	{ .compatible = "atmel,at91sam9rl-shdwc", },
+	{ .compatible = "atmel,at91sam9x5-shdwc", },
+	{ /*sentinel*/ }
+};
+
+static const char *shdwc_wakeup_modes[] = {
+	[AT91_SHDW_WKMODE0_NONE]	= "none",
+	[AT91_SHDW_WKMODE0_HIGH]	= "high",
+	[AT91_SHDW_WKMODE0_LOW]		= "low",
+	[AT91_SHDW_WKMODE0_ANYLEVEL]	= "any",
+};
+
+const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
+{
+	const char *pm;
+	int err, i;
+
+	err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
+	if (err < 0)
+		return AT91_SHDW_WKMODE0_ANYLEVEL;
+
+	for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
+		if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
+			return i;
+
+	return -ENODEV;
+}
+
+static void at91_dt_shdwc(void)
+{
+	struct device_node *np;
+	int wakeup_mode;
+	bool have_rtt, have_rtc;
+	u32 reg;
+	u32 mode = 0;
+
+	np = of_find_matching_node(NULL, shdwc_ids);
+	if (!np) {
+		pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
+		return;
+	}
+
+	at91_shdwc_base = of_iomap(np, 0);
+	if (!at91_shdwc_base)
+		panic("AT91: unable to map shdwc cpu registers\n");
+
+	wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
+	if (wakeup_mode < 0) {
+		pr_warn("AT91: shdwc unknown wakeup mode\n");
+		goto end;
+	}
+
+	if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
+		if (reg > AT91_SHDW_CPTWK0_MAX) {
+			pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
+				reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
+			reg = AT91_SHDW_CPTWK0_MAX;
+		}
+		mode |= AT91_SHDW_CPTWK0_(reg);
+	}
+
+	if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
+		have_rtt = false;
+		have_rtc = true;
+	} else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
+		have_rtt = true;
+		have_rtc = true;
+	} else {
+		have_rtt = true;
+		have_rtc = false;
+	}
+
+	if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
+			mode |= AT91_SHDW_RTCWKEN;
+
+	if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
+			mode |= AT91_SHDW_RTTWKEN;
+
+	at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
+
+end:
+	pm_power_off = at91sam9_poweroff;
+
+	of_node_put(np);
+}
+
 void __init at91_dt_initialize(void)
 {
 	at91_dt_rstc();
 	at91_dt_ramc();
+	at91_dt_shdwc();
 
 	/* Init clock subsystem */
 	at91_dt_clock_init();
-- 
1.7.7

Re: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support

[Arnd Bergmann]

On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> +       }
> +
> +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
> +               have_rtt = false;
> +               have_rtc = true;
> +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
> +               have_rtt = true;
> +               have_rtc = true;
> +       } else {
> +               have_rtt = true;
> +               have_rtc = false;
> +       }
> +
> +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
> +                       mode |= AT91_SHDW_RTCWKEN;
> +
> +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
> +                       mode |= AT91_SHDW_RTTWKEN;
> +
> +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
> +

Hi Jean-Christophe,

I don't understand why you check the specific part here. Isn't it enough to
check the property when you already mandate that they can only be present
on devices that support the specific wakeup?

If there is a good explanation for that, maybe add a code comment why it's
required.

	Arnd

Re: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support

[Jean-Christophe PLAGNIOL-VILLARD]

On 20:24 Fri 02 Mar     , Arnd Bergmann wrote:
> On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > +       }
> > +
> > +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
> > +               have_rtt = false;
> > +               have_rtc = true;
> > +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
> > +               have_rtt = true;
> > +               have_rtc = true;
> > +       } else {
> > +               have_rtt = true;
> > +               have_rtc = false;
> > +       }
> > +
> > +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
> > +                       mode |= AT91_SHDW_RTCWKEN;
> > +
> > +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
> > +                       mode |= AT91_SHDW_RTTWKEN;
> > +
> > +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
> > +
> 
> Hi Jean-Christophe,
> 
> I don't understand why you check the specific part here. Isn't it enough to
> check the property when you already mandate that they can only be present
> on devices that support the specific wakeup?
> 
> If there is a good explanation for that, maybe add a code comment why it's
> required.
some wake update source exist on few soc and we are not supposed to set the
bit otherwise

Ill put a comment.

Best Regards,
J.

Re: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support

[Arnd Bergmann]

On Wednesday 07 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 20:24 Fri 02 Mar     , Arnd Bergmann wrote:
> > On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > +       }
> > > +
> > > +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
> > > +               have_rtt = false;
> > > +               have_rtc = true;
> > > +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
> > > +               have_rtt = true;
> > > +               have_rtc = true;
> > > +       } else {
> > > +               have_rtt = true;
> > > +               have_rtc = false;
> > > +       }
> > > +
> > > +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
> > > +                       mode |= AT91_SHDW_RTCWKEN;
> > > +
> > > +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
> > > +                       mode |= AT91_SHDW_RTTWKEN;
> > > +
> > > +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
> > > +
> > 
> > Hi Jean-Christophe,
> > 
> > I don't understand why you check the specific part here. Isn't it enough to
> > check the property when you already mandate that they can only be present
> > on devices that support the specific wakeup?
> > 
> > If there is a good explanation for that, maybe add a code comment why it's
> > required.
> some wake update source exist on few soc and we are not supposed to set the
> bit otherwise
> 

I still don't understand: Doesn't the property already give the information?
In general, you should try to encode these things in specific properties instead of
checking the compatible property.

	Arnd

Re: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:49 Wed 07 Mar     , Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 20:24 Fri 02 Mar     , Arnd Bergmann wrote:
> > > On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > +       }
> > > > +
> > > > +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
> > > > +               have_rtt = false;
> > > > +               have_rtc = true;
> > > > +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
> > > > +               have_rtt = true;
> > > > +               have_rtc = true;
> > > > +       } else {
> > > > +               have_rtt = true;
> > > > +               have_rtc = false;
> > > > +       }
> > > > +
> > > > +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
> > > > +                       mode |= AT91_SHDW_RTCWKEN;
> > > > +
> > > > +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
> > > > +                       mode |= AT91_SHDW_RTTWKEN;
> > > > +
> > > > +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
> > > > +
> > > 
> > > Hi Jean-Christophe,
> > > 
> > > I don't understand why you check the specific part here. Isn't it enough to
> > > check the property when you already mandate that they can only be present
> > > on devices that support the specific wakeup?
> > > 
> > > If there is a good explanation for that, maybe add a code comment why it's
> > > required.
> > some wake update source exist on few soc and we are not supposed to set the
> > bit otherwise
> > 
> 
> I still don't understand: Doesn't the property already give the information?
Yes
> In general, you should try to encode these things in specific properties instead of
> checking the compatible property.
But I check that no mistake is done in the DT as the source of wakeup is
availlable on different version of the IP

Just more cautious

Best Regards,
J.

Re: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support

[Rob Herring]

On 03/07/2012 12:49 PM, Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 20:24 Fri 02 Mar     , Arnd Bergmann wrote:
>>> On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>> +       }
>>>> +
>>>> +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
>>>> +               have_rtt = false;
>>>> +               have_rtc = true;
>>>> +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
>>>> +               have_rtt = true;
>>>> +               have_rtc = true;
>>>> +       } else {
>>>> +               have_rtt = true;
>>>> +               have_rtc = false;
>>>> +       }
>>>> +
>>>> +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
>>>> +                       mode |= AT91_SHDW_RTCWKEN;
>>>> +
>>>> +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
>>>> +                       mode |= AT91_SHDW_RTTWKEN;
>>>> +
>>>> +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
>>>> +
>>>
>>> Hi Jean-Christophe,
>>>
>>> I don't understand why you check the specific part here. Isn't it enough to
>>> check the property when you already mandate that they can only be present
>>> on devices that support the specific wakeup?
>>>
>>> If there is a good explanation for that, maybe add a code comment why it's
>>> required.
>> some wake update source exist on few soc and we are not supposed to set the
>> bit otherwise
>>
> 
> I still don't understand: Doesn't the property already give the information?
> In general, you should try to encode these things in specific properties instead of
> checking the compatible property.
> 

Or vice-versa, the compatible properties distinguish things enough that
the property is not needed. If it is fixed in the SOC design, then you
should distinguish things with the compatible property.

Rob

> 	Arnd
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support

[Arnd Bergmann]

On Wednesday 07 March 2012, Rob Herring wrote:
> > 
> > I still don't understand: Doesn't the property already give the information?
> > In general, you should try to encode these things in specific properties instead of
> > checking the compatible property.
> > 
> 
> Or vice-versa, the compatible properties distinguish things enough that
> the property is not needed. If it is fixed in the SOC design, then you
> should distinguish things with the compatible property.

Well, one of the two, basically. I would suggest using special properties
in order to be prepared when other SOCs have the same requirement. If you
know for certain that each one will only ever be needed in one specific
SOC, then the compatible property is enough, but if it's likely that others
will have the same requirement in the future, I think it's much better
to have just a single check rather than a list of SOCs.

	Arnd