From mboxrd@z Thu Jan 1 00:00:00 1970 From: Leela Krishna Amudala Subject: [PATCH V2 7/7] ARM: EXYNOS5: Set parent clock to fimd Date: Wed, 18 Jul 2012 11:27:33 +0530 Message-ID: <1342591053-7092-8-git-send-email-l.krishna@samsung.com> References: <1342591053-7092-1-git-send-email-l.krishna@samsung.com> Return-path: In-reply-to: <1342591053-7092-1-git-send-email-l.krishna@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org To: devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, grant.likely@secretlab.ca, olofj@google.com, thomas.ab@samsung.com, kgene.kim@samsung.com, joshi@samsung.com, jg1.han@samsung.com List-Id: devicetree@vger.kernel.org This patch sets mout_mpll_user as parent clock to fimd also sets Fimd source clock rate to 800 MHz for MIPI LCD Signed-off-by: Leela Krishna Amudala --- arch/arm/mach-exynos/clock-exynos5.c | 25 +++++++++++++++---------- arch/arm/mach-exynos/mach-exynos5-dt.c | 11 +++++++++++ arch/arm/plat-samsung/include/plat/clock.h | 2 ++ 3 files changed, 28 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index f001876..8c20c4d 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -1125,6 +1125,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = { .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, }; +struct clksrc_clk exynos5_clk_sclk_fimd = { + .clk = { + .name = "sclk_fimd", + .devname = "exynos5-fb", + .enable = exynos5_clksrc_mask_disp1_0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 }, +}; + static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { @@ -1136,16 +1148,6 @@ static struct clksrc_clk exynos5_clksrcs[] = { .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 }, }, { .clk = { - .name = "sclk_fimd", - .devname = "exynos5-fb", - .enable = exynos5_clksrc_mask_disp1_0_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 }, - }, { - .clk = { .name = "aclk_266_gscl", }, .sources = &clk_src_gscl_266, @@ -1245,6 +1247,7 @@ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_mdout_spi0, &exynos5_clk_mdout_spi1, &exynos5_clk_mdout_spi2, + &exynos5_clk_sclk_fimd, }; static struct clk *exynos5_clk_cdev[] = { @@ -1497,6 +1500,8 @@ void __init_or_cpufreq exynos5_setup_clocks(void) clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000); clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000); + clk_set_parent(&exynos5_clk_sclk_fimd.clk, + &exynos5_clk_mout_mpll_user.clk); for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++) s3c_set_clksrc(&exynos5_clksrcs[ptr], true); diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 2107e01..19f3724 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -24,6 +24,9 @@ #include #include #include +#include +#include +#include #include "common.h" #include