* [PATCH v4 03/16] tegra: fdt: Add pwm binding and node [not found] ` <1348793077-10126-1-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> @ 2012-09-28 0:44 ` Simon Glass 2012-09-28 20:08 ` Thierry Reding 2012-09-28 0:44 ` [PATCH v4 04/16] tegra: fdt: Add LCD definitions for Tegra Simon Glass 2012-09-28 0:44 ` [PATCH v4 14/16] tegra: fdt: Add LCD definitions for Seaboard Simon Glass 2 siblings, 1 reply; 10+ messages in thread From: Simon Glass @ 2012-09-28 0:44 UTC (permalink / raw) To: U-Boot Mailing List Cc: Stephen Warren, Devicetree Discuss, Jerry Van Baren, Tom Warren This binding will apparently soon be in linux-next. Bring it in now since we need to do something, and may as well try to target what Linux will have. Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> --- Changes in v3: - Add new commit for pwm binding and node arch/arm/dts/tegra20.dtsi | 7 +++++++ doc/device-tree-bindings/pwm/tegra20-pwm.txt | 18 ++++++++++++++++++ 2 files changed, 25 insertions(+), 0 deletions(-) create mode 100644 doc/device-tree-bindings/pwm/tegra20-pwm.txt diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index d936b1e..3221bc9 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -211,4 +211,11 @@ compatible = "nvidia,tegra20-nand"; reg = <0x70008000 0x100>; }; + + pwm: pwm@7000a000 { + compatible = "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + }; + }; diff --git a/doc/device-tree-bindings/pwm/tegra20-pwm.txt b/doc/device-tree-bindings/pwm/tegra20-pwm.txt new file mode 100644 index 0000000..bbbeedb --- /dev/null +++ b/doc/device-tree-bindings/pwm/tegra20-pwm.txt @@ -0,0 +1,18 @@ +Tegra SoC PWFM controller + +Required properties: +- compatible: should be one of: + - "nvidia,tegra20-pwm" + - "nvidia,tegra30-pwm" +- reg: physical base address and length of the controller's registers +- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The + first cell specifies the per-chip index of the PWM to use and the second + cell is the duty cycle in nanoseconds. + +Example: + + pwm: pwm@7000a000 { + compatible = "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + }; -- 1.7.7.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4 03/16] tegra: fdt: Add pwm binding and node 2012-09-28 0:44 ` [PATCH v4 03/16] tegra: fdt: Add pwm binding and node Simon Glass @ 2012-09-28 20:08 ` Thierry Reding [not found] ` <20120928200817.GB30777-RM9K5IK7kjIQXX3q8xo1gnVAuStQJXxyR5q1nwbD4aMs9pC9oP6+/A@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Thierry Reding @ 2012-09-28 20:08 UTC (permalink / raw) To: Simon Glass Cc: U-Boot Mailing List, Devicetree Discuss, Stephen Warren, Jerry Van Baren, Tom Warren [-- Attachment #1.1: Type: text/plain, Size: 1894 bytes --] On Thu, Sep 27, 2012 at 05:44:24PM -0700, Simon Glass wrote: > This binding will apparently soon be in linux-next. Bring it in now > since we need to do something, and may as well try to target what > Linux will have. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > Changes in v3: > - Add new commit for pwm binding and node > > arch/arm/dts/tegra20.dtsi | 7 +++++++ > doc/device-tree-bindings/pwm/tegra20-pwm.txt | 18 ++++++++++++++++++ > 2 files changed, 25 insertions(+), 0 deletions(-) > create mode 100644 doc/device-tree-bindings/pwm/tegra20-pwm.txt > > diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi > index d936b1e..3221bc9 100644 > --- a/arch/arm/dts/tegra20.dtsi > +++ b/arch/arm/dts/tegra20.dtsi > @@ -211,4 +211,11 @@ > compatible = "nvidia,tegra20-nand"; > reg = <0x70008000 0x100>; > }; > + > + pwm: pwm@7000a000 { > + compatible = "nvidia,tegra20-pwm"; > + reg = <0x7000a000 0x100>; > + #pwm-cells = <2>; > + }; > + > }; > diff --git a/doc/device-tree-bindings/pwm/tegra20-pwm.txt b/doc/device-tree-bindings/pwm/tegra20-pwm.txt > new file mode 100644 > index 0000000..bbbeedb > --- /dev/null > +++ b/doc/device-tree-bindings/pwm/tegra20-pwm.txt > @@ -0,0 +1,18 @@ > +Tegra SoC PWFM controller > + > +Required properties: > +- compatible: should be one of: > + - "nvidia,tegra20-pwm" > + - "nvidia,tegra30-pwm" > +- reg: physical base address and length of the controller's registers > +- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The > + first cell specifies the per-chip index of the PWM to use and the second > + cell is the duty cycle in nanoseconds. This is a mistake in the Linux kernel documentation. The second cell specifies the period in nanoseconds, not the duty cycle. I'll fix this up in the kernel. Thierry [-- Attachment #1.2: Type: application/pgp-signature, Size: 836 bytes --] [-- Attachment #2: Type: text/plain, Size: 134 bytes --] _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ^ permalink raw reply [flat|nested] 10+ messages in thread
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* Re: [PATCH v4 03/16] tegra: fdt: Add pwm binding and node [not found] ` <20120928200817.GB30777-RM9K5IK7kjIQXX3q8xo1gnVAuStQJXxyR5q1nwbD4aMs9pC9oP6+/A@public.gmane.org> @ 2012-10-08 21:22 ` Simon Glass 0 siblings, 0 replies; 10+ messages in thread From: Simon Glass @ 2012-10-08 21:22 UTC (permalink / raw) To: Thierry Reding Cc: U-Boot Mailing List, Devicetree Discuss, Stephen Warren, Jerry Van Baren, Tom Warren Hi Thierry, On Fri, Sep 28, 2012 at 1:08 PM, Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org> wrote: > On Thu, Sep 27, 2012 at 05:44:24PM -0700, Simon Glass wrote: >> This binding will apparently soon be in linux-next. Bring it in now >> since we need to do something, and may as well try to target what >> Linux will have. >> >> Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> >> --- >> Changes in v3: >> - Add new commit for pwm binding and node >> >> arch/arm/dts/tegra20.dtsi | 7 +++++++ >> doc/device-tree-bindings/pwm/tegra20-pwm.txt | 18 ++++++++++++++++++ >> 2 files changed, 25 insertions(+), 0 deletions(-) >> create mode 100644 doc/device-tree-bindings/pwm/tegra20-pwm.txt >> >> diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi >> index d936b1e..3221bc9 100644 >> --- a/arch/arm/dts/tegra20.dtsi >> +++ b/arch/arm/dts/tegra20.dtsi >> @@ -211,4 +211,11 @@ >> compatible = "nvidia,tegra20-nand"; >> reg = <0x70008000 0x100>; >> }; >> + >> + pwm: pwm@7000a000 { >> + compatible = "nvidia,tegra20-pwm"; >> + reg = <0x7000a000 0x100>; >> + #pwm-cells = <2>; >> + }; >> + >> }; >> diff --git a/doc/device-tree-bindings/pwm/tegra20-pwm.txt b/doc/device-tree-bindings/pwm/tegra20-pwm.txt >> new file mode 100644 >> index 0000000..bbbeedb >> --- /dev/null >> +++ b/doc/device-tree-bindings/pwm/tegra20-pwm.txt >> @@ -0,0 +1,18 @@ >> +Tegra SoC PWFM controller >> + >> +Required properties: >> +- compatible: should be one of: >> + - "nvidia,tegra20-pwm" >> + - "nvidia,tegra30-pwm" >> +- reg: physical base address and length of the controller's registers >> +- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The >> + first cell specifies the per-chip index of the PWM to use and the second >> + cell is the duty cycle in nanoseconds. > > This is a mistake in the Linux kernel documentation. The second cell > specifies the period in nanoseconds, not the duty cycle. I'll fix this > up in the kernel. Oh ok, thanks. I will update this patch. Regards, Simon > > Thierry ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 04/16] tegra: fdt: Add LCD definitions for Tegra [not found] ` <1348793077-10126-1-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> 2012-09-28 0:44 ` [PATCH v4 03/16] tegra: fdt: Add pwm binding and node Simon Glass @ 2012-09-28 0:44 ` Simon Glass [not found] ` <1348793077-10126-5-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> 2012-09-28 0:44 ` [PATCH v4 14/16] tegra: fdt: Add LCD definitions for Seaboard Simon Glass 2 siblings, 1 reply; 10+ messages in thread From: Simon Glass @ 2012-09-28 0:44 UTC (permalink / raw) To: U-Boot Mailing List Cc: Stephen Warren, Devicetree Discuss, Jerry Van Baren, Tom Warren Add LCD definitions and also a proposed binding for LCD displays. The PWM is as per what will likely be committed to linux-next soon. The displaymode binding comes from a proposal here: http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html The panel binding is new, and fills a need to specify the panel timings and other tegra-specific information. Should a binding appear that allows the pwm to handle this automatically, we can revisit this. Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> --- Changes in v2: - Add nvidia prefix to device tree properties Changes in v3: - Use displaymode binding for fdt - Bring in proposed tegra display controller binding - Add new panel binding to fit with tegra display controller binding Changes in v4: - Moved panel information into panel node (was in rgb node) - Remove LCD frame buffer address property hack arch/arm/dts/tegra20.dtsi | 89 ++++++++++++++++++++++++ doc/device-tree-bindings/video/displaymode.txt | 42 +++++++++++ doc/device-tree-bindings/video/tegra20-dc.txt | 82 ++++++++++++++++++++++ 3 files changed, 213 insertions(+), 0 deletions(-) create mode 100644 doc/device-tree-bindings/video/displaymode.txt create mode 100644 doc/device-tree-bindings/video/tegra20-dc.txt diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 3221bc9..5fb1fd7 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -218,4 +218,93 @@ #pwm-cells = <2>; }; + host1x { + compatible = "nvidia,tegra20-host1x", "simple-bus"; + reg = <0x50000000 0x00024000>; + interrupts = <0 65 0x04 /* mpcore syncpt */ + 0 67 0x04>; /* mpcore general */ + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + /* video-encoding/decoding */ + mpe { + reg = <0x54040000 0x00040000>; + interrupts = <0 68 0x04>; + }; + + /* video input */ + vi { + reg = <0x54080000 0x00040000>; + interrupts = <0 69 0x04>; + }; + + /* EPP */ + epp { + reg = <0x540c0000 0x00040000>; + interrupts = <0 70 0x04>; + }; + + /* ISP */ + isp { + reg = <0x54100000 0x00040000>; + interrupts = <0 71 0x04>; + }; + + /* 2D engine */ + gr2d { + reg = <0x54140000 0x00040000>; + interrupts = <0 72 0x04>; + }; + + /* 3D engine */ + gr3d { + reg = <0x54180000 0x00040000>; + }; + + /* display controllers */ + dc@54200000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <0 73 0x04>; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <0 74 0x04>; + + rgb { + status = "disabled"; + }; + }; + + /* outputs */ + hdmi { + compatible = "nvidia,tegra20-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <0 75 0x04>; + status = "disabled"; + }; + + tvo { + compatible = "nvidia,tegra20-tvo"; + reg = <0x542c0000 0x00040000>; + interrupts = <0 76 0x04>; + status = "disabled"; + }; + + dsi { + compatible = "nvidia,tegra20-dsi"; + reg = <0x54300000 0x00040000>; + status = "disabled"; + }; + }; + }; diff --git a/doc/device-tree-bindings/video/displaymode.txt b/doc/device-tree-bindings/video/displaymode.txt new file mode 100644 index 0000000..45ca42d --- /dev/null +++ b/doc/device-tree-bindings/video/displaymode.txt @@ -0,0 +1,42 @@ +videomode bindings +================== + +(from http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html) + +Required properties: + - xres, yres: Display resolution + - left-margin, right-margin, hsync-len: Horizontal Display timing + parameters in pixels + - upper-margin, lower-margin, vsync-len: Vertical display timing + parameters in lines + - clock: display clock in Hz + +Optional properties: + - width-mm, height-mm: Display dimensions in mm + - hsync-active-high (bool): Hsync pulse is active high + - vsync-active-high (bool): Vsync pulse is active high + - interlaced (bool): This is an interlaced mode + - doublescan (bool): This is a doublescan mode + +There are different ways of describing a display mode. The devicetree +representation corresponds to the one used by the Linux Framebuffer +framework described here in Documentation/fb/framebuffer.txt. This +representation has been chosen because it's the only format which does +not allow for inconsistent parameters. Unlike the Framebuffer framework +the devicetree has the clock in Hz instead of ps. + +Example: + + display@0 { + /* 1920x1080p24 */ + clock = <52000000>; + xres = <1920>; + yres = <1080>; + left-margin = <25>; + right-margin = <25>; + hsync-len = <25>; + lower-margin = <2>; + upper-margin = <2>; + vsync-len = <2>; + hsync-active-high; + }; diff --git a/doc/device-tree-bindings/video/tegra20-dc.txt b/doc/device-tree-bindings/video/tegra20-dc.txt new file mode 100644 index 0000000..769cb98 --- /dev/null +++ b/doc/device-tree-bindings/video/tegra20-dc.txt @@ -0,0 +1,82 @@ +Display Controller +------------------ + +(there isn't yet a generic binding in Linux, so this describes what is in +U-Boot, and may change based on Linux activity) + +The device node for a display device is as described in the document +"Open Firmware Recommended Practice : Universal Serial Bus" with the +following modifications and additions : + +Required properties : + - compatible : Should be "nvidia,tegra20-dc" + +Required subnode 'rgb' is as follows: + +Required properties (rgb) : + - nvidia,panel : phandle of LCD panel information + + +The panel node describes the panel itself. This has the properties listed in +displaymode.txt as well as: + +Required properties (panel) : + - nvidia,bits-per-pixel: number of bits per pixel (depth) + - nvidia,pwm : pwm to use to set display contrast (see tegra20-pwm.txt) + - nvidia,panel-timings: 4 cells containing required timings in ms: + * delay between panel_vdd-rise and data-rise + * delay between data-rise and backlight_vdd-rise + * delay between backlight_vdd and pwm-rise + * delay between pwm-rise and backlight_en-rise + +Optional GPIO properies all have (phandle, GPIO number, flags): + - nvidia,backlight-enable-gpios: backlight enable GPIO + - nvidia,lvds-shutdown-gpios: LVDS power shutdown GPIO + - nvidia,backlight-vdd-gpios: backlight power GPIO + - nvidia,panel-vdd-gpios: panel power GPIO + +Example: + +host1x { + compatible = "nvidia,tegra20-host1x", "simple-bus"; + reg = <0x50000000 0x00024000>; + interrupts = <0 65 0x04 /* mpcore syncpt */ + 0 67 0x04>; /* mpcore general */ + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + dc@54200000 { + compatible = "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <0 73 0x04>; + + rgb { + status = "okay"; + nvidia,panel = <&lcd_panel>; + }; + }; +}; + +lcd_panel: panel { + /* Seaboard has 1366x768 */ + clock = <70600000>; + xres = <1366>; + yres = <768>; + left-margin = <58>; + right-margin = <58>; + hsync-len = <58>; + lower-margin = <4>; + upper-margin = <4>; + vsync-len = <4>; + hsync-active-high; + nvidia,bits-per-pixel = <16>; + nvidia,pwm = <&pwm 2 0>; + nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */ + nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ + nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ + nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */ + nvidia,panel-timings = <4 203 17 15>; +}; -- 1.7.7.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
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* Re: [PATCH v4 04/16] tegra: fdt: Add LCD definitions for Tegra [not found] ` <1348793077-10126-5-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> @ 2012-10-03 22:54 ` Stephen Warren 2012-10-03 22:58 ` Stephen Warren 1 sibling, 0 replies; 10+ messages in thread From: Stephen Warren @ 2012-10-03 22:54 UTC (permalink / raw) To: Simon Glass Cc: Devicetree Discuss, U-Boot Mailing List, Jerry Van Baren, Stephen Warren, Tom Warren On 09/27/2012 06:44 PM, Simon Glass wrote: > Add LCD definitions and also a proposed binding for LCD displays. > > The PWM is as per what will likely be committed to linux-next soon. > > The displaymode binding comes from a proposal here: > > http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html > > The panel binding is new, and fills a need to specify the panel > timings and other tegra-specific information. Should a binding appear > that allows the pwm to handle this automatically, we can revisit > this. > diff --git a/doc/device-tree-bindings/video/displaymode.txt b/doc/device-tree-bindings/video/displaymode.txt > +Example: > + > + display@0 { That should really be "mode" or "timing", since it's describing a display mode/timing not a display. I believe the latest messages in that thread indicate a similar change will be made to the proposed Linux binding. > diff --git a/doc/device-tree-bindings/video/tegra20-dc.txt b/doc/device-tree-bindings/video/tegra20-dc.txt > +Required properties (rgb) : > + - nvidia,panel : phandle of LCD panel information > + > + > +The panel node describes the panel itself. This has the properties listed in > +displaymode.txt as well as: It should really be a sub-node; like: panel { ... all the panel-specific stuff from this binding ... modes { default { ... all the stuff from displaymode.txt ... }; }; }; Since the panel itself and the (potentially, list of) modes it can support are separate things. ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 04/16] tegra: fdt: Add LCD definitions for Tegra [not found] ` <1348793077-10126-5-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> 2012-10-03 22:54 ` Stephen Warren @ 2012-10-03 22:58 ` Stephen Warren [not found] ` <506CC301.6050508-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 1 sibling, 1 reply; 10+ messages in thread From: Stephen Warren @ 2012-10-03 22:58 UTC (permalink / raw) To: Simon Glass Cc: Devicetree Discuss, U-Boot Mailing List, Jerry Van Baren, Stephen Warren, Tom Warren On 09/27/2012 06:44 PM, Simon Glass wrote: > Add LCD definitions and also a proposed binding for LCD displays. > > The PWM is as per what will likely be committed to linux-next soon. > > The displaymode binding comes from a proposal here: > > http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html > > The panel binding is new, and fills a need to specify the panel > timings and other tegra-specific information. Should a binding appear > that allows the pwm to handle this automatically, we can revisit > this. > diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi > + host1x { > + compatible = "nvidia,tegra20-host1x", "simple-bus"; > + reg = <0x50000000 0x00024000>; > + interrupts = <0 65 0x04 /* mpcore syncpt */ > + 0 67 0x04>; /* mpcore general */ > + > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0x54000000 0x54000000 0x04000000>; > + > + /* video-encoding/decoding */ > + mpe { > + reg = <0x54040000 0x00040000>; > + interrupts = <0 68 0x04>; > + }; Shouldn't all of these nodes have status="disabled", since in general boards will want to opt-in to these modules. In fact, many of these nodes won't end up (ever?) being used in U-Boot; perhaps we should only add the nodes we care about. > + /* display controllers */ > + dc@54200000 { > + compatible = "nvidia,tegra20-dc"; > + reg = <0x54200000 0x00040000>; > + interrupts = <0 73 0x04>; > + > + rgb { > + status = "disabled"; > + }; > + }; I think we definitely want status="disabled" in the dc nodes themselves, since we definitely want boards in U-Boot to control whether to enable the dc. ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <506CC301.6050508-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]
* Re: [PATCH v4 04/16] tegra: fdt: Add LCD definitions for Tegra [not found] ` <506CC301.6050508-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> @ 2012-10-08 20:01 ` Simon Glass 0 siblings, 0 replies; 10+ messages in thread From: Simon Glass @ 2012-10-08 20:01 UTC (permalink / raw) To: Stephen Warren Cc: Devicetree Discuss, U-Boot Mailing List, Jerry Van Baren, Stephen Warren, Tom Warren Hi Stephen, On Wed, Oct 3, 2012 at 3:58 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: > On 09/27/2012 06:44 PM, Simon Glass wrote: >> Add LCD definitions and also a proposed binding for LCD displays. >> >> The PWM is as per what will likely be committed to linux-next soon. >> >> The displaymode binding comes from a proposal here: >> >> http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html >> >> The panel binding is new, and fills a need to specify the panel >> timings and other tegra-specific information. Should a binding appear >> that allows the pwm to handle this automatically, we can revisit >> this. > >> diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi > >> + host1x { >> + compatible = "nvidia,tegra20-host1x", "simple-bus"; >> + reg = <0x50000000 0x00024000>; >> + interrupts = <0 65 0x04 /* mpcore syncpt */ >> + 0 67 0x04>; /* mpcore general */ >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + ranges = <0x54000000 0x54000000 0x04000000>; >> + >> + /* video-encoding/decoding */ >> + mpe { >> + reg = <0x54040000 0x00040000>; >> + interrupts = <0 68 0x04>; >> + }; > > Shouldn't all of these nodes have status="disabled", since in general > boards will want to opt-in to these modules. In fact, many of these > nodes won't end up (ever?) being used in U-Boot; perhaps we should only > add the nodes we care about. > >> + /* display controllers */ >> + dc@54200000 { >> + compatible = "nvidia,tegra20-dc"; >> + reg = <0x54200000 0x00040000>; >> + interrupts = <0 73 0x04>; >> + >> + rgb { >> + status = "disabled"; >> + }; >> + }; > > I think we definitely want status="disabled" in the dc nodes themselves, > since we definitely want boards in U-Boot to control whether to enable > the dc. > OK I will update these, thanks. Regards, Simon ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 14/16] tegra: fdt: Add LCD definitions for Seaboard [not found] ` <1348793077-10126-1-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> 2012-09-28 0:44 ` [PATCH v4 03/16] tegra: fdt: Add pwm binding and node Simon Glass 2012-09-28 0:44 ` [PATCH v4 04/16] tegra: fdt: Add LCD definitions for Tegra Simon Glass @ 2012-09-28 0:44 ` Simon Glass [not found] ` <1348793077-10126-15-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> 2 siblings, 1 reply; 10+ messages in thread From: Simon Glass @ 2012-09-28 0:44 UTC (permalink / raw) To: U-Boot Mailing List Cc: Stephen Warren, Devicetree Discuss, Jerry Van Baren, Tom Warren The Seaboard has a 1366x768 16bpp LCD. The backlight is controlled by one of the PWMs. Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> --- Changes in v2: - Update seaboard LCD definitions for new fdt binding Changes in v3: - Use new upstream proposed LCD definitions Changes in v4: - Adjust LCD fdt nodes for new binding - Remove LCD frame buffer address property hack board/nvidia/dts/tegra20-seaboard.dts | 31 +++++++++++++++++++++++++++++++ 1 files changed, 31 insertions(+), 0 deletions(-) diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts index 25a63a0..df730f5 100644 --- a/board/nvidia/dts/tegra20-seaboard.dts +++ b/board/nvidia/dts/tegra20-seaboard.dts @@ -163,4 +163,35 @@ compatible = "hynix,hy27uf4g2b", "nand-flash"; }; }; + + host1x { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&lcd_panel>; + }; + }; + }; + + lcd_panel: panel { + /* Seaboard has 1366x768 */ + clock = <70600000>; + xres = <1366>; + yres = <768>; + left-margin = <58>; + right-margin = <58>; + hsync-len = <58>; + lower-margin = <4>; + upper-margin = <4>; + vsync-len = <4>; + hsync-active-high; + nvidia,bits-per-pixel = <16>; + nvidia,pwm = <&pwm 2 0>; + nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */ + nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ + nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ + nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */ + nvidia,panel-timings = <4 203 17 15>; + }; + }; -- 1.7.7.3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
[parent not found: <1348793077-10126-15-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>]
* Re: [PATCH v4 14/16] tegra: fdt: Add LCD definitions for Seaboard [not found] ` <1348793077-10126-15-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> @ 2012-10-03 22:58 ` Stephen Warren [not found] ` <506CC327.2070609-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Stephen Warren @ 2012-10-03 22:58 UTC (permalink / raw) To: Simon Glass Cc: Devicetree Discuss, U-Boot Mailing List, Jerry Van Baren, Stephen Warren, Tom Warren On 09/27/2012 06:44 PM, Simon Glass wrote: > The Seaboard has a 1366x768 16bpp LCD. The backlight is controlled > by one of the PWMs. > diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts > + host1x { > + dc@54200000 { So based on my previous comment, I think you want status="okay" at this level too, perhaps even at the host1x level. > + rgb { > + status = "okay"; > + nvidia,panel = <&lcd_panel>; > + }; > + }; > + }; ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <506CC327.2070609-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]
* Re: [PATCH v4 14/16] tegra: fdt: Add LCD definitions for Seaboard [not found] ` <506CC327.2070609-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> @ 2012-10-08 20:06 ` Simon Glass 0 siblings, 0 replies; 10+ messages in thread From: Simon Glass @ 2012-10-08 20:06 UTC (permalink / raw) To: Stephen Warren Cc: Devicetree Discuss, U-Boot Mailing List, Jerry Van Baren, Stephen Warren, Tom Warren Hi Stephen, On Wed, Oct 3, 2012 at 3:58 PM, Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote: > On 09/27/2012 06:44 PM, Simon Glass wrote: >> The Seaboard has a 1366x768 16bpp LCD. The backlight is controlled >> by one of the PWMs. > >> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts > >> + host1x { >> + dc@54200000 { > > So based on my previous comment, I think you want status="okay" at this > level too, perhaps even at the host1x level. Yes I will do this. > >> + rgb { >> + status = "okay"; >> + nvidia,panel = <&lcd_panel>; >> + }; >> + }; >> + }; > Regards, Simon ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2012-10-08 21:22 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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[not found] ` <1348793077-10126-1-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2012-09-28 0:44 ` [PATCH v4 03/16] tegra: fdt: Add pwm binding and node Simon Glass
2012-09-28 20:08 ` Thierry Reding
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2012-10-08 21:22 ` Simon Glass
2012-09-28 0:44 ` [PATCH v4 04/16] tegra: fdt: Add LCD definitions for Tegra Simon Glass
[not found] ` <1348793077-10126-5-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2012-10-03 22:54 ` Stephen Warren
2012-10-03 22:58 ` Stephen Warren
[not found] ` <506CC301.6050508-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-08 20:01 ` Simon Glass
2012-09-28 0:44 ` [PATCH v4 14/16] tegra: fdt: Add LCD definitions for Seaboard Simon Glass
[not found] ` <1348793077-10126-15-git-send-email-sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2012-10-03 22:58 ` Stephen Warren
[not found] ` <506CC327.2070609-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-08 20:06 ` Simon Glass
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