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Wed, 24 Sep 2025 10:05:57 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: A0nVfrWCY5as Date: Wed, 24 Sep 2025 16:05:26 +0200 From: "Arnd Bergmann" To: "Manikanta Guntupalli" , "git (AMD-Xilinx)" , "Michal Simek" , "Alexandre Belloni" , "Frank Li" , "Rob Herring" , "krzk+dt@kernel.org" , "Conor Dooley" , =?UTF-8?Q?Przemys=C5=82aw_Gaj?= , "Wolfram Sang" , "tommaso.merciai.xr@bp.renesas.com" , "quic_msavaliy@quicinc.com" , "S-k, Shyam-sundar" , "Sakari Ailus" , "'billy_tsai@aspeedtech.com'" , "Kees Cook" , "Gustavo A. R. Silva" , "Jarkko Nikula" , "Jorge Marques" , "linux-i3c@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Linux-Arch , "linux-hardening@vger.kernel.org" Cc: "Pandey, Radhey Shyam" , "Goud, Srinivas" , "Datta, Shubhrajyoti" , "manion05gk@gmail.com" Message-Id: <134c3a96-4023-47ab-8aa9-fd6ab75e5654@app.fastmail.com> In-Reply-To: References: <20250923154551.2112388-1-manikanta.guntupalli@amd.com> <20250923154551.2112388-4-manikanta.guntupalli@amd.com> <13bbd85e-48d2-4163-b9f1-2a2a870d4322@app.fastmail.com> <4199b1ca-c1c7-41ef-b053-415f0cd80468@app.fastmail.com> Subject: Re: [PATCH V7 3/4] i3c: master: Add endianness support for i3c_readl_fifo() and i3c_writel_fifo() Content-Type: text/plain Content-Transfer-Encoding: 7bit On Wed, Sep 24, 2025, at 14:22, Guntupalli, Manikanta wrote: >> @@ -55,7 +55,7 @@ static inline void i3c_readl_fifo(const void __iomem *addr, void >> *buf, >> if (nbytes & 3) { >> u32 tmp; >> >> - tmp = readl(addr); >> + readsl(addr, &tmp, 1); >> memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3); >> } >> } > > We have not observed any issue on little-endian systems in our testing > so far (as I mentioned earlier in asm-generic/io.h: Add big-endian MMIO > accessors). Did you test the little-endian system with the 'endian' flag set to I3C_FIFO_BIG_ENDIAN though? Your v7 code will still work on little-endian kernels if that flag is set to I3C_FIFO_LITTLE_ENDIAN, and it will also work on big-endian kernels if the flag is set to I3C_FIFO_BIG_ENDIAN. But is broken for the other two: - on little-endian kernels with I3C_FIFO_BIG_ENDIAN, the entire data buffer is byteswapped in 32-bit chunks - on big-endian kernels with I3C_FIFO_LITTLE_ENDIAN, you run into the existing bug of the swapped tail word. > That said, I understand your point about FIFO semantics being different > from fixed-endian registers. To cover both cases, we considered using > writesl() for little-endian and introducing a writesl_be() helper for > big-endian, as shown below: > > static inline void i3c_writel_fifo(void __iomem *addr, const void *buf, > int nbytes, enum i3c_fifo_endian endian) > { > if (endian) > writesl_be(addr, buf, nbytes / 4); > else > writesl(addr, buf, nbytes / 4); > > if (nbytes & 3) { > u32 tmp = 0; > > memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3); > > if (endian) > writesl_be(addr, &tmp, 1); > else > writesl(addr, &tmp, 1); > } > } > > With this approach, both little-endian and big-endian cases works as expected. This version should fix the cases where you have a big-endian kernel with either I3C_FIFO_BIG_ENDIAN or I3C_FIFO_LITTLE_ENDIAN, as neither combination does any byte swaps. However I'm fairly sure it's still broken for little-endian kernels when a driver asks for a I3C_FIFO_BIG_ENDIAN conversion, same as v7. Arnd