From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gregory CLEMENT Subject: [PATCH 1/6] arm: mvebu: Add support for local interrupt Date: Mon, 21 Jan 2013 18:53:57 +0100 Message-ID: <1358790842-2986-2-git-send-email-gregory.clement@free-electrons.com> References: <1358790842-2986-1-git-send-email-gregory.clement@free-electrons.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1358790842-2986-1-git-send-email-gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: "devicetree-discuss" To: Jason Cooper , Andrew Lunn , Gregory Clement , Grant Likely , Rob Herring , John Stultz , Thomas Gleixner , Russell King Cc: Lior Amsalem , Ike Pan , Nadav Haklai , David Marlin , Yehuda Yitschak , Jani Monoses , Tawfik Bayouk , Dan Frazier , Eran Ben-Avi , Leif Lindholm , Sebastian Hesselbarth , Jon Masters , devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Chris Van Hoof , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Maen Suleiman , Shadi Ammouri List-Id: devicetree@vger.kernel.org MPIC allows the use of private interrupt for each CPUs. The 28th first interrupts are per-cpu. This patch adds support to use them. Signed-off-by: Gregory CLEMENT --- arch/arm/mach-mvebu/irq-armada-370-xp.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c index f99a4a2..c007fdc 100644 --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -145,11 +145,19 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, { armada_370_xp_irq_mask(irq_get_irq_data(virq)); writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); - - irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, - handle_level_irq); irq_set_status_flags(virq, IRQ_LEVEL); - set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); + + if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { + + irq_set_percpu_devid(virq); + irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, + handle_percpu_devid_irq); + + } else { + irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, + handle_level_irq); + } + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); return 0; } @@ -245,7 +253,7 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs if (irqnr > 1022) break; - if (irqnr >= 8) { + if (irqnr > 0) { irqnr = irq_find_mapping(armada_370_xp_mpic_domain, irqnr); handle_IRQ(irqnr, regs); -- 1.7.9.5