From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EBBDC56202 for ; Thu, 26 Nov 2020 16:03:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD30D221E2 for ; Thu, 26 Nov 2020 16:03:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391243AbgKZQD4 (ORCPT ); Thu, 26 Nov 2020 11:03:56 -0500 Received: from foss.arm.com ([217.140.110.172]:38108 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391161AbgKZQD4 (ORCPT ); Thu, 26 Nov 2020 11:03:56 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3DFA631B; Thu, 26 Nov 2020 08:03:55 -0800 (PST) Received: from [10.57.59.159] (unknown [10.57.59.159]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 67D063F23F; Thu, 26 Nov 2020 08:03:50 -0800 (PST) Subject: Re: [PATCH v4 09/24] iommu/io-pgtable-arm-v7s: Clear LVL_SHIFT/BITS macro instead of the formula To: Yong Wu , Joerg Roedel , Matthias Brugger , Rob Herring , Will Deacon Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, kernel-team@android.com, linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , anan.sun@mediatek.com, Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org References: <20201111123838.15682-1-yong.wu@mediatek.com> <20201111123838.15682-10-yong.wu@mediatek.com> From: Robin Murphy Message-ID: <13599074-25d5-721f-ea7b-1ea6badfd14f@arm.com> Date: Thu, 26 Nov 2020 16:03:49 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <20201111123838.15682-10-yong.wu@mediatek.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2020-11-11 12:38, Yong Wu wrote: > The current _ARM_V7S_LVL_BITS/ARM_V7S_LVL_SHIFT use a formula to calculate > the corresponding value for level1 and level2 to pretend the code sane. > Actually their level1 and level2 values are different from each other. > This patch only clear the two macro. No functional change. Grammar nit: to "clear" the macro sounds like you're making it empty or removing it entirely; I think you mean to say "clarify" here. English is the worst language sometimes... :) Reviewed-by: Robin Murphy > Suggested-by: Robin Murphy > Signed-off-by: Yong Wu > --- > drivers/iommu/io-pgtable-arm-v7s.c | 8 +++----- > 1 file changed, 3 insertions(+), 5 deletions(-) > > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > index 4d0aa079470f..58cc201c10a3 100644 > --- a/drivers/iommu/io-pgtable-arm-v7s.c > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > @@ -44,13 +44,11 @@ > > /* > * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2, > - * and 12 bits in a page. With some carefully-chosen coefficients we can > - * hide the ugly inconsistencies behind these macros and at least let the > - * rest of the code pretend to be somewhat sane. > + * and 12 bits in a page. > */ > #define ARM_V7S_ADDR_BITS 32 > -#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4) > -#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl))) > +#define _ARM_V7S_LVL_BITS(lvl) ((lvl) == 1 ? 12 : 8) > +#define ARM_V7S_LVL_SHIFT(lvl) ((lvl) == 1 ? 20 : 12) > #define ARM_V7S_TABLE_SHIFT 10 > > #define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl)) >