From: Christophe Leroy <christophe.leroy@csgroup.eu>
To: Herve Codina <herve.codina@bootlin.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Andrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Lee Jones <lee@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
Takashi Iwai <tiwai@suse.com>,
Shengjiu Wang <shengjiu.wang@gmail.com>,
Xiubo Li <Xiubo.Lee@gmail.com>,
Fabio Estevam <festevam@gmail.com>,
Nicolin Chen <nicoleotsuka@gmail.com>,
Christophe Leroy <christophe.leroy@csgroup.eu>,
Randy Dunlap <rdunlap@infradead.org>
Cc: netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
alsa-devel@alsa-project.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: [PATCH v4 20/28] wan: qmc_hdlc: Add runtime timeslots changes support
Date: Fri, 18 Aug 2023 18:39:14 +0200 [thread overview]
Message-ID: <1364a0742fc76e7d275273dbbc4c97b008ec70a5.1692376361.git.christophe.leroy@csgroup.eu> (raw)
In-Reply-To: <cover.1692376360.git.christophe.leroy@csgroup.eu>
From: Herve Codina <herve.codina@bootlin.com>
QMC channels support runtime timeslots changes but nothing is done at
the QMC HDLC driver to handle these changes.
Use existing IFACE ioctl in order to configure the timeslots to use.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
drivers/net/wan/fsl_qmc_hdlc.c | 169 ++++++++++++++++++++++++++++++++-
1 file changed, 168 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wan/fsl_qmc_hdlc.c b/drivers/net/wan/fsl_qmc_hdlc.c
index 4f84ac5fc63e..4b8cb5761fd1 100644
--- a/drivers/net/wan/fsl_qmc_hdlc.c
+++ b/drivers/net/wan/fsl_qmc_hdlc.c
@@ -32,6 +32,7 @@ struct qmc_hdlc {
struct qmc_hdlc_desc tx_descs[8];
unsigned int tx_out;
struct qmc_hdlc_desc rx_descs[4];
+ u32 slot_map;
};
static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
@@ -202,6 +203,162 @@ static netdev_tx_t qmc_hdlc_xmit(struct sk_buff *skb, struct net_device *netdev)
return NETDEV_TX_OK;
}
+static int qmc_hdlc_xlate_slot_map(struct qmc_hdlc *qmc_hdlc,
+ u32 slot_map, struct qmc_chan_ts_info *ts_info)
+{
+ u64 ts_mask_avail;
+ unsigned int bit;
+ unsigned int i;
+ u64 ts_mask;
+ u64 map = 0;
+
+ /* Tx and Rx masks must be identical */
+ if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
+ dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch (0x%llx, 0x%llx)\n",
+ ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
+ return -EINVAL;
+ }
+
+ ts_mask_avail = ts_info->rx_ts_mask_avail;
+ ts_mask = 0;
+ map = slot_map;
+ bit = 0;
+ for (i = 0; i < 64; i++) {
+ if (ts_mask_avail & BIT_ULL(i)) {
+ if (map & BIT_ULL(bit))
+ ts_mask |= BIT_ULL(i);
+ bit++;
+ }
+ }
+
+ if (hweight64(ts_mask) != hweight64(map)) {
+ dev_err(qmc_hdlc->dev, "Cannot translate timeslots 0x%llx -> (0x%llx,0x%llx)\n",
+ map, ts_mask_avail, ts_mask);
+ return -EINVAL;
+ }
+
+ ts_info->tx_ts_mask = ts_mask;
+ ts_info->rx_ts_mask = ts_mask;
+ return 0;
+}
+
+static int qmc_hdlc_xlate_ts_info(struct qmc_hdlc *qmc_hdlc,
+ const struct qmc_chan_ts_info *ts_info, u32 *slot_map)
+{
+ u64 ts_mask_avail;
+ unsigned int bit;
+ unsigned int i;
+ u64 ts_mask;
+ u64 map = 0;
+
+ /* Tx and Rx masks must be identical */
+ if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
+ dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch (0x%llx, 0x%llx)\n",
+ ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
+ return -EINVAL;
+ }
+ if (ts_info->rx_ts_mask != ts_info->tx_ts_mask) {
+ dev_err(qmc_hdlc->dev, "tx and rx timeslots mismatch (0x%llx, 0x%llx)\n",
+ ts_info->rx_ts_mask, ts_info->tx_ts_mask);
+ return -EINVAL;
+ }
+
+ ts_mask_avail = ts_info->rx_ts_mask_avail;
+ ts_mask = ts_info->rx_ts_mask;
+ map = 0;
+ bit = 0;
+ for (i = 0; i < 64; i++) {
+ if (ts_mask_avail & BIT_ULL(i)) {
+ if (ts_mask & BIT_ULL(i))
+ map |= BIT_ULL(bit);
+ bit++;
+ }
+ }
+
+ if (hweight64(ts_mask) != hweight64(map)) {
+ dev_err(qmc_hdlc->dev, "Cannot translate timeslots (0x%llx,0x%llx) -> 0x%llx\n",
+ ts_mask_avail, ts_mask, map);
+ return -EINVAL;
+ }
+
+ if (map >= BIT_ULL(32)) {
+ dev_err(qmc_hdlc->dev, "Slot map out of 32bit (0x%llx,0x%llx) -> 0x%llx\n",
+ ts_mask_avail, ts_mask, map);
+ return -EINVAL;
+ }
+
+ *slot_map = map;
+ return 0;
+}
+
+static int qmc_hdlc_set_iface(struct qmc_hdlc *qmc_hdlc, int if_iface, const te1_settings *te1)
+{
+ struct qmc_chan_ts_info ts_info;
+ int ret;
+
+ ret = qmc_chan_get_ts_info(qmc_hdlc->qmc_chan, &ts_info);
+ if (ret) {
+ dev_err(qmc_hdlc->dev, "get QMC channel ts info failed %d\n", ret);
+ return ret;
+ }
+ ret = qmc_hdlc_xlate_slot_map(qmc_hdlc, te1->slot_map, &ts_info);
+ if (ret)
+ return ret;
+
+ ret = qmc_chan_set_ts_info(qmc_hdlc->qmc_chan, &ts_info);
+ if (ret) {
+ dev_err(qmc_hdlc->dev, "set QMC channel ts info failed %d\n", ret);
+ return ret;
+ }
+
+ qmc_hdlc->slot_map = te1->slot_map;
+
+ return 0;
+}
+
+static int qmc_hdlc_ioctl(struct net_device *netdev, struct if_settings *ifs)
+{
+ struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
+ te1_settings te1;
+
+ switch (ifs->type) {
+ case IF_GET_IFACE:
+ ifs->type = IF_IFACE_E1;
+ if (ifs->size < sizeof(te1)) {
+ if (!ifs->size)
+ return 0; /* only type requested */
+
+ ifs->size = sizeof(te1); /* data size wanted */
+ return -ENOBUFS;
+ }
+
+ memset(&te1, 0, sizeof(te1));
+
+ /* Update slot_map */
+ te1.slot_map = qmc_hdlc->slot_map;
+
+ if (copy_to_user(ifs->ifs_ifsu.te1, &te1, sizeof(te1)))
+ return -EFAULT;
+ return 0;
+
+ case IF_IFACE_E1:
+ case IF_IFACE_T1:
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ if (netdev->flags & IFF_UP)
+ return -EBUSY;
+
+ if (copy_from_user(&te1, ifs->ifs_ifsu.te1, sizeof(te1)))
+ return -EFAULT;
+
+ return qmc_hdlc_set_iface(qmc_hdlc, ifs->type, &te1);
+
+ default:
+ return hdlc_ioctl(netdev, ifs);
+ }
+}
+
static int qmc_hdlc_open(struct net_device *netdev)
{
struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
@@ -328,13 +485,14 @@ static const struct net_device_ops qmc_hdlc_netdev_ops = {
.ndo_open = qmc_hdlc_open,
.ndo_stop = qmc_hdlc_close,
.ndo_start_xmit = hdlc_start_xmit,
- .ndo_siocwandev = hdlc_ioctl,
+ .ndo_siocwandev = qmc_hdlc_ioctl,
};
static int qmc_hdlc_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct qmc_hdlc *qmc_hdlc;
+ struct qmc_chan_ts_info ts_info;
struct qmc_chan_info info;
hdlc_device *hdlc;
int ret;
@@ -364,6 +522,15 @@ static int qmc_hdlc_probe(struct platform_device *pdev)
return -EINVAL;
}
+ ret = qmc_chan_get_ts_info(qmc_hdlc->qmc_chan, &ts_info);
+ if (ret) {
+ dev_err(qmc_hdlc->dev, "get QMC channel ts info failed %d\n", ret);
+ return ret;
+ }
+ ret = qmc_hdlc_xlate_ts_info(qmc_hdlc, &ts_info, &qmc_hdlc->slot_map);
+ if (ret)
+ return ret;
+
qmc_hdlc->netdev = alloc_hdlcdev(qmc_hdlc);
if (!qmc_hdlc->netdev) {
dev_err(qmc_hdlc->dev, "failed to alloc hdlc dev\n");
--
2.41.0
next prev parent reply other threads:[~2023-08-18 17:22 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-18 16:38 [PATCH v4 00/28] Add support for QMC HDLC, framer infrastruture and PEF2256 framer (v4) Christophe Leroy
2023-08-18 16:38 ` [PATCH v4 01/28] soc: fsl: cpm1: tsa: Fix __iomem addresses declaration Christophe Leroy
2023-08-18 16:38 ` [PATCH v4 02/28] soc: fsl: cpm1: qmc: " Christophe Leroy
2023-08-18 16:38 ` [PATCH v4 03/28] soc: fsl: cpm1: qmc: Fix rx channel reset Christophe Leroy
2023-08-18 16:38 ` [PATCH v4 04/28] soc: fsl: cpm1: qmc: Extend the API to provide Rx status Christophe Leroy
2023-08-18 16:38 ` [PATCH v4 05/28] soc: fsl: cpm1: qmc: Remove inline function specifiers Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 06/28] dt-bindings: net: Add support for QMC HDLC Christophe Leroy
2023-08-21 20:42 ` Rob Herring
2023-08-24 16:12 ` Herve Codina
2023-08-18 16:39 ` [PATCH v4 07/28] net: wan: " Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 08/28] MAINTAINERS: Add the Freescale QMC HDLC driver entry Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 09/28] soc: fsl: cpm1: qmc: Introduce available timeslots masks Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 10/28] soc: fsl: cpm1: qmc: Rename qmc_setup_tsa* to qmc_init_tsa* Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 11/28] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa* Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 12/28] soc: fsl: cpm1: qmc: Remove no more needed checks from qmc_check_chans() Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 13/28] soc: fsl: cpm1: qmc: Check available timeslots in qmc_check_chans() Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 14/28] soc: fsl: cpm1: qmc: Add support for disabling channel TSA entries Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 15/28] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 16/28] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 17/28] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop() Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 18/28] soc: fsl: cpm1: qmc: Remove timeslots handling from setup_chan() Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 19/28] soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime Christophe Leroy
2023-08-18 16:39 ` Christophe Leroy [this message]
2023-08-21 5:40 ` [PATCH v4 20/28] wan: qmc_hdlc: Add runtime timeslots changes support Christophe JAILLET
2023-08-24 16:32 ` Herve Codina
2023-08-18 16:39 ` [PATCH v4 21/28] net: wan: Add framer framework support Christophe Leroy
2023-08-19 2:46 ` Jakub Kicinski
2023-08-20 17:15 ` Simon Horman
2023-08-24 16:44 ` Herve Codina
2023-08-20 21:06 ` Linus Walleij
2023-08-21 5:19 ` Christophe Leroy
2023-08-21 7:21 ` Linus Walleij
2023-08-21 18:52 ` Jakub Kicinski
2023-08-21 6:02 ` Christophe JAILLET
2023-08-24 16:37 ` Herve Codina
2023-08-18 16:39 ` [PATCH v4 22/28] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer Christophe Leroy
2023-08-21 20:49 ` Rob Herring
2023-08-24 16:28 ` Herve Codina
2023-08-18 16:39 ` [PATCH v4 23/28] mfd: core: Ensure disabled devices are skiped without aborting Christophe Leroy
2023-08-21 12:17 ` Lee Jones
2023-09-20 9:34 ` (subset) " Lee Jones
2023-08-18 16:39 ` [PATCH v4 24/28] net: wan: framer: Add support for the Lantiq PEF2256 framer Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 25/28] pinctrl: Add support for the Lantic PEF2256 pinmux Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 26/28] MAINTAINERS: Add the Lantiq PEF2256 driver entry Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 27/28] ASoC: codecs: Add support for the framer codec Christophe Leroy
2023-08-18 23:18 ` Randy Dunlap
2023-08-19 8:57 ` Christophe Leroy
2023-08-18 16:39 ` [PATCH v4 28/28] net: wan: fsl_qmc_hdlc: Add framer support Christophe Leroy
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