From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-arm-kernel@lists.infradead.org,
Grant Likely <grant.likely@secretlab.ca>,
Rob Herring <rob.herring@calxeda.com>,
Rob Landley <rob@landley.net>,
Stephen Warren <swarren@wwwdotorg.org>,
Russell King <linux@arm.linux.org.uk>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Simon Glass <sjg@chromium.org>, Rhyland Klein <rklein@nvidia.com>,
Pritesh Raithatha <praithatha@nvidia.com>,
Linus Walleij <linus.walleij@linaro.org>,
Hiroshi Doyu <hdoyu@nvidia.com>,
Laxman Dewangan <ldewangan@nvidia.com>,
Andrew Chew <achew@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
Thierry Reding <thierry.reding@avionic-design.de>,
devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v9 09/14] clk: tegra: Workaround for Tegra114 MSENC problem
Date: Wed, 3 Apr 2013 17:40:44 +0300 [thread overview]
Message-ID: <1365000110-8916-11-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1365000110-8916-1-git-send-email-pdeschrijver@nvidia.com>
Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-periph-gate.c | 9 +++++++++
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 6dd5332..c9083fb 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -43,6 +43,8 @@ static DEFINE_SPINLOCK(periph_ref_lock);
#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
+#define LVL2_CLK_GATE_OVRE 0x554
+
/* Peripheral gate clock ops */
static int clk_periph_is_enabled(struct clk_hw *hw)
{
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
}
}
+ if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
+ writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+ writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
+ udelay(1);
+ writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+ }
+
spin_unlock_irqrestore(&periph_ref_lock, flags);
return 0;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index fd12b77..fb48f04 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -358,6 +358,7 @@ struct tegra_clk_periph_regs {
* TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
* bus to flush the write operation in apb bus. This flag indicates
* that this peripheral is in apb bus.
+ * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
*/
struct tegra_clk_periph_gate {
u32 magic;
@@ -377,6 +378,7 @@ struct tegra_clk_periph_gate {
#define TEGRA_PERIPH_NO_RESET BIT(0)
#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
#define TEGRA_PERIPH_ON_APB BIT(2)
+#define TEGRA_PERIPH_WAR_1005168 BIT(3)
void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
extern const struct clk_ops tegra_clk_periph_gate_ops;
--
1.7.7.rc0.72.g4b5ea.dirty
next prev parent reply other threads:[~2013-04-03 14:40 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-03 14:40 [PATCH v9 00/14] Tegra114 clockframework Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 01/14] clk: tegra: provide dummy cpu car ops Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 02/14] clk: tegra: Refactor PLL programming code Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 03/14] clk: tegra: Add TEGRA_PLL_BYPASS flag Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 05/14] clk: tegra: Add PLL post divider table Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 07/14] clk: tegra: Add new fields and PLL types for Tegra114 Peter De Schrijver
2013-04-03 14:40 ` Peter De Schrijver [this message]
2013-04-03 14:40 ` [PATCH v9 11/14] clk: tegra: Implement clocks " Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 12/14] clk: tegra: devicetree match for nvidia,tegra114-car Peter De Schrijver
[not found] ` <1365000110-8916-13-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-04-03 18:10 ` [PATCH v9 12/14] clk: tegra: devicetree match for nvidia, tegra114-car Stephen Warren
2013-04-03 14:40 ` [PATCH v9 13/14] ARM: dt: Add references to tegra_car clocks Peter De Schrijver
2013-04-03 14:40 ` Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 14/14] clk: tegra: Remove forced clk_enable of uartd Peter De Schrijver
2013-04-03 17:52 ` [PATCH v9 00/14] Tegra114 clockframework Stephen Warren
[not found] ` <515C6C6E.6060302-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-04-03 18:27 ` Stephen Warren
[not found] ` <515C7495.8060106-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-04-03 23:23 ` Stephen Warren
[not found] ` <515CB9D9.90303-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-04-04 8:20 ` Peter De Schrijver
[not found] ` <20130404082043.GY18519-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2013-04-04 21:20 ` Mike Turquette
[not found] ` <1365000110-8916-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-04-03 14:40 ` [PATCH v9 04/14] clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 06/14] clk: tegra: move from a lock bit idx to a lock mask Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 08/14] clk: tegra: Add flags to tegra_clk_periph() Peter De Schrijver
2013-04-03 14:40 ` [PATCH v9 10/14] ARM: tegra: Define Tegra114 CAR binding Peter De Schrijver
2013-04-03 17:55 ` Stephen Warren
2013-04-04 23:29 ` [PATCH v9 00/14] Tegra114 clockframework Stephen Warren
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