[RFC/PATCH 00/13] Add support for MSM's mmio clocks

[RFC/PATCH 00/13] Add support for MSM's mmio clocks

[Stephen Boyd]

Posting as an RFC because I haven't gone through and generated all 
the data needed yet. This is just a few clocks for now to give a general
idea of where things are headed.

The first 4 patches are generic clock framework patches. They add support
for finding clocks in DT and parsing them generically. They also add support
for setting the rate and the parent at the same time based on patches from
James Hogan's remuxing set_rate series [1].

After that we add MSM clock hardware support and then fill in the DT and
data to actually register clocks. This is sufficient enough to get the UART
going on my msm8960 device.

I'm currently waffling between the DT bindings being more descriptive
versus just using the clocks as numbers method. From what I can tell
nobody is complaining either way so it seems I could put all of
the information I encode in C structs into DT. It would be great
if more experienced DT persons could weigh in here.

Please note this patchset relies on my previous patch series that moves
existing MSM clock code to the common clock framework [2].

Stephen Boyd (13):
  clk: fixed-rate: Export clk_fixed_rate_register()
  clk: Add of_init_clk_data() to parse common clock bindings
  clk: Add of_clk_match() for device drivers
  clk: Add set_rate_and_parent() op
  clk: msm: Add support for phase locked loops (PLLs)
  clk: msm: Add support for root clock generators (RCGs)
  clk: msm: Add support for branches/gate clocks
  clk: msm: Add MSM clock driver
  clk: msm: Add support for MSM8960's global clock controller (GCC)
  clk: msm: Add support for MSM8960's multimedia clock controller (MMCC)
  ARM: dts: msm: Add MSM8960 GCC DT nodes
  ARM: dts: msm: Add MSM8960 MMCC DT nodes
  ARM: dts: msm: Add clock entries for MSM8960 uart device

 Documentation/clk.txt                              |   3 +
 Documentation/devicetree/bindings/clock/msm.txt    |  99 +++
 .../devicetree/bindings/clock/qcom,gcc.txt         |  55 ++
 .../devicetree/bindings/clock/qcom,mmcc.txt        |  38 ++
 arch/arm/boot/dts/msm8960-cdp.dts                  | 111 +++
 drivers/clk/Kconfig                                |   2 +
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-fixed-rate.c                       |   1 +
 drivers/clk/clk.c                                  | 201 +++++-
 drivers/clk/msm/Kconfig                            |  22 +
 drivers/clk/msm/Makefile                           |  11 +
 drivers/clk/msm/clk-branch.c                       | 190 ++++++
 drivers/clk/msm/clk-branch.h                       |  48 ++
 drivers/clk/msm/clk-pll.c                          | 233 +++++++
 drivers/clk/msm/clk-pll.h                          |  43 ++
 drivers/clk/msm/clk-rcg.c                          | 754 +++++++++++++++++++++
 drivers/clk/msm/clk-rcg.h                          | 114 ++++
 drivers/clk/msm/clk-rcg2.c                         | 320 +++++++++
 drivers/clk/msm/core.c                             | 271 ++++++++
 drivers/clk/msm/gcc-8960.c                         | 174 +++++
 drivers/clk/msm/internal.h                         |  27 +
 drivers/clk/msm/mmcc-8960.c                        | 142 ++++
 include/linux/clk-provider.h                       |  28 +
 23 files changed, 2868 insertions(+), 20 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/msm.txt
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,mmcc.txt
 create mode 100644 drivers/clk/msm/Kconfig
 create mode 100644 drivers/clk/msm/Makefile
 create mode 100644 drivers/clk/msm/clk-branch.c
 create mode 100644 drivers/clk/msm/clk-branch.h
 create mode 100644 drivers/clk/msm/clk-pll.c
 create mode 100644 drivers/clk/msm/clk-pll.h
 create mode 100644 drivers/clk/msm/clk-rcg.c
 create mode 100644 drivers/clk/msm/clk-rcg.h
 create mode 100644 drivers/clk/msm/clk-rcg2.c
 create mode 100644 drivers/clk/msm/core.c
 create mode 100644 drivers/clk/msm/gcc-8960.c
 create mode 100644 drivers/clk/msm/internal.h
 create mode 100644 drivers/clk/msm/mmcc-8960.c

[1] <1369056507-32521-1-git-send-email-james.hogan@imgtec.com>
[2] 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[RFC/PATCH 05/13] clk: msm: Add support for phase locked loops (PLLs)

[Stephen Boyd]

Add support for MSM's PLLs (phase locked loops). This is
sufficient enough to be able to determine the rate the PLL is
running at.

Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 Documentation/devicetree/bindings/clock/msm.txt |  40 ++++
 drivers/clk/Kconfig                             |   2 +
 drivers/clk/Makefile                            |   1 +
 drivers/clk/msm/Kconfig                         |   4 +
 drivers/clk/msm/Makefile                        |   3 +
 drivers/clk/msm/clk-pll.c                       | 233 ++++++++++++++++++++++++
 drivers/clk/msm/clk-pll.h                       |  43 +++++
 7 files changed, 326 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/msm.txt
 create mode 100644 drivers/clk/msm/Kconfig
 create mode 100644 drivers/clk/msm/Makefile
 create mode 100644 drivers/clk/msm/clk-pll.c
 create mode 100644 drivers/clk/msm/clk-pll.h

diff --git a/Documentation/devicetree/bindings/clock/msm.txt b/Documentation/devicetree/bindings/clock/msm.txt
new file mode 100644
index 0000000..2192621
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/msm.txt
@@ -0,0 +1,40 @@
+Bindings for Qualcomm's clock controllers
+
+These bindings use the common clock binding
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+PLL Binding
+-----------
+
+Required properties:
+- compatible : shall be "qcom,pll".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : from common clock binding; shall be set to the reference clock
+
+Example:
+	pll8: pll8 {
+		#clock-cells = <0>;
+		compatible = "qcom,pll";
+		clocks = <&pxo>;
+	};
+
+Voteable PLL Binding
+--------------------
+
+Voteable PLLs are PLLs surrounded by a voting wrapper that aggregates
+votes from multiple masters in the system and enables or disables the
+PLL according to the current vote.
+
+Required properties:
+- compatible: shall be "qcom,pll-vote"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : from common clock binding; shall be set to the pll that is wrapped
+  in voting logic
+
+Example:
+	vpll8: vpll8 {
+		#clock-cells = <0>;
+		compatible = "qcom,pll-vote";
+		clocks = <&pll8>;
+	};
+
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 0357ac4..acdb826 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -81,6 +81,8 @@ config COMMON_CLK_AXI_CLKGEN
 	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
 	  FPGAs. It is commonly used in Analog Devices' reference designs.
 
+source "drivers/clk/msm/Kconfig"
+
 endmenu
 
 source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 137d3e7..c9e768b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
 obj-$(CONFIG_ARCH_PRIMA2)	+= clk-prima2.o
+obj-$(CONFIG_COMMON_CLK_MSM)	+= msm/
 obj-$(CONFIG_PLAT_ORION)	+= mvebu/
 ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP)		+= mmp/
diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig
new file mode 100644
index 0000000..bf7e3d2
--- /dev/null
+++ b/drivers/clk/msm/Kconfig
@@ -0,0 +1,4 @@
+menuconfig COMMON_CLK_MSM
+	tristate "Support for Qualcomm's MSM designs"
+	depends on OF
+
diff --git a/drivers/clk/msm/Makefile b/drivers/clk/msm/Makefile
new file mode 100644
index 0000000..16b750f
--- /dev/null
+++ b/drivers/clk/msm/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_COMMON_CLK_MSM) += clk-msm.o
+
+clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-pll.o
diff --git a/drivers/clk/msm/clk-pll.c b/drivers/clk/msm/clk-pll.c
new file mode 100644
index 0000000..03c2c41
--- /dev/null
+++ b/drivers/clk/msm/clk-pll.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+
+#include <asm/div64.h>
+
+#include "clk-pll.h"
+
+/**
+ * struct clk_pll - phase locked loop (PLL)
+ * @l_reg: L register
+ * @m_reg: M register
+ * @n_reg: N register
+ * @config_reg: config register
+ * @mode_reg: mode register
+ * @status_reg: status register
+ * @status_bit: ANDed with @status_reg to determine if PLL is enabled
+ * @hw: handle between common and hardware-specific interfaces
+ */
+struct clk_pll {
+	void __iomem *l_reg;
+	void __iomem *m_reg;
+	void __iomem *n_reg;
+	void __iomem *config_reg;
+	void __iomem *mode_reg;
+	void __iomem *status_reg;
+	u8 status_bit;
+
+	struct clk_hw	hw;
+};
+
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
+
+#define PLL_OUTCTRL	BIT(0)
+#define PLL_BYPASSNL	BIT(1)
+#define PLL_RESET_N	BIT(2)
+
+static int clk_pll_enable(struct clk_hw *hw)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	u32 mode;
+
+	mode = readl_relaxed(pll->mode_reg);
+	/* Disable PLL bypass mode. */
+	mode |= PLL_BYPASSNL;
+	writel(mode, pll->mode_reg);
+
+	/*
+	 * H/W requires a 5us delay between disabling the bypass and
+	 * de-asserting the reset. Delay 10us just to be safe.
+	 */
+	udelay(10);
+
+	/* De-assert active-low PLL reset. */
+	mode |= PLL_RESET_N;
+	writel(mode, pll->mode_reg);
+
+	/* Wait until PLL is locked. */
+	udelay(50);
+
+	/* Enable PLL output. */
+	mode |= PLL_OUTCTRL;
+	writel(mode, pll->mode_reg);
+
+	return 0;
+}
+
+static void clk_pll_disable(struct clk_hw *hw)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	u32 mode;
+
+	mode = readl_relaxed(pll->mode_reg);
+	mode &= ~(PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL);
+	writel_relaxed(mode, pll->mode_reg);
+}
+
+static unsigned long
+clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	u32 l, m, n;
+	unsigned long rate;
+	u64 tmp;
+
+	l = readl_relaxed(pll->l_reg) & 0x3ff;
+	m = readl_relaxed(pll->m_reg) & 0x7ffff;
+	n = readl_relaxed(pll->n_reg) & 0x7ffff;
+
+	rate = parent_rate * l;
+	if (n) {
+		tmp = parent_rate;
+		tmp *= m;
+		do_div(tmp, n);
+		rate += tmp;
+	}
+	return rate;
+}
+
+static const struct clk_ops clk_pll_ops = {
+	.enable = clk_pll_enable,
+	.disable = clk_pll_disable,
+	.recalc_rate = clk_pll_recalc_rate,
+};
+
+struct clk *pll_clk_register(struct device *dev, struct pll_desc *desc,
+		struct clk_init_data *init)
+{
+	struct clk_pll *p;
+
+	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
+	if (!p)
+		return ERR_PTR(-ENOMEM);
+
+	p->l_reg = desc->base + desc->l_reg;
+	p->m_reg = desc->base + desc->m_reg;
+	p->n_reg = desc->base + desc->n_reg;
+	p->config_reg = desc->base + desc->config_reg;
+	p->mode_reg = desc->base + desc->mode_reg;
+	p->status_reg = desc->base + desc->status_reg;
+	p->status_bit = desc->status_bit;
+
+	init->ops = &clk_pll_ops;
+	p->hw.init = init;
+
+	return devm_clk_register(dev, &p->hw);
+}
+
+/**
+ * struct clk_pll_vote - phase locked loop (PLL) with hardware voting wrapper
+ * @vote_reg: Voting register
+ * @vote_bit: ORed into @vote_reg to enable PLL
+ * @hw: handle between common and hardware-specific interfaces
+ */
+struct clk_pll_vote {
+	void __iomem	*vote_reg;
+	u8		vote_bit;
+	struct clk_hw	hw;
+};
+
+#define to_clk_pll_vote(_hw) container_of(_hw, struct clk_pll_vote, hw)
+
+static DEFINE_SPINLOCK(pll_vote_lock);
+
+static int wait_for_pll(struct clk_pll *pll)
+{
+	int count;
+	const char *name = __clk_get_name(pll->hw.clk);
+
+	/* Wait for pll to enable. */
+	for (count = 200; count > 0; count--) {
+		if (readl_relaxed(pll->status_reg) & BIT(pll->status_bit))
+			return 0;
+		udelay(1);
+	}
+
+	WARN("%s didn't enable after voting for it!\n", name);
+	return -ETIMEDOUT;
+}
+
+static int clk_pll_vote_enable(struct clk_hw *hw)
+{
+	u32 val;
+	unsigned long flags;
+	struct clk_pll_vote *pll = to_clk_pll_vote(hw);
+	struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk)));
+
+	spin_lock_irqsave(&pll_vote_lock, flags);
+
+	val = readl_relaxed(pll->vote_reg);
+	val |= BIT(pll->vote_bit);
+	writel(val, pll->vote_reg);
+
+	spin_unlock_irqrestore(&pll_vote_lock, flags);
+
+	return wait_for_pll(p);
+}
+
+static void clk_pll_vote_disable(struct clk_hw *hw)
+{
+	u32 val;
+	unsigned long flags;
+	struct clk_pll_vote *pll = to_clk_pll_vote(hw);
+
+	spin_lock_irqsave(&pll_vote_lock, flags);
+
+	val = readl_relaxed(pll->vote_reg);
+	val &= ~BIT(pll->vote_bit);
+	writel_relaxed(val, pll->vote_reg);
+
+	spin_unlock_irqrestore(&pll_vote_lock, flags);
+}
+
+static const struct clk_ops clk_pll_vote_ops = {
+	.enable = clk_pll_vote_enable,
+	.disable = clk_pll_vote_disable,
+};
+
+struct clk *pll_vote_clk_register(struct device *dev,
+		struct pll_vote_desc *desc, struct clk_init_data *init)
+{
+	struct clk_pll_vote *p;
+
+	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
+	if (!p)
+		return ERR_PTR(-ENOMEM);
+
+	p->vote_reg = desc->base + desc->vote_reg;
+	p->vote_bit = desc->vote_bit;
+
+	init->ops = &clk_pll_vote_ops;
+	p->hw.init = init;
+
+	return devm_clk_register(dev, &p->hw);
+}
diff --git a/drivers/clk/msm/clk-pll.h b/drivers/clk/msm/clk-pll.h
new file mode 100644
index 0000000..4e63a5e
--- /dev/null
+++ b/drivers/clk/msm/clk-pll.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MSM_CLK_PLL_H__
+#define __MSM_CLK_PLL_H__
+
+struct device;
+struct clk;
+struct clk_init_data;
+
+struct pll_desc {
+	void __iomem *base;
+	u16 l_reg;
+	u16 m_reg;
+	u16 n_reg;
+	u16 config_reg;
+	u16 mode_reg;
+	u16 status_reg;
+	u8 status_bit;
+};
+
+struct pll_vote_desc {
+	void __iomem *base;
+	u16 vote_reg;
+	u8 vote_bit;
+};
+
+extern struct clk *pll_clk_register(struct device *dev, struct pll_desc *desc,
+		struct clk_init_data *init);
+extern struct clk *pll_vote_clk_register(struct device *dev,
+		struct pll_vote_desc *desc, struct clk_init_data *init);
+
+#endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[RFC/PATCH 06/13] clk: msm: Add support for root clock generators (RCGs)

[Stephen Boyd]

Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 Documentation/devicetree/bindings/clock/msm.txt |  31 +
 drivers/clk/msm/Makefile                        |   2 +
 drivers/clk/msm/clk-rcg.c                       | 754 ++++++++++++++++++++++++
 drivers/clk/msm/clk-rcg.h                       | 114 ++++
 drivers/clk/msm/clk-rcg2.c                      | 320 ++++++++++
 5 files changed, 1221 insertions(+)
 create mode 100644 drivers/clk/msm/clk-rcg.c
 create mode 100644 drivers/clk/msm/clk-rcg.h
 create mode 100644 drivers/clk/msm/clk-rcg2.c

diff --git a/Documentation/devicetree/bindings/clock/msm.txt b/Documentation/devicetree/bindings/clock/msm.txt
index 2192621..f4595fa 100644
--- a/Documentation/devicetree/bindings/clock/msm.txt
+++ b/Documentation/devicetree/bindings/clock/msm.txt
@@ -38,3 +38,34 @@ Example:
 		clocks = <&pll8>;
 	};
 
+M/N:D Binding
+-------------
+
+Required properties:
+- compatible : shall be one of "qcom,p2-mn16-clock" or "qcom,p2-mn8-clock"
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : from common clock binding; shall be set of muxed input sources
+
+Example:
+	gsbi5_uart_rcg: gsbi5_uart_rcg {
+		#clock-cells = <0>;
+		compatible = "qcom,p2-mn16-clock";
+		clocks = <&pxo>, <&pll8>;
+	};
+
+M/N:D Dynamic Binding
+---------------------
+
+Required properties:
+- compatible : shall be one of "qcom,mn4-dyn-clock", "qcom,mn8-dyn-clock" or
+	       "qcom,p4-dyn-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : from common clock binding; shall be set of muxed input sources
+
+Example:
+	gfx2d_rcg : gfx2d_rcg {
+		#clock-cells = <0>;
+		compatible = "qcom,mn4-dyn-clock";
+		clocks = <&pxo>, <&pll2>, <&pll8>;
+	};
+
diff --git a/drivers/clk/msm/Makefile b/drivers/clk/msm/Makefile
index 16b750f..fb78ac9 100644
--- a/drivers/clk/msm/Makefile
+++ b/drivers/clk/msm/Makefile
@@ -1,3 +1,5 @@
 obj-$(CONFIG_COMMON_CLK_MSM) += clk-msm.o
 
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-pll.o
+clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg.o
+clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg2.o
diff --git a/drivers/clk/msm/clk-rcg.c b/drivers/clk/msm/clk-rcg.c
new file mode 100644
index 0000000..3400fee
--- /dev/null
+++ b/drivers/clk/msm/clk-rcg.c
@@ -0,0 +1,754 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+
+#include <asm/div64.h>
+
+#include "clk-rcg.h"
+
+/**
+ * struct mn - M/N:D counter
+ * @mnctr_en_bit: bit to enable mn counter
+ * @mnctr_reset_bit: bit to assert mn counter reset
+ * @mnctr_mode_shift: lowest bit of mn counter mode field
+ * @n_val_shift: lowest bit of n value field
+ * @m_val_shift: lowest bit of m value field
+ * @width: number of bits in m/n/d values
+ */
+struct mn {
+	u8		mnctr_en_bit;
+	u8		mnctr_reset_bit;
+	u8		mnctr_mode_shift;
+#define MNCTR_MODE_DUAL 0x2
+#define MNCTR_MODE_MASK 0x3
+	u8		n_val_shift;
+	u8		m_val_shift;
+	u8		width;
+};
+
+/**
+ * struct pre_div - pre-divider
+ * @pre_div_shift: lowest bit of pre divider field
+ * @pre_div_width: number of bits in predivider
+ */
+struct pre_div {
+	u8		pre_div_shift;
+	u8		pre_div_width;
+};
+
+/**
+ * struct src_sel - source selector
+ * @src_sel_shift: lowest bit of source selection field
+ * @parent_map: map from software's parent index to hardware's src_sel field
+ */
+struct src_sel {
+	u8		src_sel_shift;
+#define SRC_SEL_MASK	0x7
+	u8		*parent_map;
+};
+
+/**
+ * struct clk_rcg - root clock generator
+ *
+ * @ctl_reg: clock control register
+ * @ctl_bit: ORed with @ctl_reg to enable the clock
+ * @ns_reg: NS register
+ * @md_reg: MD register
+ * @mn: mn counter
+ * @p: pre divider
+ * @s: source selector
+ * @freq_tbl: Frequency table
+ * @hw: handle between common and hardware-specific interfaces
+ * @lock: register lock
+ *
+ */
+struct clk_rcg {
+	void __iomem	*ctl_reg;
+	void __iomem	*ns_reg;
+	void __iomem	*md_reg;
+
+	u8		ctl_bit;
+	struct mn	mn;
+	struct pre_div	p;
+	struct src_sel	s;
+
+	const struct freq_tbl	*freq_tbl;
+
+	struct clk_hw	hw;
+	spinlock_t	*lock;
+};
+
+#define to_clk_rcg(_hw) container_of(_hw, struct clk_rcg, hw)
+
+/**
+ * struct clk_dyn_rcg - root clock generator with glitch free mux
+ *
+ * @ctl_reg: clock control register
+ * @ctl_bit: ORed with @ctl_reg to enable the clock
+ * @mux_sel_bit: Bit to switch glitch free mux
+ * @ns_reg: NS register
+ * @md_reg: MD0 and MD1 register
+ * @mn: mn counter (banked)
+ * @s: source selector (banked)
+ * @freq_tbl: Frequency table
+ * @hw: handle between common and hardware-specific interfaces
+ * @lock: register lock
+ *
+ */
+struct clk_dyn_rcg {
+	void __iomem	*ctl_reg;
+	void __iomem	*ns_reg;
+	void __iomem	*md_reg[2];
+
+	u8		ctl_bit;
+	u8		mux_sel_bit;
+	struct mn	mn[2];
+	struct pre_div	p[2];
+	struct src_sel	s[2];
+
+	const struct freq_tbl	*freq_tbl;
+
+	struct clk_hw	hw;
+	spinlock_t	*lock;
+};
+
+#define to_clk_dyn_rcg(_hw) container_of(_hw, struct clk_dyn_rcg, hw)
+
+static int clk_rcg_toggle(void __iomem *ctl_reg, u8 ctl_bit,
+		spinlock_t *lock, bool en)
+{
+	unsigned long flags;
+	u32 val;
+
+	spin_lock_irqsave(lock, flags);
+
+	val = readl_relaxed(ctl_reg);
+	if (en)
+		val |= BIT(ctl_bit);
+	else
+		val &= ~BIT(ctl_bit);
+	writel(val, ctl_reg);
+
+	spin_unlock_irqrestore(lock, flags);
+
+	return 0;
+}
+
+static int clk_rcg_enable(struct clk_hw *hw)
+{
+	struct clk_rcg *rcg = to_clk_rcg(hw);
+
+	return clk_rcg_toggle(rcg->ctl_reg, rcg->ctl_bit, rcg->lock, true);
+}
+
+static void clk_rcg_disable(struct clk_hw *hw)
+{
+	struct clk_rcg *rcg = to_clk_rcg(hw);
+
+	clk_rcg_toggle(rcg->ctl_reg, rcg->ctl_bit, rcg->lock, false);
+}
+
+static int clk_dyn_rcg_enable(struct clk_hw *hw)
+{
+	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
+
+	return clk_rcg_toggle(rcg->ctl_reg, rcg->ctl_bit, rcg->lock, true);
+}
+
+static void clk_dyn_rcg_disable(struct clk_hw *hw)
+{
+	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
+
+	clk_rcg_toggle(rcg->ctl_reg, rcg->ctl_bit, rcg->lock, false);
+}
+
+static int clk_dyn_rcg_is_enabled(struct clk_hw *hw)
+{
+	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
+	u32 val;
+
+	val = readl_relaxed(rcg->ctl_reg);
+	val &= BIT(rcg->ctl_bit);
+
+	return val ? 1 : 0;
+}
+
+static u32 ns_to_src(struct src_sel *s, u32 ns)
+{
+	ns >>= s->src_sel_shift;
+	ns &= SRC_SEL_MASK;
+	return ns;
+}
+
+static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
+{
+	u32 mask;
+
+	mask = SRC_SEL_MASK;
+	mask <<= s->src_sel_shift;
+	ns &= ~mask;
+
+	ns |= src << s->src_sel_shift;
+	return ns;
+}
+
+static u8 clk_rcg_get_parent(struct clk_hw *hw)
+{
+	struct clk_rcg *rcg = to_clk_rcg(hw);
+	int num_parents = __clk_get_num_parents(hw->clk);
+	u32 ns;
+	int i;
+
+	ns = readl_relaxed(rcg->ns_reg);
+	ns = ns_to_src(&rcg->s, ns);
+
+	for (i = 0; i < num_parents; i++)
+		if (ns == rcg->s.parent_map[i])
+			return i;
+
+	return -EINVAL;
+}
+
+static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
+{
+	bank &= BIT(rcg->mux_sel_bit);
+	return !!bank;
+}
+
+static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
+{
+	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
+	int num_parents = __clk_get_num_parents(hw->clk);
+	u32 ns, ctl;
+	int bank;
+	int i;
+	struct src_sel *s;
+
+	ctl = readl_relaxed(rcg->ctl_reg);
+	bank = reg_to_bank(rcg, ctl);
+	s = &rcg->s[bank];
+
+	ns = readl_relaxed(rcg->ns_reg);
+	ns = ns_to_src(s, ns);
+
+	for (i = 0; i < num_parents; i++)
+		if (ns == s->parent_map[i])
+			return i;
+
+	return -EINVAL;
+}
+
+static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_rcg *rcg = to_clk_rcg(hw);
+	unsigned long flags;
+	u32 ns;
+
+	spin_lock_irqsave(rcg->lock, flags);
+
+	ns = readl_relaxed(rcg->ns_reg);
+	ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns);
+	writel(ns, rcg->ns_reg);
+
+	spin_unlock_irqrestore(rcg->lock, flags);
+
+	return 0;
+}
+
+static u32 md_to_m(struct mn *mn, u32 md)
+{
+	md >>= mn->m_val_shift;
+	md &= BIT(mn->width) - 1;
+	return md;
+}
+
+static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
+{
+	ns >>= p->pre_div_shift;
+	ns &= BIT(p->pre_div_width) - 1;
+	return ns;
+}
+
+static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
+{
+	u32 mask;
+
+	mask = BIT(p->pre_div_width) - 1;
+	mask <<= p->pre_div_shift;
+	ns &= ~mask;
+
+	ns |= pre_div << p->pre_div_shift;
+	return ns;
+}
+
+static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
+{
+	u32 mask, mask_w;
+
+	mask_w = BIT(mn->width) - 1;
+	mask = (mask_w << mn->m_val_shift) | mask_w;
+	md &= ~mask;
+
+	if (n) {
+		m <<= mn->m_val_shift;
+		md |= m;
+		md |= ~n & mask_w;
+	}
+
+	return md;
+}
+
+static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
+{
+	ns = ~ns >> mn->n_val_shift;
+	ns &= BIT(mn->width) - 1;
+	return ns + m;
+}
+
+static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
+{
+	val >>= mn->mnctr_mode_shift;
+	val &= MNCTR_MODE_MASK;
+	return val;
+}
+
+static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
+{
+	u32 mask;
+
+	mask = BIT(mn->width) - 1;
+	mask <<= mn->n_val_shift;
+	ns &= ~mask;
+
+	if (n) {
+		n = n - m;
+		n = ~n;
+		n &= BIT(mn->width) - 1;
+		n <<= mn->n_val_shift;
+		ns |= n;
+	}
+
+	return ns;
+}
+
+static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
+{
+	u32 mask;
+
+	mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift;
+	mask |= BIT(mn->mnctr_en_bit);
+	val &= ~mask;
+
+	if (n) {
+		val |= BIT(mn->mnctr_en_bit);
+		val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift;
+	}
+
+	return val;
+}
+
+static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
+{
+	unsigned long flags;
+	u32 ns, md, ctl, *regp;
+	int bank, new_bank;
+	struct mn *mn;
+	struct pre_div *p;
+	struct src_sel *s;
+	bool enabled;
+	void __iomem *md_reg;
+	void __iomem *bank_reg;
+	bool banked_mn = !!rcg->md_reg[0];
+
+	spin_lock_irqsave(rcg->lock, flags);
+
+	enabled = __clk_is_enabled(rcg->hw.clk);
+
+	ns = readl_relaxed(rcg->ns_reg);
+	ctl = readl_relaxed(rcg->ctl_reg);
+
+	if (banked_mn) {
+		regp = &ctl;
+		bank_reg = rcg->ctl_reg;
+	} else {
+		regp = &ns;
+		bank_reg = rcg->ns_reg;
+	}
+
+	bank = reg_to_bank(rcg, *regp);
+	new_bank = enabled ? !bank : bank;
+
+	if (banked_mn) {
+		mn = &rcg->mn[new_bank];
+		md_reg = rcg->md_reg[new_bank];
+
+		ns |= BIT(mn->mnctr_reset_bit);
+		writel_relaxed(ns, rcg->ns_reg);
+
+		md = readl_relaxed(md_reg);
+		md = mn_to_md(mn, f->m, f->n, md);
+		writel_relaxed(md, md_reg);
+
+		ns = mn_to_ns(mn, f->m, f->n, ns);
+		writel_relaxed(ns, rcg->ns_reg);
+
+		ctl = mn_to_reg(mn, f->m, f->n, ctl);
+		writel_relaxed(ctl, rcg->ctl_reg);
+
+		ns &= ~BIT(mn->mnctr_reset_bit);
+		writel_relaxed(ns, rcg->ns_reg);
+	} else {
+		p = &rcg->p[new_bank];
+		ns = pre_div_to_ns(p, f->pre_div - 1, ns);
+	}
+
+	s = &rcg->s[new_bank];
+	ns = src_to_ns(s, s->parent_map[f->src], ns);
+	writel_relaxed(ns, rcg->ns_reg);
+
+	if (enabled) {
+		*regp ^= BIT(rcg->mux_sel_bit);
+		writel_relaxed(*regp, bank_reg);
+	}
+
+	/* Ensure parent switch is completed */
+	mb();
+	spin_unlock_irqrestore(rcg->lock, flags);
+}
+
+static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
+	u32 ns, ctl, md, reg;
+	int bank;
+	struct freq_tbl f = { 0 };
+	bool banked_mn = !!rcg->md_reg[0];
+
+	ctl = readl_relaxed(rcg->ctl_reg);
+	ns = readl_relaxed(rcg->ns_reg);
+	reg = banked_mn ? ctl : ns;
+
+	bank = reg_to_bank(rcg, reg);
+
+	if (banked_mn) {
+		md = readl_relaxed(rcg->md_reg[bank]);
+		f.m = md_to_m(&rcg->mn[bank], md);
+		f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
+	} else {
+		f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
+	}
+	f.src = index;
+
+	configure_bank(rcg, &f);
+
+	return 0;
+}
+
+/*
+ * Calculate m/n:d rate
+ *
+ *          parent_rate     m
+ *   rate = ----------- x  ---
+ *            pre_div       n
+ */
+static unsigned long
+calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
+{
+	if (pre_div)
+		rate /= pre_div + 1;
+
+	if (mode) {
+		u64 tmp = rate;
+		tmp *= m;
+		do_div(tmp, n);
+		rate = tmp;
+	}
+
+	return rate;
+}
+
+static unsigned long
+clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct clk_rcg *rcg = to_clk_rcg(hw);
+	u32 pre_div, m, n, ns, md, mode;
+	struct mn *mn = &rcg->mn;
+
+	ns = readl_relaxed(rcg->ns_reg);
+	md = readl_relaxed(rcg->md_reg);
+
+	pre_div = ns_to_pre_div(&rcg->p, ns);
+	m = md_to_m(mn, md);
+	n = ns_m_to_n(mn, ns, m);
+	/* MN counter mode is in ctl_reg sometimes */
+	if (rcg->ctl_reg != rcg->ns_reg)
+		mode = readl_relaxed(rcg->ctl_reg);
+	else
+		mode = ns;
+	mode = reg_to_mnctr_mode(mn, mode);
+
+	return calc_rate(parent_rate, m, n, mode, pre_div);
+}
+
+static unsigned long
+clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
+	u32 m, n, pre_div, ns, md, mode, reg;
+	int bank;
+	struct mn *mn;
+	bool banked_mn = !!rcg->md_reg[0];
+
+	ns = readl_relaxed(rcg->ns_reg);
+
+	if (banked_mn)
+		reg = readl_relaxed(rcg->ctl_reg);
+	else
+		reg = ns;
+
+	bank = reg_to_bank(rcg, reg);
+
+	if (banked_mn) {
+		mn = &rcg->mn[bank];
+		md = readl_relaxed(rcg->md_reg[bank]);
+		m = md_to_m(mn, md);
+		n = ns_m_to_n(mn, ns, m);
+		mode = reg_to_mnctr_mode(mn, reg);
+		return calc_rate(parent_rate, m, n, mode, 0);
+	} else {
+		pre_div = ns_to_pre_div(&rcg->p[bank], ns);
+		return calc_rate(parent_rate, 0, 0, 0, pre_div);
+	}
+}
+
+static const
+struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
+{
+	for (; f->freq; f++)
+		if (rate <= f->freq)
+			return f;
+
+	return NULL;
+}
+
+static long _freq_tbl_determine_rate(struct clk_hw *hw,
+		const struct freq_tbl *f, unsigned long rate,
+		unsigned long *p_rate, struct clk **p)
+{
+	f = find_freq(f, rate);
+	if (!f)
+		return -EINVAL;
+
+	*p = clk_get_parent_by_index(hw->clk, f->src);
+	*p_rate =  __clk_get_rate(*p);
+
+	return f->freq;
+}
+
+static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long *p_rate, struct clk **p)
+{
+	struct clk_rcg *rcg = to_clk_rcg(hw);
+
+	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
+}
+
+static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long *p_rate, struct clk **p)
+{
+	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
+
+	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
+}
+
+static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	struct clk_rcg *rcg = to_clk_rcg(hw);
+	unsigned long flags;
+	const struct freq_tbl *f;
+	u32 ns, md, ctl;
+	struct mn *mn = &rcg->mn;
+
+	f = find_freq(rcg->freq_tbl, rate);
+	if (!f)
+		return -EINVAL;
+
+	spin_lock_irqsave(rcg->lock, flags);
+
+	ns = readl_relaxed(rcg->ns_reg);
+	ns |= BIT(mn->mnctr_reset_bit);
+	writel_relaxed(ns, rcg->ns_reg);
+
+	md = readl_relaxed(rcg->md_reg);
+	md = mn_to_md(mn, f->m, f->n, md);
+	writel_relaxed(md, rcg->md_reg);
+
+	/* MN counter mode is in ctl_reg sometimes */
+	if (rcg->ctl_reg != rcg->ns_reg) {
+		ctl = readl_relaxed(rcg->ctl_reg);
+		ctl = mn_to_reg(mn, f->m, f->n, ctl);
+		writel_relaxed(ctl, rcg->ctl_reg);
+	} else {
+		ns = mn_to_reg(mn, f->m, f->n, ns);
+	}
+	ns = mn_to_ns(mn, f->m, f->n, ns);
+	ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
+	writel_relaxed(ns, rcg->ns_reg);
+
+	ns &= ~BIT(mn->mnctr_reset_bit);
+	writel(ns, rcg->ns_reg);
+
+	spin_unlock_irqrestore(rcg->lock, flags);
+
+	return 0;
+}
+
+static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
+{
+	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
+	const struct freq_tbl *f;
+
+	f = find_freq(rcg->freq_tbl, rate);
+	if (!f)
+		return -EINVAL;
+
+	configure_bank(rcg, f);
+
+	return 0;
+}
+
+static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	return __clk_dyn_rcg_set_rate(hw, rate);
+}
+
+static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
+		unsigned long rate, unsigned long parent_rate, u8 index)
+{
+	return __clk_dyn_rcg_set_rate(hw, rate);
+}
+
+static const struct clk_ops clk_rcg_ops = {
+	.enable = clk_rcg_enable,
+	.disable = clk_rcg_disable,
+	.get_parent = clk_rcg_get_parent,
+	.set_parent = clk_rcg_set_parent,
+	.recalc_rate = clk_rcg_recalc_rate,
+	.determine_rate = clk_rcg_determine_rate,
+	.set_rate = clk_rcg_set_rate,
+};
+
+struct clk *rcg_clk_register(struct device *dev, struct rcg_desc *desc,
+		spinlock_t *lock, struct clk_init_data *init,
+		u8 pre_div_width, u8 mnd_width)
+{
+	struct clk_rcg *r;
+
+	r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
+	if (!r)
+		return ERR_PTR(-ENOMEM);
+
+	r->ctl_reg = desc->base + desc->ctl_reg;
+	r->ns_reg = desc->base + desc->ns_reg;
+	r->md_reg = desc->base + desc->md_reg;
+	r->ctl_bit = desc->ctl_bit;
+	r->mn.mnctr_en_bit = desc->mnctr_en_bit;
+	r->mn.mnctr_reset_bit = desc->mnctr_reset_bit;
+	r->mn.mnctr_mode_shift = desc->mnctr_mode_shift;
+	r->mn.n_val_shift = desc->n_val_shift;
+	r->mn.m_val_shift = desc->m_val_shift;
+	r->p.pre_div_shift = desc->pre_div_shift;
+	r->p.pre_div_width = pre_div_width;
+	r->s.src_sel_shift = desc->src_sel_shift;
+	r->s.parent_map = desc->parent_map;
+	r->freq_tbl = desc->freq_tbl;
+	r->lock = lock;
+	r->mn.width = mnd_width;
+
+	init->ops = &clk_rcg_ops;
+	init->flags |= CLK_SET_RATE_GATE;
+	r->hw.init = init;
+
+	return devm_clk_register(dev, &r->hw);
+}
+
+static const struct clk_ops clk_dyn_rcg_ops = {
+	.enable = clk_dyn_rcg_enable,
+	.is_enabled = clk_dyn_rcg_is_enabled,
+	.disable = clk_dyn_rcg_disable,
+	.get_parent = clk_dyn_rcg_get_parent,
+	.set_parent = clk_dyn_rcg_set_parent,
+	.recalc_rate = clk_dyn_rcg_recalc_rate,
+	.determine_rate = clk_dyn_rcg_determine_rate,
+	.set_rate = clk_dyn_rcg_set_rate,
+	.set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
+};
+
+struct clk *
+rcg_dyn_clk_register(struct device *dev, struct rcg_dyn_desc *desc,
+		spinlock_t *lock, struct clk_init_data *init, u8 pre_div_width,
+		u8 mnd_width)
+{
+	struct clk_dyn_rcg *r;
+
+	r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
+	if (!r)
+		return ERR_PTR(-ENOMEM);
+
+	r->ctl_reg = desc->base + desc->ctl_reg;
+	r->ns_reg = desc->base + desc->ns_reg;
+	r->ctl_bit = desc->ctl_bit;
+	if (mnd_width) {
+		r->md_reg[0] = desc->base + desc->md0_reg;
+		r->md_reg[1] = desc->base + desc->md1_reg;
+		r->mn[0].mnctr_en_bit = desc->mnctr0_en_bit;
+		r->mn[0].mnctr_reset_bit = desc->mnctr0_reset_bit;
+		r->mn[0].mnctr_mode_shift = desc->mnctr0_mode_shift;
+		r->mn[0].n_val_shift = desc->n0_val_shift;
+		r->mn[0].m_val_shift = desc->m0_val_shift;
+		r->mn[0].width = mnd_width;
+		r->mn[1].mnctr_en_bit = desc->mnctr1_en_bit;
+		r->mn[1].mnctr_reset_bit = desc->mnctr1_reset_bit;
+		r->mn[1].mnctr_mode_shift = desc->mnctr1_mode_shift;
+		r->mn[1].n_val_shift = desc->n1_val_shift;
+		r->mn[1].m_val_shift = desc->m1_val_shift;
+		r->mn[1].width = mnd_width;
+	}
+	if (pre_div_width) {
+		r->p[0].pre_div_shift = desc->pre_div0_shift;
+		r->p[0].pre_div_width = pre_div_width;
+		r->p[1].pre_div_shift = desc->pre_div1_shift;
+		r->p[1].pre_div_width = pre_div_width;
+	}
+	r->s[0].src_sel_shift = desc->src0_sel_shift;
+	r->s[0].parent_map = desc->parent_map;
+	r->s[1].src_sel_shift = desc->src1_sel_shift;
+	r->s[1].parent_map = desc->parent_map;
+	r->mux_sel_bit = desc->mux_sel_bit;
+	r->freq_tbl = desc->freq_tbl;
+	r->lock = lock;
+
+	init->ops = &clk_dyn_rcg_ops;
+	r->hw.init = init;
+
+	return devm_clk_register(dev, &r->hw);
+}
diff --git a/drivers/clk/msm/clk-rcg.h b/drivers/clk/msm/clk-rcg.h
new file mode 100644
index 0000000..9cc572d
--- /dev/null
+++ b/drivers/clk/msm/clk-rcg.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MSM_CLK_RCG_H__
+#define __MSM_CLK_RCG_H__
+
+struct device;
+struct clk;
+struct clk_init_data;
+
+struct freq_tbl {
+	unsigned long freq;
+	u8 src;
+	u8 pre_div;
+	u16 m;
+	u16 n;
+};
+
+struct rcg_desc {
+	void __iomem *base;
+	u32 ctl_reg;
+	u32 ns_reg;
+	u32 md_reg;
+
+	u8 ctl_bit;
+	u8 mnctr_en_bit;
+	u8 mnctr_reset_bit;
+	u8 mnctr_mode_shift;
+	u8 pre_div_shift;
+	u8 src_sel_shift;
+	u8 n_val_shift;
+	u8 m_val_shift;
+
+	u8 *parent_map;
+	struct freq_tbl *freq_tbl;
+};
+
+extern struct clk *rcg_clk_register(struct device *dev, struct rcg_desc *desc,
+		spinlock_t *lock, struct clk_init_data *init,
+		u8 pre_div_width, u8 mnd_width);
+
+#define rcg_p2mn8_clk_register(dev, desc, lock, init) \
+	rcg_clk_register(dev, desc, lock, init, 2, 8)
+#define rcg_p2mn16_clk_register(dev, desc, lock, init) \
+	rcg_clk_register(dev, desc, lock, init, 2, 16)
+
+struct rcg_dyn_desc {
+	void __iomem *base;
+	u32 ctl_reg;
+	u32 ns_reg;
+	u32 md0_reg;
+	u32 md1_reg;
+
+	u8 ctl_bit;
+	u8 mnctr0_en_bit;
+	u8 mnctr1_en_bit;
+	u8 mnctr0_reset_bit;
+	u8 mnctr1_reset_bit;
+	u8 mnctr0_mode_shift;
+	u8 mnctr1_mode_shift;
+	u8 pre_div0_shift;
+	u8 pre_div1_shift;
+	u8 src0_sel_shift;
+	u8 src1_sel_shift;
+	u8 n0_val_shift;
+	u8 n1_val_shift;
+	u8 m0_val_shift;
+	u8 m1_val_shift;
+	u8 mux_sel_bit;
+
+	u8 *parent_map;
+	struct freq_tbl *freq_tbl;
+};
+
+struct clk *rcg_dyn_clk_register(struct device *dev,
+		struct rcg_dyn_desc *desc, spinlock_t *lock,
+		struct clk_init_data *init, u8 pre_div_width, u8 mnd_width);
+
+#define rcg_mn4_dyn_clk_register(dev, desc, lock, init) \
+	rcg_dyn_clk_register(dev, desc, lock, init, 0, 4)
+#define rcg_mn8_dyn_clk_register(dev, desc, lock, init) \
+	rcg_dyn_clk_register(dev, desc, lock, init, 0, 8)
+#define rcg_p4_dyn_clk_register(dev, desc, lock, init) \
+	rcg_dyn_clk_register(dev, desc, lock, init, 4, 0)
+
+struct rcg2_desc {
+	void __iomem *base;
+	u32 cmd_rcgr;
+	u8 *parent_map;
+	struct freq_tbl *freq_tbl;
+};
+
+extern struct clk *rcg2_clk_register(struct device *dev, struct rcg2_desc *desc,
+		spinlock_t *lock, struct clk_init_data *init,
+		u8 hid_width, u8 mnd_width);
+
+#define rcg_h5_clk_register(dev, desc, lock, init) \
+	rcg2_clk_register(dev, desc, lock, init, 5, 0)
+#define rcg_h5mn8_clk_register(dev, desc, lock, init) \
+	rcg2_clk_register(dev, desc, lock, init, 5, 8)
+#define rcg_h5mn16_clk_register(dev, desc, lock, init) \
+	rcg2_clk_register(dev, desc, lock, init, 5, 16)
+
+#endif
diff --git a/drivers/clk/msm/clk-rcg2.c b/drivers/clk/msm/clk-rcg2.c
new file mode 100644
index 0000000..b8daf87
--- /dev/null
+++ b/drivers/clk/msm/clk-rcg2.c
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <asm/div64.h>
+
+#include "clk-rcg.h"
+
+#define CMD_REG			0x0
+#define CMD_UPDATE		BIT(0)
+#define CMD_ROOT_EN		BIT(1)
+#define CMD_DIRTY_CFG		BIT(4)
+#define CMD_DIRTY_N		BIT(5)
+#define CMD_DIRTY_M		BIT(6)
+#define CMD_DIRTY_D		BIT(7)
+#define CMD_ROOT_OFF		BIT(31)
+
+#define CFG_REG			0x4
+#define CFG_SRC_DIV_SHIFT	0
+#define CFG_SRC_SEL_SHIFT	8
+#define CFG_SRC_SEL_MASK	(0x7 << CFG_SRC_SEL_SHIFT)
+#define CFG_MODE_SHIFT		12
+#define CFG_MODE_MASK		(0x3 << CFG_MODE_SHIFT)
+#define CFG_MODE_DUAL_EDGE	(0x2 << CFG_MODE_SHIFT)
+
+#define M_REG			0x8
+#define N_REG			0xc
+#define D_REG			0x10
+
+/**
+ * struct clk_rcg2 - root clock generator
+ *
+ * @base: corresponds to *_CMD_RCGR
+ * @mnd_width: number of bits in m/n/d values
+ * @hid_width: number of bits in half integer divider
+ * @parent_map: map from software's parent index to hardware's src_sel field
+ * @freq_tbl: Frequency table
+ * @hw: handle between common and hardware-specific interfaces
+ * @lock: register lock
+ *
+ */
+struct clk_rcg2 {
+	void __iomem		*base;
+	u8			mnd_width;
+	u8			hid_width;
+	u8			*parent_map;
+	const struct freq_tbl	*freq_tbl;
+	struct clk_hw		hw;
+	spinlock_t		*lock;
+};
+
+#define to_clk_rcg2(_hw) container_of(_hw, struct clk_rcg2, hw)
+
+static int clk_rcg2_is_enabled(struct clk_hw *hw)
+{
+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+	u32 cmd;
+
+	cmd = readl_relaxed(rcg->base + CMD_REG);
+	cmd &= CMD_ROOT_OFF;
+
+	return cmd ? 0 : 1;
+}
+
+static u8 clk_rcg2_get_parent(struct clk_hw *hw)
+{
+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+	int num_parents = __clk_get_num_parents(hw->clk);
+	u32 cfg;
+	int i;
+
+	cfg = readl_relaxed(rcg->base + CFG_REG);
+	cfg &= CFG_SRC_SEL_MASK;
+	cfg >>= CFG_SRC_SEL_SHIFT;
+
+	for (i = 0; i < num_parents; i++)
+		if (cfg == rcg->parent_map[i])
+			return i;
+
+	return -EINVAL;
+}
+
+static void update_config(struct clk_rcg2 *rcg)
+{
+	int count;
+	u32 cmd;
+	const char *name = __clk_get_name(rcg->hw.clk);
+
+	cmd = readl_relaxed(rcg->base + CMD_REG);
+	cmd |= CMD_UPDATE;
+	writel_relaxed(cmd, rcg->base + CMD_REG);
+
+	/* Wait for update to take effect */
+	for (count = 500; count > 0; count--) {
+		if (!(readl_relaxed(rcg->base + CMD_REG) & CMD_UPDATE))
+			return;
+		udelay(1);
+	}
+
+	WARN(1, "%s: rcg didn't update its configuration.", name);
+}
+
+static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+	unsigned long flags;
+	u32 cfg;
+
+	spin_lock_irqsave(rcg->lock, flags);
+
+	cfg = readl_relaxed(rcg->base + CFG_REG);
+	cfg &= ~CFG_SRC_SEL_MASK;
+	cfg |= rcg->parent_map[index] << CFG_SRC_SEL_SHIFT;
+	writel(cfg, rcg->base + CFG_REG);
+
+	update_config(rcg);
+
+	spin_unlock_irqrestore(rcg->lock, flags);
+
+	return 0;
+}
+
+/*
+ * Calculate m/n:d rate
+ *
+ *          parent_rate     m
+ *   rate = ----------- x  ---
+ *            hid_div       n
+ */
+static unsigned long
+calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
+{
+	if (hid_div) {
+		rate *= 2;
+		rate /= hid_div + 1;
+	}
+
+	if (mode) {
+		u64 tmp = rate;
+		tmp *= m;
+		do_div(tmp, n);
+		rate = tmp;
+	}
+
+	return rate;
+}
+
+static unsigned long
+clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+	u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
+
+	cfg = readl_relaxed(rcg->base + CFG_REG);
+
+	if (rcg->mnd_width) {
+		mask = BIT(rcg->mnd_width) - 1;
+		m = readl_relaxed(rcg->base + M_REG);
+		m &= mask;
+		n = readl_relaxed(rcg->base + N_REG);
+		n =  ~n;
+		n &= mask;
+		n += m;
+		mode = cfg & CFG_MODE_MASK;
+		mode >>= CFG_MODE_SHIFT;
+	}
+
+	mask = BIT(rcg->hid_width) - 1;
+	hid_div = cfg >> CFG_SRC_DIV_SHIFT;
+	hid_div &= mask;
+
+	return calc_rate(parent_rate, m, n, mode, hid_div);
+}
+
+static const
+struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
+{
+	for (; f->freq; f++)
+		if (rate <= f->freq)
+			return f;
+
+	return NULL;
+}
+
+static long _freq_tbl_determine_rate(struct clk_hw *hw,
+		const struct freq_tbl *f, unsigned long rate,
+		unsigned long *p_rate, struct clk **p)
+{
+	f = find_freq(f, rate);
+	if (!f)
+		return -EINVAL;
+
+	*p = clk_get_parent_by_index(hw->clk, f->src);
+	*p_rate =  __clk_get_rate(*p);
+
+	return f->freq;
+}
+
+static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long *p_rate, struct clk **p)
+{
+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+
+	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
+}
+
+static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
+{
+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+	unsigned long flags;
+	const struct freq_tbl *f;
+	u32 cfg, m, n, d, mask, val;
+
+	f = find_freq(rcg->freq_tbl, rate);
+	if (!f)
+		return -EINVAL;
+
+	spin_lock_irqsave(rcg->lock, flags);
+
+	cfg = readl_relaxed(rcg->base + CFG_REG);
+	mask = BIT(rcg->hid_width) - 1;
+	mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
+	cfg &= ~mask;
+
+	if (rcg->mnd_width && f->n) {
+		mask = BIT(rcg->mnd_width) - 1;
+		m = readl_relaxed(rcg->base + M_REG);
+		m &= ~mask;
+		m |= f->m;
+		writel_relaxed(m, rcg->base + M_REG);
+
+		val = readl_relaxed(rcg->base + M_REG);
+		val &= ~mask;
+		n = f->n - f->m;
+		n = ~n;
+		n &= mask;
+		val |= n;
+		writel_relaxed(val, rcg->base + N_REG);
+
+		d = readl_relaxed(rcg->base + D_REG);
+		d &= ~mask;
+		d |= ~f->n & mask;
+		writel_relaxed(d, rcg->base + D_REG);
+
+		cfg |= CFG_MODE_DUAL_EDGE;
+	}
+
+	cfg |= f->pre_div << CFG_SRC_DIV_SHIFT;
+	cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
+	writel_relaxed(cfg, rcg->base + CFG_REG);
+
+	update_config(rcg);
+
+	spin_unlock_irqrestore(rcg->lock, flags);
+
+	return 0;
+}
+
+static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	return __clk_rcg2_set_rate(hw, rate);
+}
+
+static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
+		unsigned long rate, unsigned long parent_rate, u8 index)
+{
+	return __clk_rcg2_set_rate(hw, rate);
+}
+
+static const struct clk_ops clk_rcg2_ops = {
+	.is_enabled = clk_rcg2_is_enabled,
+	.get_parent = clk_rcg2_get_parent,
+	.set_parent = clk_rcg2_set_parent,
+	.recalc_rate = clk_rcg2_recalc_rate,
+	.determine_rate = clk_rcg2_determine_rate,
+	.set_rate = clk_rcg2_set_rate,
+	.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
+};
+
+struct clk *rcg2_clk_register(struct device *dev, struct rcg2_desc *desc,
+		spinlock_t *lock, struct clk_init_data *init,
+		u8 hid_width, u8 mnd_width)
+{
+	struct clk_rcg2 *r;
+
+	r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
+	if (!r)
+		return ERR_PTR(-ENOMEM);
+
+	r->base = desc->base + desc->cmd_rcgr;
+	r->parent_map = desc->parent_map;
+	r->freq_tbl = desc->freq_tbl;
+	r->lock = lock;
+	r->mnd_width = mnd_width;
+	r->hid_width = hid_width;
+
+	init->ops = &clk_rcg2_ops;
+	r->hw.init = init;
+
+	return devm_clk_register(dev, &r->hw);
+}
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[RFC/PATCH 07/13] clk: msm: Add support for branches/gate clocks

[Stephen Boyd]

Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 Documentation/devicetree/bindings/clock/msm.txt |  28 ++++
 drivers/clk/msm/Makefile                        |   1 +
 drivers/clk/msm/clk-branch.c                    | 190 ++++++++++++++++++++++++
 drivers/clk/msm/clk-branch.h                    |  48 ++++++
 4 files changed, 267 insertions(+)
 create mode 100644 drivers/clk/msm/clk-branch.c
 create mode 100644 drivers/clk/msm/clk-branch.h

diff --git a/Documentation/devicetree/bindings/clock/msm.txt b/Documentation/devicetree/bindings/clock/msm.txt
index f4595fa..6840398 100644
--- a/Documentation/devicetree/bindings/clock/msm.txt
+++ b/Documentation/devicetree/bindings/clock/msm.txt
@@ -69,3 +69,31 @@ Example:
 		clocks = <&pxo>, <&pll2>, <&pll8>;
 	};
 
+CXC Binding
+-----------
+
+Required properties:
+- compatible : shall be "qcom,cxc-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : from common clock binding; shall be set to the source being gated
+
+Example:
+	gsbi5_uart_clk: gsbi5_uart_cxc {
+		#clock-cells = <0>;
+		compatible = "qcom,cxc-clock";
+		clocks = <&gsbi5_uart_rcg>;
+	};
+
+CXC With Hardware Gating Binding
+--------------------------------
+
+Required properties:
+- compatible : shall be "qcom,cxc-hg-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : from common clock binding; shall be set to the source being gated
+
+	gsbi5_uart_ahb: gsbi5_uart_ahb {
+		#clock-cells = <0>;
+		compatible = "qcom,cxc-hg-clock";
+		clocks = <&cfpb_clk>;
+	};
diff --git a/drivers/clk/msm/Makefile b/drivers/clk/msm/Makefile
index fb78ac9..e1cee29 100644
--- a/drivers/clk/msm/Makefile
+++ b/drivers/clk/msm/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_COMMON_CLK_MSM) += clk-msm.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-pll.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg2.o
+clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-branch.o
diff --git a/drivers/clk/msm/clk-branch.c b/drivers/clk/msm/clk-branch.c
new file mode 100644
index 0000000..ff2e599
--- /dev/null
+++ b/drivers/clk/msm/clk-branch.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+
+#include "clk-branch.h"
+
+/**
+ * struct clk_branch - gating clock with status bit and dynamic hardware gating
+ *
+ * @ctl_reg: clock control register
+ * @ctl_bit: ORed with @ctl_reg to enable the clock
+ * @hwcg_reg: dynamic hardware clock gating register
+ * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
+ * @halt_reg: halt register
+ * @halt_bit: ANDed with @halt_reg to test for clock halted
+ * @halt_check: type of halt checking to perform
+ * @hw: handle between common and hardware-specific interfaces
+ * @lock: register lock
+ *
+ * Clock which can gate its output.
+ */
+struct clk_branch {
+	void __iomem	*ctl_reg;
+	void __iomem	*hwcg_reg;
+	void __iomem	*halt_reg;
+
+	u8		ctl_bit;
+	u8		hwcg_bit;
+	u8		halt_bit;
+	u8		halt_check;
+
+	struct clk_hw	hw;
+	spinlock_t	*lock;
+};
+
+#define to_clk_branch(_hw) container_of(_hw, struct clk_branch, hw)
+
+static bool clk_branch_is_halted(const struct clk_branch *br)
+{
+	bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
+	u32 status_bit = readl_relaxed(br->halt_reg) & BIT(br->halt_bit);
+	return invert ? !status_bit : status_bit;
+}
+
+static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
+{
+	if (!br->hwcg_reg)
+		return 0;
+
+	return !!(readl_relaxed(br->hwcg_reg) & BIT(br->hwcg_bit));
+}
+
+static int clk_branch_wait(const struct clk_branch *br, bool enabling)
+{
+	bool voted = br->halt_check & BRANCH_VOTED;
+	const char *name = __clk_get_name(br->hw.clk);
+
+	/* Skip checking halt bit if the clock is in hardware gated mode */
+	if (clk_branch_in_hwcg_mode(br))
+		return 0;
+
+	if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
+		udelay(10);
+	} else if (br->halt_check == BRANCH_HALT_ENABLE ||
+		   br->halt_check == BRANCH_HALT ||
+		   (enabling && voted)) {
+		int count = 200;
+
+		while (count-- > 0) {
+			if (clk_branch_is_halted(br) == !enabling)
+				return 0;
+			udelay(1);
+		}
+		WARN("%s status stuck at 'o%s'", name, enabling ? "ff" : "n");
+		return -EBUSY;
+	}
+	return 0;
+}
+
+static int clk_branch_toggle(const struct clk_hw *hw, bool en)
+{
+	struct clk_branch *br = to_clk_branch(hw);
+	unsigned long flags;
+	u32 val;
+
+	spin_lock_irqsave(br->lock, flags);
+
+	val = readl_relaxed(br->ctl_reg);
+	if (en)
+		val |= BIT(br->ctl_bit);
+	else
+		val &= ~BIT(br->ctl_bit);
+	writel(val, br->ctl_reg);
+
+	spin_unlock_irqrestore(br->lock, flags);
+
+	return clk_branch_wait(br, en);
+}
+
+static int clk_branch_enable(struct clk_hw *hw)
+{
+	return clk_branch_toggle(hw, true);
+}
+
+static void clk_branch_disable(struct clk_hw *hw)
+{
+	clk_branch_toggle(hw, false);
+}
+
+static int clk_branch_is_enabled(struct clk_hw *hw)
+{
+	struct clk_branch *br = to_clk_branch(hw);
+	u32 val;
+
+	val = readl_relaxed(br->ctl_reg);
+	val &= BIT(br->ctl_bit);
+
+	return val ? 1 : 0;
+}
+
+static const struct clk_ops clk_branch_ops = {
+	.enable = clk_branch_enable,
+	.is_enabled = clk_branch_is_enabled,
+	.disable = clk_branch_disable,
+};
+
+struct clk *branch_clk_register(struct device *dev, struct branch_desc *desc,
+		spinlock_t *lock, struct clk_init_data *init)
+{
+	struct clk_branch *b;
+
+	b = devm_kzalloc(dev, sizeof(*b), GFP_KERNEL);
+	if (!b)
+		return ERR_PTR(-ENOMEM);
+
+	b->ctl_reg = desc->base + desc->ctl_reg;
+	b->halt_reg = desc->base + desc->halt_reg;
+	b->ctl_bit = desc->ctl_bit;
+	b->halt_bit = desc->halt_bit;
+	b->halt_check = desc->halt_check;
+	b->lock = lock;
+
+	init->ops = &clk_branch_ops;
+	init->flags |= CLK_SET_RATE_PARENT;
+	b->hw.init = init;
+
+	return devm_clk_register(dev, &b->hw);
+}
+
+struct clk *branch_hg_clk_register(struct device *dev, struct branch_desc *desc,
+		spinlock_t *lock, struct clk_init_data *init)
+{
+	struct clk_branch *b;
+
+	b = devm_kzalloc(dev, sizeof(*b), GFP_KERNEL);
+	if (!b)
+		return ERR_PTR(-ENOMEM);
+
+	b->ctl_reg = desc->base + desc->ctl_reg;
+	b->halt_reg = desc->base + desc->halt_reg;
+	b->hwcg_reg = desc->base + desc->hwcg_reg;
+	b->ctl_bit = desc->ctl_bit;
+	b->halt_bit = desc->halt_bit;
+	b->halt_check = desc->halt_check;
+	b->lock = lock;
+
+	init->ops = &clk_branch_ops;
+	init->flags |= CLK_SET_RATE_PARENT;
+	b->hw.init = init;
+
+	return devm_clk_register(dev, &b->hw);
+}
diff --git a/drivers/clk/msm/clk-branch.h b/drivers/clk/msm/clk-branch.h
new file mode 100644
index 0000000..bcb7345
--- /dev/null
+++ b/drivers/clk/msm/clk-branch.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MSM_CLK_BRANCH_H__
+#define __MSM_CLK_BRANCH_H__
+
+#include <linux/spinlock.h>
+
+struct device;
+struct clk;
+struct clk_init_data;
+
+struct branch_desc {
+	void __iomem *base;
+	u32 ctl_reg;
+	u32 hwcg_reg;
+	u32 halt_reg;
+
+	u8 ctl_bit;
+	u8 hwcg_bit;
+	u8 halt_bit;
+	u8 halt_check;
+#define BRANCH_VOTED			BIT(7) /* Delay on disable */
+#define BRANCH_HALT			0 /* pol: 1 = halt */
+#define BRANCH_HALT_VOTED		(BRANCH_HALT | BRANCH_VOTED)
+#define BRANCH_HALT_ENABLE		1 /* pol: 0 = halt */
+#define BRANCH_HALT_ENABLE_VOTED	(BRANCH_HALT_ENABLE | BRANCH_VOTED)
+#define BRANCH_HALT_DELAY		2 /* No bit to check; just delay */
+};
+
+extern struct clk *branch_clk_register(struct device *dev,
+		struct branch_desc *desc, spinlock_t *lock,
+		struct clk_init_data *init);
+extern struct clk *branch_hg_clk_register(struct device *dev,
+		struct branch_desc *desc, spinlock_t *lock,
+		struct clk_init_data *init);
+
+#endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[RFC/PATCH 09/13] clk: msm: Add support for MSM8960's global clock controller (GCC)

[Stephen Boyd]

Fill in the data and wire up the global clock controller to the
MSM clock driver. This should allow most non-multimedia device
drivers to control their clocks on 8960 based platforms.

Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 .../devicetree/bindings/clock/qcom,gcc.txt         |  55 +++++++
 drivers/clk/msm/Kconfig                            |  10 ++
 drivers/clk/msm/Makefile                           |   2 +
 drivers/clk/msm/core.c                             |   3 +
 drivers/clk/msm/gcc-8960.c                         | 174 +++++++++++++++++++++
 drivers/clk/msm/internal.h                         |   2 +
 6 files changed, 246 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
 create mode 100644 drivers/clk/msm/gcc-8960.c

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
new file mode 100644
index 0000000..2311e1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -0,0 +1,55 @@
+MSM Global Clock Controller Binding
+-----------------------------------
+
+Required properties :
+- compatible : shall contain at least "qcom,gcc" and only one of the
+	       following:
+
+			"qcom,gcc-8660"
+			"qcom,gcc-8960"
+
+- reg : shall contain base register location and length
+- clocks : shall contain clocks supplied by the clock controller
+
+Example:
+	clock-controller@900000 {
+		compatible = "qcom,gcc-8960", "qcom,gcc";
+		reg = <0x900000 0x4000>;
+
+		clocks {
+			pxo: pxo {
+				#clock-cells = <0>;
+				compatible = "fixed-clock";
+				clock-frequency = <27000000>;
+			};
+
+			pll8: pll8 {
+				#clock-cells = <0>;
+				compatible = "qcom,pll";
+				clocks = <&pxo>;
+			};
+
+			vpll8: vpll8 {
+				#clock-cells = <0>;
+				compatible = "qcom,pll-vote";
+				clocks = <&pll8>;
+			};
+
+			gsbi5_uart_rcg: gsbi5_uart_rcg {
+				#clock-cells = <0>;
+				compatible = "qcom,p2-mn16-clock";
+				clocks = <&pxo>, <&vpll8>;
+			};
+
+			gsbi5_uart_clk: gsbi5_uart_cxc {
+				#clock-cells = <0>;
+				compatible = "qcom,cxc-clock";
+				clocks = <&gsbi5_uart_rcg>;
+			};
+
+			gsbi5_uart_ahb: gsbi5_uart_ahb {
+				#clock-cells = <0>;
+				compatible = "qcom,cxc-hg-clock";
+			};
+		};
+	};
diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig
index bf7e3d2..3eaffb6 100644
--- a/drivers/clk/msm/Kconfig
+++ b/drivers/clk/msm/Kconfig
@@ -2,3 +2,13 @@ menuconfig COMMON_CLK_MSM
 	tristate "Support for Qualcomm's MSM designs"
 	depends on OF
 
+if COMMON_CLK_MSM
+
+config MSM_GCC_8960
+	bool "MSM8960 Global Clock Controller"
+	help
+	  Support for the global clock controller on msm8960 devices.
+	  Say Y if you want to use peripheral devices such as UART, SPI,
+	  i2c, USB, SD/eMMC, SATA, PCIe, etc.
+
+endif
diff --git a/drivers/clk/msm/Makefile b/drivers/clk/msm/Makefile
index 9cfd0d7..c785943 100644
--- a/drivers/clk/msm/Makefile
+++ b/drivers/clk/msm/Makefile
@@ -6,3 +6,5 @@ clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg2.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-branch.o
 
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += core.o
+
+clk-msm-$(CONFIG_MSM_GCC_8960) += gcc-8960.o
diff --git a/drivers/clk/msm/core.c b/drivers/clk/msm/core.c
index b1904c0..b1ac8c1 100644
--- a/drivers/clk/msm/core.c
+++ b/drivers/clk/msm/core.c
@@ -173,6 +173,9 @@ typedef struct clk *
 		struct cc_data *cc);
 
 static const struct of_device_id msm_cc_match_table[] = {
+#ifdef CONFIG_MSM_GCC_8960
+	{ .compatible = "qcom,gcc-8960", .data = &msm_gcc_clk_matches },
+#endif
 	{ }
 };
 MODULE_DEVICE_TABLE(of, msm_cc_match_table);
diff --git a/drivers/clk/msm/gcc-8960.c b/drivers/clk/msm/gcc-8960.c
new file mode 100644
index 0000000..11f47d8
--- /dev/null
+++ b/drivers/clk/msm/gcc-8960.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+
+#include "internal.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+
+static struct pll_desc pll8_desc = {
+	.l_reg = 0x3144,
+	.m_reg = 0x3148,
+	.n_reg = 0x314c,
+	.config_reg = 0x3154,
+	.mode_reg = 0x3140,
+	.status_reg = 0x3158,
+	.status_bit = 16,
+};
+
+static struct pll_vote_desc pll8_vote_desc = {
+	.vote_reg = 0x34c0,
+	.vote_bit = 8,
+};
+
+#define PXO	0
+#define PLL8	1
+
+static u8 gcc_pxo_pll8_map[] = {
+	[PXO]	= 0,
+	[PLL8]	= 3,
+};
+
+static struct freq_tbl clk_tbl_gsbi_uart[] = {
+	{  1843200, PLL8, 2,  6, 625 },
+	{  3686400, PLL8, 2, 12, 625 },
+	{  7372800, PLL8, 2, 24, 625 },
+	{ 14745600, PLL8, 2, 48, 625 },
+	{ 16000000, PLL8, 4,  1,   6 },
+	{ 24000000, PLL8, 4,  1,   4 },
+	{ 32000000, PLL8, 4,  1,   3 },
+	{ 40000000, PLL8, 1,  5,  48 },
+	{ 46400000, PLL8, 1, 29, 240 },
+	{ 48000000, PLL8, 4,  1,   2 },
+	{ 51200000, PLL8, 1,  2,  15 },
+	{ 56000000, PLL8, 1,  7,  48 },
+	{ 58982400, PLL8, 1, 96, 625 },
+	{ 64000000, PLL8, 2,  1,   3 },
+	{ }
+};
+
+static struct rcg_desc gsbi5_uart_rcg = {
+	.ctl_reg = 0x2a54,
+	.ns_reg = 0x2a54,
+	.md_reg = 0x2a50,
+	.ctl_bit = 11,
+	.mnctr_en_bit = 8,
+	.mnctr_reset_bit = 7,
+	.mnctr_mode_shift = 5,
+	.pre_div_shift = 3,
+	.src_sel_shift = 0,
+	.n_val_shift = 16,
+	.m_val_shift = 16,
+	.parent_map = gcc_pxo_pll8_map,
+	.freq_tbl = clk_tbl_gsbi_uart,
+};
+
+static struct branch_desc gsbi5_uart_cxc = {
+	.ctl_reg = 0x2a54,
+	.halt_reg = 0x2fd0,
+	.ctl_bit = 9,
+	.halt_bit = 22,
+	.halt_check = BRANCH_HALT,
+};
+
+static struct rcg_desc gsbi6_uart_rcg = {
+	.ctl_reg = 0x2a74,
+	.ns_reg = 0x2a74,
+	.md_reg = 0x2a70,
+	.ctl_bit = 11,
+	.mnctr_en_bit = 8,
+	.mnctr_reset_bit = 7,
+	.mnctr_mode_shift = 5,
+	.pre_div_shift = 3,
+	.src_sel_shift = 0,
+	.n_val_shift = 16,
+	.m_val_shift = 16,
+	.parent_map = gcc_pxo_pll8_map,
+	.freq_tbl = clk_tbl_gsbi_uart,
+};
+
+static struct branch_desc gsbi6_uart_cxc = {
+	.ctl_reg = 0x2a74,
+	.halt_reg = 0x2fd0,
+	.ctl_bit = 9,
+	.halt_bit = 18,
+	.halt_check = BRANCH_HALT,
+};
+
+static struct branch_desc gsbi5_uart_ahb = {
+	.ctl_reg = 0x2a40,
+	.halt_reg = 0x2fd0,
+	.hwcg_reg = 0x2a40,
+	.ctl_bit = 4,
+	.hwcg_bit = 6,
+	.halt_bit = 23,
+	.halt_check = BRANCH_HALT,
+};
+
+static struct freq_tbl clk_tbl_gsbi_qup[] = {
+	{  1100000, PXO,  1, 2, 49 },
+	{  5400000, PXO,  1, 1,  5 },
+	{ 10800000, PXO,  1, 2,  5 },
+	{ 15060000, PLL8, 1, 2, 51 },
+	{ 24000000, PLL8, 4, 1,  4 },
+	{ 25600000, PLL8, 1, 1, 15 },
+	{ 27000000, PXO,  1, 0,  0 },
+	{ 48000000, PLL8, 4, 1,  2 },
+	{ 51200000, PLL8, 1, 2, 15 },
+	{ }
+};
+
+static struct rcg_desc gsbi5_qup_rcg = {
+	.ctl_reg = 0x2a4c,
+	.ns_reg = 0x2a4c,
+	.md_reg = 0x2a48,
+	.ctl_bit = 11,
+	.mnctr_en_bit = 8,
+	.mnctr_reset_bit = 7,
+	.mnctr_mode_shift = 5,
+	.pre_div_shift = 3,
+	.src_sel_shift = 0,
+	.n_val_shift = 16,
+	.m_val_shift = 16,
+	.parent_map = gcc_pxo_pll8_map,
+	.freq_tbl = clk_tbl_gsbi_qup,
+};
+
+static struct branch_desc gsbi5_qup_cxc = {
+	.ctl_reg = 0x2a4c,
+	.halt_reg = 0x2fd0,
+	.ctl_bit = 9,
+	.halt_bit = 20,
+	.halt_check = BRANCH_HALT,
+};
+
+static struct of_clk_match msm_gcc_clk_match[] = {
+	{ .name = "cxo" },
+	{ .name = "pxo" },
+	{ .name = "pll8", .driver_data = &pll8_desc },
+	{ .name = "vpll8", .driver_data = &pll8_vote_desc },
+	{ .name = "gsbi5_uart_rcg", .driver_data = &gsbi5_uart_rcg },
+	{ .name = "gsbi5_uart_cxc", .driver_data = &gsbi5_uart_cxc },
+	{ .name = "gsbi6_uart_rcg", .driver_data = &gsbi6_uart_rcg },
+	{ .name = "gsbi6_uart_cxc", .driver_data = &gsbi6_uart_cxc },
+	{ .name = "gsbi5_uart_ahb", .driver_data = &gsbi5_uart_ahb },
+	{ .name = "gsbi5_qup_rcg", .driver_data = &gsbi5_qup_rcg },
+	{ .name = "gsbi5_qup_cxc", .driver_data = &gsbi5_qup_cxc },
+};
+
+const struct msm_clk_match msm_gcc_clk_matches = {
+	.matches = msm_gcc_clk_match,
+	.size = ARRAY_SIZE(msm_gcc_clk_match)
+};
diff --git a/drivers/clk/msm/internal.h b/drivers/clk/msm/internal.h
index 177bd3b..0b6b9fe 100644
--- a/drivers/clk/msm/internal.h
+++ b/drivers/clk/msm/internal.h
@@ -21,4 +21,6 @@ struct msm_clk_match {
 	size_t size;
 };
 
+extern const struct msm_clk_match msm_gcc_clk_matches;
+
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[RFC/PATCH 10/13] clk: msm: Add support for MSM8960's multimedia clock controller (MMCC)

[Stephen Boyd]

Fill in the data and wire up the multimedia clock controller to
the MSM clock driver. This should allow multimedia device drivers
to control their clocks on 8960 based platforms.

Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 .../devicetree/bindings/clock/qcom,mmcc.txt        |  38 ++++++
 drivers/clk/msm/Kconfig                            |   8 ++
 drivers/clk/msm/Makefile                           |   1 +
 drivers/clk/msm/core.c                             |   3 +
 drivers/clk/msm/internal.h                         |   1 +
 drivers/clk/msm/mmcc-8960.c                        | 142 +++++++++++++++++++++
 6 files changed, 193 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,mmcc.txt
 create mode 100644 drivers/clk/msm/mmcc-8960.c

diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
new file mode 100644
index 0000000..e06577e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -0,0 +1,38 @@
+MSM Multimedia Clock Controller Binding
+-----------------------------------------
+
+Required properties :
+- compatible : shall contain at least "qcom,mmcc" and only one of the
+	       following:
+
+			"qcom,mmcc-8660"
+			"qcom,mmcc-8960"
+
+- reg : shall contain base register location and length
+- clocks : shall contain clocks supplied by the clock controller
+
+Example:
+	clock-controller@4000000 {
+		compatible = "qcom,mmcc-8960", "qcom,mmcc";
+		reg = <0x4000000 0x1000>;
+
+		clocks {
+			pll2: pll2 {
+				#clock-cells = <0>;
+				compatible = "qcom,pll";
+				clocks = <&pxo>;
+			};
+
+			mdp_rcg: mdp_rcg {
+				#clock-cells = <0>;
+				compatible = "qcom,mn8-dyn-clock";
+				clocks = <&pxo>, <&pll2>, <&vpll8>;
+			};
+
+			mdp_cxc: mdp_cxc {
+				#clock-cells = <0>;
+				compatible = "qcom,cxc-clock";
+				clocks = <&mdp_rcg>;
+			};
+		};
+	};
diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig
index 3eaffb6..6147380 100644
--- a/drivers/clk/msm/Kconfig
+++ b/drivers/clk/msm/Kconfig
@@ -11,4 +11,12 @@ config MSM_GCC_8960
 	  Say Y if you want to use peripheral devices such as UART, SPI,
 	  i2c, USB, SD/eMMC, SATA, PCIe, etc.
 
+config MSM_MMCC_8960
+	bool "MSM8960 Multimedia Clock Controller"
+	select MSM_GCC_8960
+	help
+	  Support for the multimedia clock controller on msm8960 devices.
+	  Say Y if you want to support multimedia devices such as display,
+	  graphics, video encode/decode, camera, etc.
+
 endif
diff --git a/drivers/clk/msm/Makefile b/drivers/clk/msm/Makefile
index c785943..ae199f5 100644
--- a/drivers/clk/msm/Makefile
+++ b/drivers/clk/msm/Makefile
@@ -8,3 +8,4 @@ clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-branch.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += core.o
 
 clk-msm-$(CONFIG_MSM_GCC_8960) += gcc-8960.o
+clk-msm-$(CONFIG_MSM_MMCC_8960) += mmcc-8960.o
diff --git a/drivers/clk/msm/core.c b/drivers/clk/msm/core.c
index b1ac8c1..f30aee5 100644
--- a/drivers/clk/msm/core.c
+++ b/drivers/clk/msm/core.c
@@ -176,6 +176,9 @@ static const struct of_device_id msm_cc_match_table[] = {
 #ifdef CONFIG_MSM_GCC_8960
 	{ .compatible = "qcom,gcc-8960", .data = &msm_gcc_clk_matches },
 #endif
+#ifdef CONFIG_MSM_MMCC_8960
+	{ .compatible = "qcom,mmcc-8960", .data = &msm_mmcc_clk_matches },
+#endif
 	{ }
 };
 MODULE_DEVICE_TABLE(of, msm_cc_match_table);
diff --git a/drivers/clk/msm/internal.h b/drivers/clk/msm/internal.h
index 0b6b9fe..77ffc45 100644
--- a/drivers/clk/msm/internal.h
+++ b/drivers/clk/msm/internal.h
@@ -22,5 +22,6 @@ struct msm_clk_match {
 };
 
 extern const struct msm_clk_match msm_gcc_clk_matches;
+extern const struct msm_clk_match msm_mmcc_clk_matches;
 
 #endif
diff --git a/drivers/clk/msm/mmcc-8960.c b/drivers/clk/msm/mmcc-8960.c
new file mode 100644
index 0000000..c57e9cc
--- /dev/null
+++ b/drivers/clk/msm/mmcc-8960.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+
+#include "internal.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+
+static struct pll_desc pll2_desc = {
+	.l_reg = 0x320,
+	.m_reg = 0x324,
+	.n_reg = 0x328,
+	.config_reg = 0x32c,
+	.mode_reg = 0x31c,
+	.status_reg = 0x334,
+	.status_bit = 16,
+};
+
+#define PXO	0
+#define PLL2	1
+#define PLL8	2
+
+static u8 mmcc_pxo_pll2_pll8_map[] = {
+	[PXO]	= 0,
+	[PLL2]	= 1,
+	[PLL8]	= 2,
+};
+
+static struct freq_tbl clk_tbl_mdp[] = {
+	{   9600000, PLL8, 0, 1, 40 },
+	{  13710000, PLL8, 0, 1, 28 },
+	{  27000000, PXO,  0, 0,  0 },
+	{  29540000, PLL8, 0, 1, 13 },
+	{  34910000, PLL8, 0, 1, 11 },
+	{  38400000, PLL8, 0, 1, 10 },
+	{  59080000, PLL8, 0, 2, 13 },
+	{  76800000, PLL8, 0, 1,  5 },
+	{  85330000, PLL8, 0, 2,  9 },
+	{  96000000, PLL8, 0, 1,  4 },
+	{ 128000000, PLL8, 0, 1,  3 },
+	{ 160000000, PLL2, 0, 1,  5 },
+	{ 177780000, PLL2, 0, 2,  9 },
+	{ 200000000, PLL2, 0, 1,  4 },
+	{ 228571000, PLL2, 0, 2,  7 },
+	{ 266667000, PLL2, 0, 1,  3 },
+	{ }
+};
+
+static struct rcg_dyn_desc mdp_rcg = {
+	.ctl_reg = 0xc0,
+	.ns_reg = 0xd0,
+	.md0_reg = 0xc4,
+	.md1_reg = 0xc8,
+	.ctl_bit = 2,
+	.mnctr0_en_bit = 8,
+	.mnctr1_en_bit = 5,
+	.mnctr0_reset_bit = 31,
+	.mnctr1_reset_bit = 30,
+	.mnctr0_mode_shift = 9,
+	.mnctr1_mode_shift = 6,
+	.src0_sel_shift = 3,
+	.src1_sel_shift = 0,
+	.n0_val_shift = 22,
+	.n1_val_shift = 14,
+	.m0_val_shift = 8,
+	.m1_val_shift = 8,
+	.mux_sel_bit = 11,
+	.parent_map = mmcc_pxo_pll2_pll8_map,
+	.freq_tbl = clk_tbl_mdp,
+};
+
+static struct branch_desc mdp_cxc = {
+	.ctl_reg = 0xc0,
+	.halt_reg = 0x1d0,
+	.ctl_bit = 0,
+	.halt_bit = 10,
+	.halt_check = BRANCH_HALT,
+};
+
+static struct freq_tbl clk_tbl_rot[] = {
+	{  27000000, PXO,   1 },
+	{  29540000, PLL8, 13 },
+	{  32000000, PLL8, 12 },
+	{  38400000, PLL8, 10 },
+	{  48000000, PLL8,  8 },
+	{  54860000, PLL8,  7 },
+	{  64000000, PLL8,  6 },
+	{  76800000, PLL8,  5 },
+	{  96000000, PLL8,  4 },
+	{ 100000000, PLL2,  8 },
+	{ 114290000, PLL2,  7 },
+	{ 133330000, PLL2,  6 },
+	{ 160000000, PLL2,  5 },
+	{ 200000000, PLL2,  4 },
+	{ }
+};
+
+static struct rcg_dyn_desc rot_rcg = {
+	.ctl_reg = 0xe0,
+	.ns_reg = 0xe8,
+	.ctl_bit = 2,
+	.pre_div0_shift = 22,
+	.pre_div1_shift = 26,
+	.src0_sel_shift = 16,
+	.src1_sel_shift = 19,
+	.mux_sel_bit = 30,
+	.parent_map = mmcc_pxo_pll2_pll8_map,
+	.freq_tbl = clk_tbl_rot,
+};
+
+static struct branch_desc rot_cxc = {
+	.ctl_reg = 0xe0,
+	.halt_reg = 0x1d0,
+	.ctl_bit = 0,
+	.halt_bit = 15,
+	.halt_check = BRANCH_HALT,
+};
+
+static struct of_clk_match msm_mmcc_clk_match[] = {
+	{ .name = "pll2", .driver_data = &pll2_desc },
+	{ .name = "mdp_rcg", .driver_data = &mdp_rcg },
+	{ .name = "mdp_cxc", .driver_data = &mdp_cxc },
+	{ .name = "rot_rcg", .driver_data = &rot_rcg },
+	{ .name = "rot_cxc", .driver_data = &rot_cxc },
+};
+
+const struct msm_clk_match msm_mmcc_clk_matches = {
+	.matches = msm_mmcc_clk_match,
+	.size = ARRAY_SIZE(msm_mmcc_clk_match)
+};
-- 
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