* [PATCH 2/4] ARM: msm: Re-organize platsmp to make it extensible
2013-06-28 23:25 [PATCH 0/4] Add SMP support for MSM8660, MSM8960 and MSM8974 Rohit Vaswani
@ 2013-06-28 23:26 ` Rohit Vaswani
2013-06-28 23:26 ` [PATCH 3/4] ARM: msm: Add SMP support for 8960 Rohit Vaswani
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Rohit Vaswani @ 2013-06-28 23:26 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Rob Landley, Russell King, David Brown,
Daniel Walker, Bryan Huntsman
Cc: Rohit Vaswani, linux-doc, linux-kernel, devicetree-discuss,
linux-arm-msm
This makes it easy to add SMP support for new targets
by adding cpus property and the release sequence.
We add the enable-method property for the cpus property to
specify which release sequence to use.
While at it, add the 8660 cpus bindings to make SMP work.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 6 ++
Documentation/devicetree/bindings/arm/msm/scss.txt | 15 ++++
arch/arm/boot/dts/msm8660-surf.dts | 23 +++++-
arch/arm/mach-msm/platsmp.c | 96 ++++++++++++++++------
4 files changed, 116 insertions(+), 24 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/msm/scss.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index f32494d..327aad2 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -44,6 +44,12 @@ For the ARM architecture every CPU node must contain the following properties:
"marvell,mohawk"
"marvell,xsc3"
"marvell,xscale"
+ "qcom,scorpion"
+- enable-method: Specifies the method used to enable or take the secondary cores
+ out of reset. This allows different reset sequence for
+ different types of cpus.
+ This should be one of:
+ "qcom,scss"
Example:
diff --git a/Documentation/devicetree/bindings/arm/msm/scss.txt b/Documentation/devicetree/bindings/arm/msm/scss.txt
new file mode 100644
index 0000000..21c3e26
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/scss.txt
@@ -0,0 +1,15 @@
+* SCSS - Scorpion Sub-system
+
+Properties
+
+- compatible : Should contain "qcom,scss".
+
+- reg: Specifies the base address for the SCSS registers used for
+ booting up secondary cores.
+
+Example:
+
+ scss@902000 {
+ compatible = "qcom,scss";
+ reg = <0x00902000 0x2000>;
+ };
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index cdc010e..203e51a 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -7,6 +7,22 @@
compatible = "qcom,msm8660-surf", "qcom,msm8660";
interrupt-parent = <&intc>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,scorpion";
+ device_type = "cpu";
+ enable-method = "qcom,scss";
+
+ cpu@0 {
+ reg = <0>;
+ };
+
+ cpu@1 {
+ reg = <1>;
+ };
+ };
+
intc: interrupt-controller@2080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;
@@ -37,7 +53,12 @@
#interrupt-cells = <2>;
};
- serial@19c40000 {
+ scss@902000 {
+ compatible = "qcom,scss";
+ reg = <0x00902000 0x2000>;
+ };
+
+ serial@19c400000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 7d48759..17022e0 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -13,6 +13,8 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/jiffies.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/smp.h>
#include <linux/io.h>
@@ -38,7 +40,7 @@ static inline int get_core_count(void)
return ((read_cpuid_id() >> 4) & 3) + 1;
}
-static void __cpuinit msm_secondary_init(unsigned int cpu)
+static void msm_secondary_init(unsigned int cpu)
{
/*
* Synchronise with the boot thread.
@@ -47,35 +49,63 @@ static void __cpuinit msm_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
-static __cpuinit void prepare_cold_cpu(unsigned int cpu)
+static int scorpion_release_secondary(void)
{
- int ret;
- ret = scm_set_boot_addr(virt_to_phys(secondary_startup),
- SCM_FLAG_COLDBOOT_CPU1);
- if (ret == 0) {
- void __iomem *sc1_base_ptr;
- sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
- if (sc1_base_ptr) {
- writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
- writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
- writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
- iounmap(sc1_base_ptr);
- }
- } else
- printk(KERN_DEBUG "Failed to set secondary core boot "
- "address\n");
+ void __iomem *sc1_base_ptr;
+ struct device_node *dn = NULL;
+
+ dn = of_find_compatible_node(dn, NULL, "qcom,scss");
+ if (!dn) {
+ pr_err("%s: Missing scss node in device tree\n", __func__);
+ return -ENXIO;
+ }
+
+ sc1_base_ptr = of_iomap(dn, 0);
+ if (sc1_base_ptr) {
+ writel_relaxed(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
+ writel_relaxed(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
+ writel_relaxed(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
+ mb();
+ iounmap(sc1_base_ptr);
+ } else {
+ return -ENOMEM;
+ }
+
+ return 0;
}
-static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static DEFINE_PER_CPU(int, cold_boot_done);
+
+static void boot_cold_cpu(unsigned int cpu)
{
- static int cold_boot_done;
+ const char *enable_method;
+ struct device_node *dn = NULL;
- /* Only need to bring cpu out of reset this way once */
- if (cold_boot_done == false) {
- prepare_cold_cpu(cpu);
- cold_boot_done = true;
+ dn = of_find_node_by_name(dn, "cpus");
+ if (!dn) {
+ pr_err("%s: Missing node cpus in device tree\n", __func__);
+ return;
}
+ enable_method = of_get_property(dn, "enable-method", NULL);
+ if (!enable_method) {
+ pr_err("%s: cpus node is missing enable-method property\n",
+ __func__);
+ } else if (!strcmp(enable_method, "qcom,scss")) {
+ if (per_cpu(cold_boot_done, cpu) == false) {
+ scorpion_release_secondary();
+ per_cpu(cold_boot_done, cpu) = true;
+ }
+ } else {
+ pr_err("%s: Invalid enable-method property: %s\n",
+ __func__, enable_method);
+ }
+}
+
+static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ boot_cold_cpu(cpu);
+
/*
* set synchronisation state between this boot processor
* and the secondary one
@@ -118,8 +148,28 @@ static void __init msm_smp_init_cpus(void)
set_cpu_possible(i, true);
}
+static const int cold_boot_flags[] __initconst = {
+ 0,
+ SCM_FLAG_COLDBOOT_CPU1,
+};
+
static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
{
+ int cpu, map;
+ unsigned int flags = 0;
+
+ for_each_present_cpu(cpu) {
+ map = cpu_logical_map(cpu);
+ if (map > ARRAY_SIZE(cold_boot_flags)) {
+ set_cpu_present(cpu, false);
+ __WARN();
+ continue;
+ }
+ flags |= cold_boot_flags[map];
+ }
+
+ if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags))
+ pr_warn("Failed to set CPU boot address\n");
}
struct smp_operations msm_smp_ops __initdata = {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/4] ARM: msm: Add SMP support for 8960
2013-06-28 23:25 [PATCH 0/4] Add SMP support for MSM8660, MSM8960 and MSM8974 Rohit Vaswani
2013-06-28 23:26 ` [PATCH 2/4] ARM: msm: Re-organize platsmp to make it extensible Rohit Vaswani
@ 2013-06-28 23:26 ` Rohit Vaswani
2013-06-28 23:26 ` [PATCH 4/4] ARM: msm: Add support for 8974 SMP Rohit Vaswani
2013-07-15 20:37 ` [PATCH 0/4] Add SMP support for MSM8660, MSM8960 and MSM8974 Rohit Vaswani
3 siblings, 0 replies; 5+ messages in thread
From: Rohit Vaswani @ 2013-06-28 23:26 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Rob Landley, Russell King, David Brown,
Daniel Walker, Bryan Huntsman
Cc: Rohit Vaswani, linux-doc, linux-kernel, devicetree-discuss,
linux-arm-msm
Add the cpus bindings and the Krait release sequence
to make SMP work for MSM8960
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 +
Documentation/devicetree/bindings/arm/msm/kpss.txt | 16 ++++++
arch/arm/boot/dts/msm8960-cdp.dts | 22 +++++++++
arch/arm/mach-msm/platsmp.c | 57 ++++++++++++++++++++++
arch/arm/mach-msm/scm-boot.h | 8 +--
5 files changed, 102 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/msm/kpss.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 327aad2..1132eac 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -45,11 +45,13 @@ For the ARM architecture every CPU node must contain the following properties:
"marvell,xsc3"
"marvell,xscale"
"qcom,scorpion"
+ "qcom,krait"
- enable-method: Specifies the method used to enable or take the secondary cores
out of reset. This allows different reset sequence for
different types of cpus.
This should be one of:
"qcom,scss"
+ "qcom,kpssv1"
Example:
diff --git a/Documentation/devicetree/bindings/arm/msm/kpss.txt b/Documentation/devicetree/bindings/arm/msm/kpss.txt
new file mode 100644
index 0000000..7272340
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/kpss.txt
@@ -0,0 +1,16 @@
+* KPSS - Krait Processor Sub-system
+
+Properties
+
+- compatible : Should contain "qcom,kpss".
+
+- reg: Specifies the base address for the KPSS registers used for
+ booting up secondary cores.
+
+Example:
+
+ kpss@2088000 {
+ compatible = "qcom,kpss";
+ reg = <0x02088000 0x1000
+ 0x02098000 0x2000>;
+ };
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
index db2060c..8c82d5e 100644
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -7,6 +7,22 @@
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
interrupt-parent = <&intc>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,krait";
+ device_type = "cpu";
+ enable-method = "qcom,kpssv1";
+
+ cpu@0 {
+ reg = <0>;
+ };
+
+ cpu@1 {
+ reg = <1>;
+ };
+ };
+
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@@ -37,6 +53,12 @@
reg = <0xfd510000 0x4000>;
};
+ kpss@2088000 {
+ compatible = "qcom,kpss";
+ reg = <0x02088000 0x1000
+ 0x02098000 0x2000>;
+ };
+
serial@16440000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x16440000 0x1000>,
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 17022e0..82eb079 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -74,6 +74,56 @@ static int scorpion_release_secondary(void)
return 0;
}
+static int msm8960_release_secondary(unsigned int cpu)
+{
+ void __iomem *reg;
+ struct device_node *dn = NULL;
+
+ if (cpu == 0 || cpu >= num_possible_cpus())
+ return -EINVAL;
+
+ dn = of_find_compatible_node(dn, NULL, "qcom,kpss");
+ if (!dn) {
+ pr_err("%s : Missing kpss node from device tree\n", __func__);
+ return -ENXIO;
+ }
+
+ reg = of_iomap(dn, cpu);
+ if (!reg)
+ return -ENOMEM;
+
+ pr_debug("Starting secondary CPU %d\n", cpu);
+
+ /* Turn on CPU Rail */
+ writel_relaxed(0xA4, reg+0x1014);
+ mb();
+ udelay(512);
+
+ /* Krait bring-up sequence */
+ writel_relaxed(0x109, reg+0x04);
+ writel_relaxed(0x101, reg+0x04);
+ mb();
+ ndelay(300);
+
+ writel_relaxed(0x121, reg+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x120, reg+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x100, reg+0x04);
+ mb();
+ udelay(100);
+
+ writel_relaxed(0x180, reg+0x04);
+ mb();
+
+ iounmap(reg);
+ return 0;
+}
+
static DEFINE_PER_CPU(int, cold_boot_done);
static void boot_cold_cpu(unsigned int cpu)
@@ -96,6 +146,11 @@ static void boot_cold_cpu(unsigned int cpu)
scorpion_release_secondary();
per_cpu(cold_boot_done, cpu) = true;
}
+ } else if (!strcmp(enable_method, "qcom,kpssv1")) {
+ if (per_cpu(cold_boot_done, cpu) == false) {
+ msm8960_release_secondary(cpu);
+ per_cpu(cold_boot_done, cpu) = true;
+ }
} else {
pr_err("%s: Invalid enable-method property: %s\n",
__func__, enable_method);
@@ -151,6 +206,8 @@ static void __init msm_smp_init_cpus(void)
static const int cold_boot_flags[] __initconst = {
0,
SCM_FLAG_COLDBOOT_CPU1,
+ SCM_FLAG_COLDBOOT_CPU2,
+ SCM_FLAG_COLDBOOT_CPU3,
};
static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h
index 7be32ff..6aabb24 100644
--- a/arch/arm/mach-msm/scm-boot.h
+++ b/arch/arm/mach-msm/scm-boot.h
@@ -13,9 +13,11 @@
#define __MACH_SCM_BOOT_H
#define SCM_BOOT_ADDR 0x1
-#define SCM_FLAG_COLDBOOT_CPU1 0x1
-#define SCM_FLAG_WARMBOOT_CPU1 0x2
-#define SCM_FLAG_WARMBOOT_CPU0 0x4
+#define SCM_FLAG_COLDBOOT_CPU1 0x01
+#define SCM_FLAG_COLDBOOT_CPU2 0x08
+#define SCM_FLAG_COLDBOOT_CPU3 0x20
+#define SCM_FLAG_WARMBOOT_CPU0 0x04
+#define SCM_FLAG_WARMBOOT_CPU1 0x02
int scm_set_boot_addr(phys_addr_t addr, int flags);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 4/4] ARM: msm: Add support for 8974 SMP
2013-06-28 23:25 [PATCH 0/4] Add SMP support for MSM8660, MSM8960 and MSM8974 Rohit Vaswani
2013-06-28 23:26 ` [PATCH 2/4] ARM: msm: Re-organize platsmp to make it extensible Rohit Vaswani
2013-06-28 23:26 ` [PATCH 3/4] ARM: msm: Add SMP support for 8960 Rohit Vaswani
@ 2013-06-28 23:26 ` Rohit Vaswani
2013-07-15 20:37 ` [PATCH 0/4] Add SMP support for MSM8660, MSM8960 and MSM8974 Rohit Vaswani
3 siblings, 0 replies; 5+ messages in thread
From: Rohit Vaswani @ 2013-06-28 23:26 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Rob Landley, Russell King, David Brown,
Daniel Walker, Bryan Huntsman
Cc: Rohit Vaswani, linux-doc, linux-kernel, devicetree-discuss,
linux-arm-msm
Add the cpus bindings and the Kraitv2 release sequence
to make SMP work for 2 cores on MSM8974.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm/boot/dts/msm8974.dts | 23 ++++++++
arch/arm/mach-msm/board-dt-8974.c | 3 +
arch/arm/mach-msm/platsmp.c | 79 ++++++++++++++++++++++++++
4 files changed, 106 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 1132eac..7c3c677 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -52,6 +52,7 @@ For the ARM architecture every CPU node must contain the following properties:
This should be one of:
"qcom,scss"
"qcom,kpssv1"
+ "qcom,kpssv2"
Example:
diff --git a/arch/arm/boot/dts/msm8974.dts b/arch/arm/boot/dts/msm8974.dts
index c31c097..ef35a9b 100644
--- a/arch/arm/boot/dts/msm8974.dts
+++ b/arch/arm/boot/dts/msm8974.dts
@@ -7,6 +7,22 @@
compatible = "qcom,msm8974";
interrupt-parent = <&intc>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,krait";
+ device_type = "cpu";
+ enable-method = "qcom,kpssv2";
+
+ cpu@0 {
+ reg = <0>;
+ };
+
+ cpu@1 {
+ reg = <1>;
+ };
+ };
+
intc: interrupt-controller@f9000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@@ -23,4 +39,11 @@
<1 1 0xf08>;
clock-frequency = <19200000>;
};
+
+ kpss@f9012000 {
+ compatible = "qcom,kpss";
+ reg = <0xf9012000 0x1000>,
+ <0xf9088000 0x1000>,
+ <0xf9098000 0x1000>;
+ };
};
diff --git a/arch/arm/mach-msm/board-dt-8974.c b/arch/arm/mach-msm/board-dt-8974.c
index d7f84f2..06119f9 100644
--- a/arch/arm/mach-msm/board-dt-8974.c
+++ b/arch/arm/mach-msm/board-dt-8974.c
@@ -13,11 +13,14 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
+#include "common.h"
+
static const char * const msm8974_dt_match[] __initconst = {
"qcom,msm8974",
NULL
};
DT_MACHINE_START(MSM8974_DT, "Qualcomm MSM (Flattened Device Tree)")
+ .smp = smp_ops(msm_smp_ops),
.dt_compat = msm8974_dt_match,
MACHINE_END
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 82eb079..0fdae69 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -124,6 +124,80 @@ static int msm8960_release_secondary(unsigned int cpu)
return 0;
}
+static int msm8974_release_secondary(unsigned int cpu)
+{
+ void __iomem *reg;
+ void __iomem *l2_saw_base;
+ struct device_node *dn = NULL;
+ unsigned apc_pwr_gate_ctl = 0x14;
+ unsigned reg_val;
+
+ if (cpu == 0 || cpu >= num_possible_cpus())
+ return -EINVAL;
+
+ dn = of_find_compatible_node(dn, NULL, "qcom,kpss");
+ if (!dn) {
+ pr_err("%s : Missing kpss node from device tree\n", __func__);
+ return -ENXIO;
+ }
+
+ reg = of_iomap(dn, cpu+1);
+ if (!reg)
+ return -ENOMEM;
+
+ pr_debug("Starting secondary CPU %d\n", cpu);
+
+ /* Turn on the BHS, turn off LDO Bypass and power down LDO */
+ reg_val = 0x403f0001;
+ writel_relaxed(reg_val, reg + apc_pwr_gate_ctl);
+
+ /* complete the above write before the delay */
+ mb();
+ /* wait for the bhs to settle */
+ udelay(1);
+
+ /* Turn on BHS segments */
+ reg_val |= 0x3f << 1;
+ writel_relaxed(reg_val, reg + apc_pwr_gate_ctl);
+
+ /* complete the above write before the delay */
+ mb();
+ /* wait for the bhs to settle */
+ udelay(1);
+
+ /* Finally turn on the bypass so that BHS supplies power */
+ reg_val |= 0x3f << 8;
+ writel_relaxed(reg_val, reg + apc_pwr_gate_ctl);
+
+ /* enable max phases */
+ l2_saw_base = of_iomap(dn, 0);
+ if (!l2_saw_base) {
+ return -ENOMEM;
+ }
+ writel_relaxed(0x10003, l2_saw_base + 0x1c);
+ mb();
+ udelay(50);
+
+ iounmap(l2_saw_base);
+
+ writel_relaxed(0x021, reg+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x020, reg+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x000, reg+0x04);
+ mb();
+
+ writel_relaxed(0x080, reg+0x04);
+ mb();
+
+ iounmap(reg);
+ return 0;
+}
+
static DEFINE_PER_CPU(int, cold_boot_done);
static void boot_cold_cpu(unsigned int cpu)
@@ -151,6 +225,11 @@ static void boot_cold_cpu(unsigned int cpu)
msm8960_release_secondary(cpu);
per_cpu(cold_boot_done, cpu) = true;
}
+ } else if (!strcmp(enable_method, "qcom,kpssv2")) {
+ if (per_cpu(cold_boot_done, cpu) == false) {
+ msm8974_release_secondary(cpu);
+ per_cpu(cold_boot_done, cpu) = true;
+ }
} else {
pr_err("%s: Invalid enable-method property: %s\n",
__func__, enable_method);
--
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 0/4] Add SMP support for MSM8660, MSM8960 and MSM8974
2013-06-28 23:25 [PATCH 0/4] Add SMP support for MSM8660, MSM8960 and MSM8974 Rohit Vaswani
` (2 preceding siblings ...)
2013-06-28 23:26 ` [PATCH 4/4] ARM: msm: Add support for 8974 SMP Rohit Vaswani
@ 2013-07-15 20:37 ` Rohit Vaswani
3 siblings, 0 replies; 5+ messages in thread
From: Rohit Vaswani @ 2013-07-15 20:37 UTC (permalink / raw)
To: Rohit Vaswani
Cc: Grant Likely, Rob Herring, Rob Landley, Russell King, David Brown,
Daniel Walker, Bryan Huntsman, linux-doc, linux-kernel,
devicetree-discuss, linux-arm-msm
ping ?
On 6/28/2013 4:25 PM, Rohit Vaswani wrote:
> This series re-organizes the platsmp.c and adds SMP support for
> MSM8660, MSM8960 and MSM8974.
> We convert to using the cpus property in device tree and
> add a "enable-method" property for arm32.
> This helps select the appropriate release sequence for the
> secondary cores based on the cpu.
>
> Rohit Vaswani (4):
> ARM: msm: Remove pen_release usage
> ARM: msm: Re-organize platsmp to make it extensible
> ARM: msm: Add SMP support for 8960
> ARM: msm: Add support for 8974 SMP
>
> Documentation/devicetree/bindings/arm/cpus.txt | 9 +
> Documentation/devicetree/bindings/arm/msm/kpss.txt | 16 ++
> Documentation/devicetree/bindings/arm/msm/scss.txt | 15 ++
> arch/arm/boot/dts/msm8660-surf.dts | 23 +-
> arch/arm/boot/dts/msm8960-cdp.dts | 22 ++
> arch/arm/boot/dts/msm8974.dts | 23 ++
> arch/arm/mach-msm/board-dt-8974.c | 3 +
> arch/arm/mach-msm/headsmp.S | 41 ----
> arch/arm/mach-msm/hotplug.c | 31 +--
> arch/arm/mach-msm/platsmp.c | 265 ++++++++++++++++-----
> arch/arm/mach-msm/scm-boot.h | 8 +-
> 11 files changed, 330 insertions(+), 126 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/msm/kpss.txt
> create mode 100644 Documentation/devicetree/bindings/arm/msm/scss.txt
> delete mode 100644 arch/arm/mach-msm/headsmp.S
>
Thanks,
Rohit Vaswani
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^ permalink raw reply [flat|nested] 5+ messages in thread