[PATCH] Documentation: Add device tree binding file for MOXA ART SoCs interrupt controller

[PATCH] Documentation: Add device tree binding file for MOXA ART SoCs interrupt controller

[Jonas Jensen]

Add binding document for MOXA ART SoCs interrupt controller.

Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com>
---

Notes:
    The MOXA ART irqchip driver was added without accompanying devicetree document.
    ( in next-20130716   drivers/irqchip/irq-moxart.c )
    
    Applies to next-20130716

 .../interrupt-controller/moxa,moxart-ic.txt        | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/moxa,moxart-ic.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/moxa,moxart-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/moxa,moxart-ic.txt
new file mode 100644
index 0000000..58f1fe1
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/moxa,moxart-ic.txt
@@ -0,0 +1,28 @@
+* MOXA ART Interrupt Controller
+
+MOXA ART Interrupt Controller (moxart-ic) is used on MOXA ART SoCs
+and supports 32 non-configurable number of interrupts
+
+Main node required properties:
+
+- compatible : "moxa,moxart-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The type shall be a <u32> and the value shall be 2.
+
+  The first cell contains the interrupt number in the range [0-31].
+  The second cell contains the interrupt type
+
+- reg: physical base address and size of the intc registers map.
+- interrupt-mask: Specifies if the interrupt is edge or level-triggered
+  each bit represent an interrupt 0-31 where 1 signify edge
+
+Example:
+
+	intc: interrupt-controller@98800000 {
+		compatible = "moxa,moxart-ic";
+		reg = <0x98800000 0x38>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-mask = <0x00080000>;
+	};
-- 
1.8.2.1

Re: [PATCH] Documentation: Add device tree binding file for MOXA ART SoCs interrupt controller

[Mark Rutland]

On Thu, Jul 18, 2013 at 09:50:26AM +0100, Jonas Jensen wrote:
> Add binding document for MOXA ART SoCs interrupt controller.
> 
> Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com>
> ---
> 
> Notes:
>     The MOXA ART irqchip driver was added without accompanying devicetree document.
>     ( in next-20130716   drivers/irqchip/irq-moxart.c )

Aaargh. That should not have happened >:(

>     
>     Applies to next-20130716
> 
>  .../interrupt-controller/moxa,moxart-ic.txt        | 28 ++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/moxa,moxart-ic.txt
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/moxa,moxart-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/moxa,moxart-ic.txt
> new file mode 100644
> index 0000000..58f1fe1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/moxa,moxart-ic.txt
> @@ -0,0 +1,28 @@
> +* MOXA ART Interrupt Controller
> +
> +MOXA ART Interrupt Controller (moxart-ic) is used on MOXA ART SoCs
> +and supports 32 non-configurable number of interrupts
> +
> +Main node required properties:
> +
> +- compatible : "moxa,moxart-ic"
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> +  interrupt source. The type shall be a <u32> and the value shall be 2.
> +
> +  The first cell contains the interrupt number in the range [0-31].
> +  The second cell contains the interrupt type
> +
> +- reg: physical base address and size of the intc registers map.
> +- interrupt-mask: Specifies if the interrupt is edge or level-triggered
> +  each bit represent an interrupt 0-31 where 1 signify edge

For the GIC, this gets descrbied in the interrupt sepcifier rather than
on the interrupt controller's root node. Is there a reason to do this
differently here?

Thanks,
Mark.

> +
> +Example:
> +
> +	intc: interrupt-controller@98800000 {
> +		compatible = "moxa,moxart-ic";
> +		reg = <0x98800000 0x38>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-mask = <0x00080000>;
> +	};
> -- 
> 1.8.2.1
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
> 

Re: [PATCH] Documentation: Add device tree binding file for MOXA ART SoCs interrupt controller

[Jonas Jensen]

Hi Mark,

On 2 August 2013 11:35, Mark Rutland <mark.rutland@arm.com> wrote:
>>     The MOXA ART irqchip driver was added without accompanying devicetree document.
>>     ( in next-20130716   drivers/irqchip/irq-moxart.c )
>
> Aaargh. That should not have happened >:(

Sorry about this, my plan was to submit all documents along with
moxart platform support. At the time I did not know it is more normal
to push the binding along with the driver.

>> +- interrupt-mask: Specifies if the interrupt is edge or level-triggered
>> +  each bit represent an interrupt 0-31 where 1 signify edge
>
> For the GIC, this gets descrbied in the interrupt sepcifier rather than
> on the interrupt controller's root node. Is there a reason to do this
> differently here?

The reason is, IRQ types must be written to the controller as two u32
registers (IRQ_MODE_REG and IRQ_LEVEL_REG). I could not find an easier
way (that uses generic things) to do it.

It's true that "interrupt-mask" is redundant, DT "interrupts" hold the
same information. I just never found nice way to collect it from DT.

See registers written on line 111:
http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-moxart.c#n111


Best regards,
Jonas

Re: [PATCH] Documentation: Add device tree binding file for MOXA ART SoCs interrupt controller

[Arnd Bergmann]

On Thursday 08 August 2013, Jonas Jensen wrote:
> It's true that "interrupt-mask" is redundant, DT "interrupts" hold the
> same information. I just never found nice way to collect it from DT.
> 
> See registers written on line 111:
> http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-moxart.c#n111
> 

Can't you just update the register whenever an interrupt gets mapped?

All unused interrupts can start out as edge triggered.

	Arnd