[RESEND PATCH 0/4] Enable ethernet support for SOCFPGA

[RESEND PATCH 0/4] Enable ethernet support for SOCFPGA

[dinguyen]

From: Dinh Nguyen <dinguyen@altera.com>

Hello,

These 4 patches are meant to enable ethernet and SD/MMC for the SOCFPGA
platform.

patch (1/4): Adds select ARM_TWD for the platform
patch (2/4): Add platform specific initialization for the ethernet controller.
patch (3/4): Commit 25c83b5c2 added "snps,phy-addr" for getting the PHY addr.
        Set the ethernet clocks to be emac_0_clk and emac_1_clk so it be gated.
patch (4/4): Update defconfig to support SD/MMC, ethernet, EXT3 and NFS.

Thanks,

Dinh Nguyen (4):
  arm: socfpga: Enable ARM_TWD for socfpga
  arm: socfpga: Add platform initialization for ethernet
  ARM: socfpga: dts: Fix entries for the ethernet entries.
  arm: socfpga: Add support for SD/MMC and ethernet to defconfig

 arch/arm/boot/dts/socfpga.dtsi         |    4 +-
 arch/arm/boot/dts/socfpga_cyclone5.dts |    2 +-
 arch/arm/configs/socfpga_defconfig     |    8 +++
 arch/arm/mach-socfpga/Kconfig          |    1 +
 arch/arm/mach-socfpga/core.h           |    8 +++
 arch/arm/mach-socfpga/socfpga.c        |   85 +++++++++++++++++++++++++++++++-
 6 files changed, 104 insertions(+), 4 deletions(-)

CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: devicetree@vger.kernel.org
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>

-- 
1.7.9.5

[RESEND PATCH 1/4] arm: socfpga: Enable ARM_TWD for socfpga

[dinguyen]

From: Dinh Nguyen <dinguyen@altera.com>

Update Kconfig to enable TWD.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
Reviewed-by: Pavel Machek <pavel@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: devicetree@vger.kernel.org
Cc: Pavel Machek <pavel@denx.de>
Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
---
 arch/arm/mach-socfpga/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index dd86db4..efad818 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -11,6 +11,7 @@ config ARCH_SOCFPGA
 	select GENERIC_CLOCKEVENTS
 	select GPIO_PL061 if GPIOLIB
 	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD if LOCAL_TIMERS
 	select HAVE_SMP
 	select MFD_SYSCON
 	select SPARSE_IRQ
-- 
1.7.9.5

Re: [RESEND PATCH 1/4] arm: socfpga: Enable ARM_TWD for socfpga

[Mark Rutland]

On Mon, Aug 05, 2013 at 10:58:42PM +0100, dinguyen@altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Update Kconfig to enable TWD.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> Reviewed-by: Pavel Machek <pavel@denx.de>
> CC: Arnd Bergmann <arnd@arndb.de>
> CC: Olof Johansson <olof@lixom.net>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Ian Campbell <ian.campbell@citrix.com>
> Cc: devicetree@vger.kernel.org
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> ---
>  arch/arm/mach-socfpga/Kconfig |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index dd86db4..efad818 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -11,6 +11,7 @@ config ARCH_SOCFPGA
>  	select GENERIC_CLOCKEVENTS
>  	select GPIO_PL061 if GPIOLIB
>  	select HAVE_ARM_SCU
> +	select HAVE_ARM_TWD if LOCAL_TIMERS

With Stephen Boyd's local timer API removal [1], LOCAL_TIMERS is
disappearing. I believe that you should just select HAVE_ARM_TWD.

Thanks,
Mark.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/179983.html

Re: [RESEND PATCH 1/4] arm: socfpga: Enable ARM_TWD for socfpga

[Dinh Nguyen]

On Tue, 2013-08-06 at 14:35 +0100, Mark Rutland wrote:
> On Mon, Aug 05, 2013 at 10:58:42PM +0100, dinguyen@altera.com wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Update Kconfig to enable TWD.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> > Reviewed-by: Pavel Machek <pavel@denx.de>
> > CC: Arnd Bergmann <arnd@arndb.de>
> > CC: Olof Johansson <olof@lixom.net>
> > Cc: Rob Herring <rob.herring@calxeda.com>
> > Cc: Pawel Moll <pawel.moll@arm.com>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Stephen Warren <swarren@wwwdotorg.org>
> > Cc: Ian Campbell <ian.campbell@citrix.com>
> > Cc: devicetree@vger.kernel.org
> > Cc: Pavel Machek <pavel@denx.de>
> > Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> > ---
> >  arch/arm/mach-socfpga/Kconfig |    1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> > index dd86db4..efad818 100644
> > --- a/arch/arm/mach-socfpga/Kconfig
> > +++ b/arch/arm/mach-socfpga/Kconfig
> > @@ -11,6 +11,7 @@ config ARCH_SOCFPGA
> >  	select GENERIC_CLOCKEVENTS
> >  	select GPIO_PL061 if GPIOLIB
> >  	select HAVE_ARM_SCU
> > +	select HAVE_ARM_TWD if LOCAL_TIMERS
> 
> With Stephen Boyd's local timer API removal [1], LOCAL_TIMERS is
> disappearing. I believe that you should just select HAVE_ARM_TWD.

Thanks Mark, will fix.

Dinh
> 
> Thanks,
> Mark.
> 
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/179983.html
> 

Re: [RESEND PATCH 1/4] arm: socfpga: Enable ARM_TWD for socfpga

[Pavel Machek]

On Mon 2013-08-05 16:58:42, dinguyen@altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Update Kconfig to enable TWD.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> Reviewed-by: Pavel Machek <pavel@denx.de>

Tested-by: Pavel Machek <pavel@denx.de>

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[RESEND PATCH 2/4] arm: socfpga: Add platform initialization for ethernet

[dinguyen]

From: Dinh Nguyen <dinguyen@altera.com>

Use the PHYLIB to set the correct clock and skew values to the Micrel PHY. Add
platform specific intilization to put the STMMAC ethernet controller into the
correct PHY mode.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: devicetree@vger.kernel.org
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
---
 arch/arm/mach-socfpga/core.h    |    8 ++++
 arch/arm/mach-socfpga/socfpga.c |   85 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 92 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 572b8f7..505b8fe5 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -28,6 +28,14 @@
 #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
 #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
 
+#define SYSMGR_EMACGRP_CTRL_OFFSET 0x60
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
+
 extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index bfce964..abbde76 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -16,10 +16,14 @@
  */
 #include <linux/clk-provider.h>
 #include <linux/irqchip.h>
+#include <linux/micrel_phy.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/of_net.h>
 #include <linux/of_platform.h>
 #include <linux/reboot.h>
+#include <linux/stmmac.h>
+#include <linux/phy.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -33,6 +37,22 @@ void __iomem *rst_manager_base_addr;
 void __iomem *clk_mgr_base_addr;
 unsigned long cpu1start_addr;
 
+static int stmmac_plat_init(struct platform_device *pdev);
+
+static struct plat_stmmacenet_data stmmacenet0_data = {
+	.init = &stmmac_plat_init,
+};
+
+static struct plat_stmmacenet_data stmmacenet1_data = {
+	.init = &stmmac_plat_init,
+};
+
+static const struct of_dev_auxdata socfpga_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff700000, NULL, &stmmacenet0_data),
+	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff702000, NULL, &stmmacenet1_data),
+	{/* sentinel */}
+};
+
 static struct map_desc scu_io_desc __initdata = {
 	.virtual	= SOCFPGA_SCU_VIRT_BASE,
 	.pfn		= 0, /* run-time */
@@ -58,6 +78,65 @@ static void __init socfpga_scu_map_io(void)
 	iotable_init(&scu_io_desc, 1);
 }
 
+static int ksz9021rlrn_phy_fixup(struct phy_device *phydev)
+{
+	if (IS_BUILTIN(CONFIG_PHYLIB)) {
+		/* min rx data delay */
+		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
+			MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000);
+		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
+
+		/* max rx/tx clock delay, min rx/tx control delay */
+		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
+			MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000);
+		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xa0d0);
+		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 0x104);
+	}
+
+	return 0;
+}
+
+static int stmmac_plat_init(struct platform_device *pdev)
+{
+	u32 ctrl, val, shift;
+	int phymode;
+
+	if (of_machine_is_compatible("altr,socfpga-vt"))
+		return 0;
+
+	phymode = of_get_phy_mode(pdev->dev.of_node);
+
+	switch (phymode) {
+	case PHY_INTERFACE_MODE_RGMII:
+		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+		break;
+	case PHY_INTERFACE_MODE_MII:
+	case PHY_INTERFACE_MODE_GMII:
+		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+		break;
+	default:
+		pr_err("%s bad phy mode %d", __func__, phymode);
+		return -EINVAL;
+	}
+
+	if (&stmmacenet1_data == pdev->dev.platform_data)
+		shift = SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH;
+	else if (&stmmacenet0_data == pdev->dev.platform_data)
+		shift = 0;
+	else {
+		pr_err("%s unexpected platform data pointer\n", __func__);
+		return -EINVAL;
+	}
+
+	ctrl = readl(sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET);
+	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << shift);
+	ctrl |= (val << shift);
+
+	writel(ctrl, (sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET));
+
+	return 0;
+}
+
 static void __init socfpga_map_io(void)
 {
 	socfpga_scu_map_io();
@@ -106,9 +185,13 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 static void __init socfpga_cyclone5_init(void)
 {
 	l2x0_of_init(0, ~0UL);
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table,
+		socfpga_auxdata_lookup, NULL);
 	of_clk_init(NULL);
 	socfpga_init_clocks();
+	if (IS_BUILTIN(CONFIG_PHYLIB))
+		phy_register_fixup_for_uid(PHY_ID_KSZ9021RLRN,
+			MICREL_PHY_ID_MASK, ksz9021rlrn_phy_fixup);
 }
 
 static const char *altera_dt_match[] = {
-- 
1.7.9.5

Re: [RESEND PATCH 2/4] arm: socfpga: Add platform initialization for ethernet

[Pavel Machek]

Hi!

> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Use the PHYLIB to set the correct clock and skew values to the Micrel PHY. Add
> platform specific intilization to put the STMMAC ethernet controller into the
> correct PHY mode.
> 
...
>  arch/arm/mach-socfpga/core.h    |    8 ++++
>  arch/arm/mach-socfpga/socfpga.c |   85 ++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 92 insertions(+), 1 deletion(-)

When I tried to apply it on today's mainline, I got:

  LD      init/built-in.o
arch/arm/mach-socfpga/socfpga.c: In function 'ksz9021rlrn_phy_fixup':
arch/arm/mach-socfpga/socfpga.c:85:21: error:
'MICREL_KSZ9021_EXTREG_CTRL' undeclared (first use in this function)
arch/arm/mach-socfpga/socfpga.c:85:21: note: each undeclared
identifier is reported only once for each function it appears in
arch/arm/mach-socfpga/socfpga.c:86:4: error:
'MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW' undeclared (first use in this
function)
arch/arm/mach-socfpga/socfpga.c:87:21: error:
'MICREL_KSZ9021_EXTREG_DATA_WRITE' undeclared (first use in this
function)
arch/arm/mach-socfpga/socfpga.c:91:4: error:
'MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW' undeclared (first use in this
function)
arch/arm/mach-socfpga/socfpga.c: In function 'socfpga_cyclone5_init':
arch/arm/mach-socfpga/socfpga.c:193:30: error: 'PHY_ID_KSZ9021RLRN'
undeclared (first use in this function)

I tried adding
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git to my
branch, but that did not help.
 
It compiles ok when I apply

Date: Mon, 15 Jul 2013 18:08:50 -0500
From: dinguyen@altera.com
To: dinh.linux@gmail.com, netdev@vger.kernel.org
Cc: Pavel Machek <pavel@denx.de>, Nicolas Ferre
<nicolas.ferre@atmel.com>,
        "David S. Miller" <davem@davemloft.net>,
        linux-arm-kernel@lists.infradead.org,
        Shawn Guo <shawn.guo@linaro.org>,
        Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>,
        Andrew Victor <linux@maxim.org.za>,
        Dinh Nguyen <dinguyen@altera.com>
Subject: [PATCH] phy: micrel: Add definitions for common Micrel PHY
registers
X-Mailer: git-send-email 1.7.9.5

From: Dinh Nguyen <dinguyen@altera.com>

Add defines for common Micrel PHY setups so that other platforms
can use them. Update imx61 and sama5 hardware to use the micrel_phy.h
PHY defines.

Also add support for the KSZ9021RLRN PHY.

. Perhaps it should be added to the series (or at least pushed
again?).

Thanks,
									Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Re: [RESEND PATCH 2/4] arm: socfpga: Add platform initialization for ethernet

[Olof Johansson]

Hi,

On Mon, Aug 05, 2013 at 04:58:43PM -0500, dinguyen@altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Use the PHYLIB to set the correct clock and skew values to the Micrel PHY. Add
> platform specific intilization to put the STMMAC ethernet controller into the
> correct PHY mode.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> CC: Arnd Bergmann <arnd@arndb.de>
> CC: Olof Johansson <olof@lixom.net>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Ian Campbell <ian.campbell@citrix.com>
> Cc: devicetree@vger.kernel.org
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> ---
>  arch/arm/mach-socfpga/core.h    |    8 ++++
>  arch/arm/mach-socfpga/socfpga.c |   85 ++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 92 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
> index 572b8f7..505b8fe5 100644
> --- a/arch/arm/mach-socfpga/core.h
> +++ b/arch/arm/mach-socfpga/core.h
> @@ -28,6 +28,14 @@
>  #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
>  #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
>  
> +#define SYSMGR_EMACGRP_CTRL_OFFSET 0x60
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
> +
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
> +
>  extern void socfpga_secondary_startup(void);
>  extern void __iomem *socfpga_scu_base_addr;
>  
> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
> index bfce964..abbde76 100644
> --- a/arch/arm/mach-socfpga/socfpga.c
> +++ b/arch/arm/mach-socfpga/socfpga.c
> @@ -16,10 +16,14 @@
>   */
>  #include <linux/clk-provider.h>
>  #include <linux/irqchip.h>
> +#include <linux/micrel_phy.h>
>  #include <linux/of_address.h>
>  #include <linux/of_irq.h>
> +#include <linux/of_net.h>
>  #include <linux/of_platform.h>
>  #include <linux/reboot.h>
> +#include <linux/stmmac.h>
> +#include <linux/phy.h>
>  
>  #include <asm/hardware/cache-l2x0.h>
>  #include <asm/mach/arch.h>
> @@ -33,6 +37,22 @@ void __iomem *rst_manager_base_addr;
>  void __iomem *clk_mgr_base_addr;
>  unsigned long cpu1start_addr;
>  
> +static int stmmac_plat_init(struct platform_device *pdev);
> +
> +static struct plat_stmmacenet_data stmmacenet0_data = {
> +	.init = &stmmac_plat_init,
> +};
> +
> +static struct plat_stmmacenet_data stmmacenet1_data = {
> +	.init = &stmmac_plat_init,
> +};

I would prefer to see refactoring of the driver such that it gets
the phy configuration data out of the devicetree instead of needing
per-board callbacks.

> +
> +static const struct of_dev_auxdata socfpga_auxdata_lookup[] __initconst = {
> +	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff700000, NULL, &stmmacenet0_data),
> +	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff702000, NULL, &stmmacenet1_data),
> +	{/* sentinel */}
> +};
> +
>  static struct map_desc scu_io_desc __initdata = {
>  	.virtual	= SOCFPGA_SCU_VIRT_BASE,
>  	.pfn		= 0, /* run-time */
> @@ -58,6 +78,65 @@ static void __init socfpga_scu_map_io(void)
>  	iotable_init(&scu_io_desc, 1);
>  }
>  
> +static int ksz9021rlrn_phy_fixup(struct phy_device *phydev)
> +{
> +	if (IS_BUILTIN(CONFIG_PHYLIB)) {

So what happens if PHYLIB is a module?

> +		/* min rx data delay */
> +		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
> +			MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000);
> +		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
> +
> +		/* max rx/tx clock delay, min rx/tx control delay */
> +		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
> +			MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000);
> +		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xa0d0);
> +		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 0x104);
> +	}
> +
> +	return 0;
> +}
> +
> +static int stmmac_plat_init(struct platform_device *pdev)
> +{
> +	u32 ctrl, val, shift;
> +	int phymode;
> +
> +	if (of_machine_is_compatible("altr,socfpga-vt"))
> +		return 0;
> +
> +	phymode = of_get_phy_mode(pdev->dev.of_node);
> +
> +	switch (phymode) {
> +	case PHY_INTERFACE_MODE_RGMII:
> +		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
> +		break;
> +	case PHY_INTERFACE_MODE_MII:
> +	case PHY_INTERFACE_MODE_GMII:
> +		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
> +		break;
> +	default:
> +		pr_err("%s bad phy mode %d", __func__, phymode);
> +		return -EINVAL;
> +	}
> +
> +	if (&stmmacenet1_data == pdev->dev.platform_data)
> +		shift = SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH;
> +	else if (&stmmacenet0_data == pdev->dev.platform_data)
> +		shift = 0;

This is awkward too, comparing back to the platform data to figure out which of
the two devices you're on.

> +	else {
> +		pr_err("%s unexpected platform data pointer\n", __func__);
> +		return -EINVAL;
> +	}
> +
> +	ctrl = readl(sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET);
> +	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << shift);
> +	ctrl |= (val << shift);
> +
> +	writel(ctrl, (sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET));
> +
> +	return 0;
> +}
> +
>  static void __init socfpga_map_io(void)
>  {
>  	socfpga_scu_map_io();
> @@ -106,9 +185,13 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
>  static void __init socfpga_cyclone5_init(void)
>  {
>  	l2x0_of_init(0, ~0UL);
> -	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +	of_platform_populate(NULL, of_default_bus_match_table,
> +		socfpga_auxdata_lookup, NULL);
>  	of_clk_init(NULL);
>  	socfpga_init_clocks();
> +	if (IS_BUILTIN(CONFIG_PHYLIB))
> +		phy_register_fixup_for_uid(PHY_ID_KSZ9021RLRN,
> +			MICREL_PHY_ID_MASK, ksz9021rlrn_phy_fixup);


-Olof

Re: [RESEND PATCH 2/4] arm: socfpga: Add platform initialization for ethernet

[Dinh Nguyen]

On Sun, 2013-08-11 at 16:55 -0700, Olof Johansson wrote:
> Hi,
> 
> On Mon, Aug 05, 2013 at 04:58:43PM -0500, dinguyen@altera.com wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Use the PHYLIB to set the correct clock and skew values to the Micrel PHY. Add
> > platform specific intilization to put the STMMAC ethernet controller into the
> > correct PHY mode.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> > CC: Arnd Bergmann <arnd@arndb.de>
> > CC: Olof Johansson <olof@lixom.net>
> > Cc: Rob Herring <rob.herring@calxeda.com>
> > Cc: Pawel Moll <pawel.moll@arm.com>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Stephen Warren <swarren@wwwdotorg.org>
> > Cc: Ian Campbell <ian.campbell@citrix.com>
> > Cc: devicetree@vger.kernel.org
> > Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > Cc: Pavel Machek <pavel@denx.de>
> > Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> > ---
> >  arch/arm/mach-socfpga/core.h    |    8 ++++
> >  arch/arm/mach-socfpga/socfpga.c |   85 ++++++++++++++++++++++++++++++++++++++-
> >  2 files changed, 92 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
> > index 572b8f7..505b8fe5 100644
> > --- a/arch/arm/mach-socfpga/core.h
> > +++ b/arch/arm/mach-socfpga/core.h
> > @@ -28,6 +28,14 @@
> >  #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
> >  #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
> >  
> > +#define SYSMGR_EMACGRP_CTRL_OFFSET 0x60
> > +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
> > +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
> > +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
> > +#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
> > +
> > +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
> > +
> >  extern void socfpga_secondary_startup(void);
> >  extern void __iomem *socfpga_scu_base_addr;
> >  
> > diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
> > index bfce964..abbde76 100644
> > --- a/arch/arm/mach-socfpga/socfpga.c
> > +++ b/arch/arm/mach-socfpga/socfpga.c
> > @@ -16,10 +16,14 @@
> >   */
> >  #include <linux/clk-provider.h>
> >  #include <linux/irqchip.h>
> > +#include <linux/micrel_phy.h>
> >  #include <linux/of_address.h>
> >  #include <linux/of_irq.h>
> > +#include <linux/of_net.h>
> >  #include <linux/of_platform.h>
> >  #include <linux/reboot.h>
> > +#include <linux/stmmac.h>
> > +#include <linux/phy.h>
> >  
> >  #include <asm/hardware/cache-l2x0.h>
> >  #include <asm/mach/arch.h>
> > @@ -33,6 +37,22 @@ void __iomem *rst_manager_base_addr;
> >  void __iomem *clk_mgr_base_addr;
> >  unsigned long cpu1start_addr;
> >  
> > +static int stmmac_plat_init(struct platform_device *pdev);
> > +
> > +static struct plat_stmmacenet_data stmmacenet0_data = {
> > +	.init = &stmmac_plat_init,
> > +};
> > +
> > +static struct plat_stmmacenet_data stmmacenet1_data = {
> > +	.init = &stmmac_plat_init,
> > +};
> 
> I would prefer to see refactoring of the driver such that it gets
> the phy configuration data out of the devicetree instead of needing
> per-board callbacks.
> 
> > +
> > +static const struct of_dev_auxdata socfpga_auxdata_lookup[] __initconst = {
> > +	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff700000, NULL, &stmmacenet0_data),
> > +	OF_DEV_AUXDATA("snps,dwmac-3.70a", 0xff702000, NULL, &stmmacenet1_data),
> > +	{/* sentinel */}
> > +};
> > +
> >  static struct map_desc scu_io_desc __initdata = {
> >  	.virtual	= SOCFPGA_SCU_VIRT_BASE,
> >  	.pfn		= 0, /* run-time */
> > @@ -58,6 +78,65 @@ static void __init socfpga_scu_map_io(void)
> >  	iotable_init(&scu_io_desc, 1);
> >  }
> >  
> > +static int ksz9021rlrn_phy_fixup(struct phy_device *phydev)
> > +{
> > +	if (IS_BUILTIN(CONFIG_PHYLIB)) {
> 
> So what happens if PHYLIB is a module?
> 
> > +		/* min rx data delay */
> > +		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
> > +			MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000);
> > +		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
> > +
> > +		/* max rx/tx clock delay, min rx/tx control delay */
> > +		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
> > +			MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000);
> > +		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xa0d0);
> > +		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, 0x104);
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int stmmac_plat_init(struct platform_device *pdev)
> > +{
> > +	u32 ctrl, val, shift;
> > +	int phymode;
> > +
> > +	if (of_machine_is_compatible("altr,socfpga-vt"))
> > +		return 0;
> > +
> > +	phymode = of_get_phy_mode(pdev->dev.of_node);
> > +
> > +	switch (phymode) {
> > +	case PHY_INTERFACE_MODE_RGMII:
> > +		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
> > +		break;
> > +	case PHY_INTERFACE_MODE_MII:
> > +	case PHY_INTERFACE_MODE_GMII:
> > +		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
> > +		break;
> > +	default:
> > +		pr_err("%s bad phy mode %d", __func__, phymode);
> > +		return -EINVAL;
> > +	}
> > +
> > +	if (&stmmacenet1_data == pdev->dev.platform_data)
> > +		shift = SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH;
> > +	else if (&stmmacenet0_data == pdev->dev.platform_data)
> > +		shift = 0;
> 
> This is awkward too, comparing back to the platform data to figure out which of
> the two devices you're on.
> 
> > +	else {
> > +		pr_err("%s unexpected platform data pointer\n", __func__);
> > +		return -EINVAL;
> > +	}
> > +
> > +	ctrl = readl(sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET);
> > +	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << shift);
> > +	ctrl |= (val << shift);
> > +
> > +	writel(ctrl, (sys_manager_base_addr + SYSMGR_EMACGRP_CTRL_OFFSET));
> > +
> > +	return 0;
> > +}
> > +
> >  static void __init socfpga_map_io(void)
> >  {
> >  	socfpga_scu_map_io();
> > @@ -106,9 +185,13 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
> >  static void __init socfpga_cyclone5_init(void)
> >  {
> >  	l2x0_of_init(0, ~0UL);
> > -	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> > +	of_platform_populate(NULL, of_default_bus_match_table,
> > +		socfpga_auxdata_lookup, NULL);
> >  	of_clk_init(NULL);
> >  	socfpga_init_clocks();
> > +	if (IS_BUILTIN(CONFIG_PHYLIB))
> > +		phy_register_fixup_for_uid(PHY_ID_KSZ9021RLRN,
> > +			MICREL_PHY_ID_MASK, ksz9021rlrn_phy_fixup);
> 

Thanks for the review Olof. Will rework.

Dinh
> 
> -Olof
> 

[RESEND PATCH 3/4] ARM: socfpga: dts: Fix entries for the ethernet entries.

[dinguyen]

From: Dinh Nguyen <dinguyen@altera.com>

Use the gate-clock emac_0_clk and emac_1_clk. Fix phy-addr binding to the
correct snps,phy-addr binding.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: devicetree@vger.kernel.org
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
---
 arch/arm/boot/dts/socfpga.dtsi         |    4 ++--
 arch/arm/boot/dts/socfpga_cyclone5.dts |    2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index dbf7f22..93ee655 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -444,7 +444,7 @@
 			interrupts = <0 115 4>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-			clocks = <&emac0_clk>;
+			clocks = <&emac_0_clk>;
 			clock-names = "stmmaceth";
 			status = "disabled";
 		};
@@ -455,7 +455,7 @@
 			interrupts = <0 120 4>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-			clocks = <&emac1_clk>;
+			clocks = <&emac_1_clk>;
 			clock-names = "stmmaceth";
 			status = "disabled";
 		};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 1853cb1..102c4d8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -50,7 +50,7 @@
 
 		ethernet@ff702000 {
 			phy-mode = "rgmii";
-			phy-addr = <0xffffffff>; /* probe for phy addr */
+			snps,phy-addr = <0xffffffff>; /* probe for phy addr */
 			status = "okay";
 		};
 
-- 
1.7.9.5

Re: [RESEND PATCH 3/4] ARM: socfpga: dts: Fix entries for the ethernet entries.

[Pavel Machek]

Hi!

> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Use the gate-clock emac_0_clk and emac_1_clk. Fix phy-addr binding to the
> correct snps,phy-addr binding.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> CC: Arnd Bergmann <arnd@arndb.de>
> CC: Olof Johansson <olof@lixom.net>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Ian Campbell <ian.campbell@citrix.com>
> Cc: devicetree@vger.kernel.org
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>

With this patch, ethernet starts to work for me.

Reviewed-by: Pavel Machek <pavel@denx.de>
Tested-by: Pavel Machek <pavel@denx.de>

Thanks!
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

[RESEND PATCH 4/4] arm: socfpga: Add support for SD/MMC and ethernet to defconfig

[dinguyen]

From: Dinh Nguyen <dinguyen@altera.com>

Update the socfpga_defconfig to include dw_mmc driver and Micrel PHY.
Also enable EXT3 and NFS FS support.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: devicetree@vger.kernel.org
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
---
 arch/arm/configs/socfpga_defconfig |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 4e1ce21..dcca3a1 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -52,6 +52,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_STMMAC_ETH=y
+CONFIG_MICREL_PHY=y
 # CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_SERPORT is not set
@@ -66,6 +67,9 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT3_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
 CONFIG_VFAT_FS=y
@@ -82,3 +86,7 @@ CONFIG_DEBUG_INFO=y
 CONFIG_ENABLE_DEFAULT_TRACERS=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
+CONFIG_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_SOCFPGA=y
-- 
1.7.9.5

Re: [RESEND PATCH 4/4] arm: socfpga: Add support for SD/MMC and ethernet to defconfig

[Pavel Machek]

Hi!

> Update the socfpga_defconfig to include dw_mmc driver and Micrel PHY.
> Also enable EXT3 and NFS FS support.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> CC: Arnd Bergmann <arnd@arndb.de>
> CC: Olof Johansson <olof@lixom.net>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Ian Campbell <ian.campbell@citrix.com>
> Cc: devicetree@vger.kernel.org
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>

Reviewed-by: Pavel Machek <pavel@denx.de>

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Re: [RESEND PATCH 4/4] arm: socfpga: Add support for SD/MMC and ethernet to defconfig

[Pavel Machek]

Hi!

> From: Dinh Nguyen <dinguyen@altera.com>
> 
> Update the socfpga_defconfig to include dw_mmc driver and Micrel PHY.
> Also enable EXT3 and NFS FS support.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>


> @@ -82,3 +86,7 @@ CONFIG_DEBUG_INFO=y
>  CONFIG_ENABLE_DEFAULT_TRACERS=y
>  CONFIG_DEBUG_USER=y
>  CONFIG_XZ_DEC=y
> +CONFIG_MMC=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_PLTFM=y
> +CONFIG_MMC_DW_SOCFPGA=y

Actually, I was confused here. This series does not seem to enable MMC,
so it probably should not be enabled in defconfig.

[Patch below can be used to get MMC working, but is not
production-quality.]

Thanks,
								Pavel

commit 035495806fddc3f0dfdd23630185d6c1e0ec0923
Author: Pavel Machek <pavel@denx.de>
Date:   Thu Aug 8 10:57:56 2013 +0200

    With these patches, mmc now works.

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index d950c67..0e5881b 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -449,6 +449,23 @@
 			status = "disabled";
 		};
 
+               mmc: dwmmc0@ff704000 {
+                       compatible = "snps,dw-mshc";
+                       reg = <0xff704000 0x1000>;
+                       interrupts = <0 139 4>;
+                       bus-hz = <12500000>; /*12.5 MHz*/
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       num-slots = <1>;
+                       supports-highspeed;
+                       broken-cd;
+                       fifo-depth = <0x400>;
+                       slot@0 {
+                               reg = <0>;
+                               bus-width = <4>;
+                       };
+               };
+
 		gmac1: ethernet@ff702000 {
 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 			reg = <0xff702000 0x2000>;
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index ee5f167..8e40030 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -38,10 +38,16 @@
 
 #include "dw_mmc.h"
 
+#define SDMMC_INT_DTO                  BIT(9)
+
 /* Common flag combinations */
-#define DW_MCI_DATA_ERROR_FLAGS	(SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
-				 SDMMC_INT_HTO | SDMMC_INT_SBE  | \
-				 SDMMC_INT_EBE)
+/* According to Synopsys, the data starvation interrupt (HTO) should not treat
+ * as error. Software should continue the data transfer. We have verified this
+ * in Virtual Target. The same is applied to FIFO under/overrun (FRUN) as well.
+ */
+#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
+				 SDMMC_INT_HTO | SDMMC_INT_FRUN | SDMMC_INT_SBE | SDMMC_INT_EBE)
+
 #define DW_MCI_CMD_ERROR_FLAGS	(SDMMC_INT_RTO | SDMMC_INT_RCRC | \
 				 SDMMC_INT_RESP_ERR)
 #define DW_MCI_ERROR_FLAGS	(DW_MCI_DATA_ERROR_FLAGS | \
@@ -276,6 +282,9 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 	if (drv_data && drv_data->prepare_command)
 		drv_data->prepare_command(slot->host, &cmdr);
 
+	if (slot->host->use_hold_reg)
+		cmdr |= SDMMC_CMD_USE_HOLD_REG;
+
 	return cmdr;
 }
 
@@ -2125,6 +2134,11 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
 		return ERR_PTR(-ENOMEM);
 	}
 
+	if (of_property_read_u32(dev->of_node, "bus-hz", &pdata->bus_hz)) {
+		dev_err(dev, "couldn't determine bus-hz\n");
+		pdata->bus_hz = 50000000;
+	}
+
 	/* find out number of slots supported */
 	if (of_property_read_u32(dev->of_node, "num-slots",
 				&pdata->num_slots)) {
@@ -2287,6 +2301,9 @@ int dw_mci_probe(struct dw_mci *host)
 		host->data_shift = 2;
 	}
 
+	/* Get the USE_HOLD_REG */
+	host->use_hold_reg = mci_readl(host, CMD) & SDMMC_CMD_USE_HOLD_REG;
+
 	/* Reset all blocks */
 	if (!mci_wait_reset(host->dev, host))
 		return -ENODEV;
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index 198f0fa..b8bcfed 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -187,6 +187,9 @@ struct dw_mci {
 	struct regulator	*vmmc;	/* Power regulator */
 	unsigned long		irq_flags; /* IRQ flags */
 	int			irq;
+
+	/* Set to one for SDR12 and SDR25 */
+	unsigned int use_hold_reg;
 };
 
 /* DMA ops for Internal/External DMAC interface */


-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Re: [RESEND PATCH 4/4] arm: socfpga: Add support for SD/MMC and ethernet to defconfig

[Dinh Nguyen]

On Thu, 2013-08-08 at 11:01 +0200, ZY - pavel wrote:
> Hi!
> 
> > From: Dinh Nguyen <dinguyen@altera.com>
> > 
> > Update the socfpga_defconfig to include dw_mmc driver and Micrel PHY.
> > Also enable EXT3 and NFS FS support.
> > 
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Tested-by: Jack Mitchell <jack.mitchell@dbbroadcast.co.uk>
> 
> 
> > @@ -82,3 +86,7 @@ CONFIG_DEBUG_INFO=y
> >  CONFIG_ENABLE_DEFAULT_TRACERS=y
> >  CONFIG_DEBUG_USER=y
> >  CONFIG_XZ_DEC=y
> > +CONFIG_MMC=y
> > +CONFIG_MMC_DW=y
> > +CONFIG_MMC_DW_PLTFM=y
> > +CONFIG_MMC_DW_SOCFPGA=y
> 
> Actually, I was confused here. This series does not seem to enable MMC,
> so it probably should not be enabled in defconfig.

You need this patch, which you reviewed also.

http://archive.arm.linux.org.uk/lurker/message/20130805.204312.7f9a34d2.en.html

I'm staging these patches at:

git.rocketboards.org:linux-socfpga-next.git for-next

Dinh

> 
> [Patch below can be used to get MMC working, but is not
> production-quality.]
> 
> Thanks,
> 								Pavel
> 
> commit 035495806fddc3f0dfdd23630185d6c1e0ec0923
> Author: Pavel Machek <pavel@denx.de>
> Date:   Thu Aug 8 10:57:56 2013 +0200
> 
>     With these patches, mmc now works.
> 
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index d950c67..0e5881b 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -449,6 +449,23 @@
>  			status = "disabled";
>  		};
>  
> +               mmc: dwmmc0@ff704000 {
> +                       compatible = "snps,dw-mshc";
> +                       reg = <0xff704000 0x1000>;
> +                       interrupts = <0 139 4>;
> +                       bus-hz = <12500000>; /*12.5 MHz*/
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       num-slots = <1>;
> +                       supports-highspeed;
> +                       broken-cd;
> +                       fifo-depth = <0x400>;
> +                       slot@0 {
> +                               reg = <0>;
> +                               bus-width = <4>;
> +                       };
> +               };
> +
>  		gmac1: ethernet@ff702000 {
>  			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
>  			reg = <0xff702000 0x2000>;
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index ee5f167..8e40030 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -38,10 +38,16 @@
>  
>  #include "dw_mmc.h"
>  
> +#define SDMMC_INT_DTO                  BIT(9)
> +
>  /* Common flag combinations */
> -#define DW_MCI_DATA_ERROR_FLAGS	(SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
> -				 SDMMC_INT_HTO | SDMMC_INT_SBE  | \
> -				 SDMMC_INT_EBE)
> +/* According to Synopsys, the data starvation interrupt (HTO) should not treat
> + * as error. Software should continue the data transfer. We have verified this
> + * in Virtual Target. The same is applied to FIFO under/overrun (FRUN) as well.
> + */
> +#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
> +				 SDMMC_INT_HTO | SDMMC_INT_FRUN | SDMMC_INT_SBE | SDMMC_INT_EBE)
> +
>  #define DW_MCI_CMD_ERROR_FLAGS	(SDMMC_INT_RTO | SDMMC_INT_RCRC | \
>  				 SDMMC_INT_RESP_ERR)
>  #define DW_MCI_ERROR_FLAGS	(DW_MCI_DATA_ERROR_FLAGS | \
> @@ -276,6 +282,9 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
>  	if (drv_data && drv_data->prepare_command)
>  		drv_data->prepare_command(slot->host, &cmdr);
>  
> +	if (slot->host->use_hold_reg)
> +		cmdr |= SDMMC_CMD_USE_HOLD_REG;
> +
>  	return cmdr;
>  }
>  
> @@ -2125,6 +2134,11 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
>  		return ERR_PTR(-ENOMEM);
>  	}
>  
> +	if (of_property_read_u32(dev->of_node, "bus-hz", &pdata->bus_hz)) {
> +		dev_err(dev, "couldn't determine bus-hz\n");
> +		pdata->bus_hz = 50000000;
> +	}
> +
>  	/* find out number of slots supported */
>  	if (of_property_read_u32(dev->of_node, "num-slots",
>  				&pdata->num_slots)) {
> @@ -2287,6 +2301,9 @@ int dw_mci_probe(struct dw_mci *host)
>  		host->data_shift = 2;
>  	}
>  
> +	/* Get the USE_HOLD_REG */
> +	host->use_hold_reg = mci_readl(host, CMD) & SDMMC_CMD_USE_HOLD_REG;
> +
>  	/* Reset all blocks */
>  	if (!mci_wait_reset(host->dev, host))
>  		return -ENODEV;
> diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
> index 198f0fa..b8bcfed 100644
> --- a/include/linux/mmc/dw_mmc.h
> +++ b/include/linux/mmc/dw_mmc.h
> @@ -187,6 +187,9 @@ struct dw_mci {
>  	struct regulator	*vmmc;	/* Power regulator */
>  	unsigned long		irq_flags; /* IRQ flags */
>  	int			irq;
> +
> +	/* Set to one for SDR12 and SDR25 */
> +	unsigned int use_hold_reg;
>  };
>  
>  /* DMA ops for Internal/External DMAC interface */
> 
>