* [PATCH] arm64: dts: rockchip: Fix PWM pinctrl names
@ 2025-03-10 14:09 Yao Zi
2025-03-12 7:46 ` Heiko Stuebner
[not found] ` <20250511100022.31465-1-amadeus@jmu.edu.cn>
0 siblings, 2 replies; 8+ messages in thread
From: Yao Zi @ 2025-03-10 14:09 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Yao Zi, Dragan Simic, Johan Jonker, Diederik de Haas, Andy Yan,
Damon Ding, Jing Luo, Sebastian Reichel, Robin Murphy,
Tomeu Vizoso
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
These Rockchip boards assign "active" as the pinctrl name for PWM
controllers, which has never been supported in mainline Rockchip PWM
driver. It seems the name used by downstream kernel is accidentally
brought into maineline. Let's fix them.
Fixes: 4403e1237be3 ("arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc")
Fixes: 964ed0807b5f ("arm64: dts: rockchip: add rk3318 A95X Z2 board")
Fixes: e7a095908227 ("arm64: dts: rockchip: Add devicetree for NanoPC-T4")
Fixes: 3f5d336d64d6 ("arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B")
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
It's uncommon to have a commit carrying so many fix tags, but otherwise
four seperate small commits will be created with the same topic. I'm
willing to change this if it's inappropriate.
I don't have these boards for a real test, but the change should be the
right way.
Thanks for your time and review.
arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts | 2 +-
arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 4 ++--
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +-
arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
index 629121de5a13..5e7181948992 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
@@ -147,7 +147,7 @@ rtc: rtc@51 {
&pwm5 {
status = "okay";
- pinctrl-names = "active";
+ pinctrl-names = "default";
pinctrl-0 = <&pwm5_pin_pull_down>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
index a94114fb7cc1..96c27fc5005d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
@@ -274,13 +274,13 @@ otg_vbus_drv: otg-vbus-drv {
&pwm0 {
pinctrl-0 = <&pwm0_pin_pull_up>;
- pinctrl-names = "active";
+ pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_pin_pull_up>;
- pinctrl-names = "active";
+ pinctrl-names = "default";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index b169be06d4d1..c8eb5481f43d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -603,7 +603,7 @@ &pwm1 {
};
&pwm2 {
- pinctrl-names = "active";
+ pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin_pull_down>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
index 8f00e0444c00..8b717c4017a4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
@@ -433,7 +433,7 @@ &pwm2 {
};
&pwm13 {
- pinctrl-names = "active";
+ pinctrl-names = "default";
pinctrl-0 = <&pwm13m2_pins>;
status = "okay";
};
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: rockchip: Fix PWM pinctrl names
2025-03-10 14:09 [PATCH] arm64: dts: rockchip: Fix PWM pinctrl names Yao Zi
@ 2025-03-12 7:46 ` Heiko Stuebner
[not found] ` <20250511100022.31465-1-amadeus@jmu.edu.cn>
1 sibling, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-03-12 7:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Dragan Simic,
Johan Jonker, Diederik de Haas, Andy Yan, Damon Ding, Jing Luo,
Sebastian Reichel, Robin Murphy, Tomeu Vizoso, Yao Zi
Cc: Heiko Stuebner, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
On Mon, 10 Mar 2025 14:09:17 +0000, Yao Zi wrote:
> These Rockchip boards assign "active" as the pinctrl name for PWM
> controllers, which has never been supported in mainline Rockchip PWM
> driver. It seems the name used by downstream kernel is accidentally
> brought into maineline. Let's fix them.
>
>
Applied, thanks!
[1/1] arm64: dts: rockchip: Fix PWM pinctrl names
commit: 96d8d325324639f03fcca12e4ea92265ebb24837
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC
2025-05-09 10:23 [PATCH v7 0/5] rockchip: Add rk3562 SoC and evb support Kever Yang
@ 2025-05-09 10:23 ` Kever Yang
2025-05-16 7:01 ` Chukun Pan
0 siblings, 1 reply; 8+ messages in thread
From: Kever Yang @ 2025-05-09 10:23 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, Finley Xiao, Kever Yang, devicetree, Conor Dooley,
Rob Herring, linux-kernel, Krzysztof Kozlowski, linux-arm-kernel
From: Finley Xiao <finley.xiao@rock-chips.com>
RK3562 is a SoC from Rockchip, which embedded with quad
ARM Cortex-A53.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v7: None
Changes in v6:
- Remove USB and watchdog nodes
Changes in v5:
- Update scmi-shmem from soc to reserved memory
Changes in v4:
- remove gmac and otp nodes
Changes in v3:
- remove i2c/serial/spi alias
- add soc node
Changes in v2:
- remove grf in cru
- Update some properties order
.../boot/dts/rockchip/rk3562-pinctrl.dtsi | 2352 +++++++++++++++++
arch/arm64/boot/dts/rockchip/rk3562.dtsi | 1187 +++++++++
2 files changed, 3539 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/rockchip/rk3562.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi
new file mode 100644
index 000000000000..b311448d77a3
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi
@@ -0,0 +1,2352 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ cam {
+ /omit-if-no-ref/
+ camm0_clk0_out: camm0-clk0-out {
+ rockchip,pins =
+ /* camm0_clk0_out */
+ <3 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ camm0_clk1_out: camm0-clk1-out {
+ rockchip,pins =
+ /* camm0_clk1_out */
+ <3 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ camm1_clk0_out: camm1-clk0-out {
+ rockchip,pins =
+ /* camm1_clk0_out */
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ camm1_clk1_out: camm1-clk1-out {
+ rockchip,pins =
+ /* camm1_clk1_out */
+ <4 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clk2_out: cam-clk2-out {
+ rockchip,pins =
+ /* cam_clk2_out */
+ <3 RK_PB4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clk3_out: cam-clk3-out {
+ rockchip,pins =
+ /* cam_clk3_out */
+ <3 RK_PB5 2 &pcfg_pull_none>;
+ };
+ };
+
+ can0 {
+ /omit-if-no-ref/
+ can0m0_pins: can0m0-pins {
+ rockchip,pins =
+ /* can0_rx_m0 */
+ <3 RK_PA1 4 &pcfg_pull_none>,
+ /* can0_tx_m0 */
+ <3 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m1_pins: can0m1-pins {
+ rockchip,pins =
+ /* can0_rx_m1 */
+ <3 RK_PB7 6 &pcfg_pull_none>,
+ /* can0_tx_m1 */
+ <3 RK_PB6 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m2_pins: can0m2-pins {
+ rockchip,pins =
+ /* can0_rx_m2 */
+ <0 RK_PC7 2 &pcfg_pull_none>,
+ /* can0_tx_m2 */
+ <0 RK_PC6 2 &pcfg_pull_none>;
+ };
+ };
+
+ can1 {
+ /omit-if-no-ref/
+ can1m0_pins: can1m0-pins {
+ rockchip,pins =
+ /* can1_rx_m0 */
+ <1 RK_PB7 4 &pcfg_pull_none>,
+ /* can1_tx_m0 */
+ <1 RK_PC0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m1_pins: can1m1-pins {
+ rockchip,pins =
+ /* can1_rx_m1 */
+ <0 RK_PC1 4 &pcfg_pull_none>,
+ /* can1_tx_m1 */
+ <0 RK_PC0 4 &pcfg_pull_none>;
+ };
+ };
+
+ clk {
+ /omit-if-no-ref/
+ clk_32k_in: clk-32k-in {
+ rockchip,pins =
+ /* clk_32k_in */
+ <0 RK_PB0 1 &pcfg_pull_none>;
+ };
+ };
+
+ clk0 {
+ /omit-if-no-ref/
+ clk0_32k_out: clk0-32k-out {
+ rockchip,pins =
+ /* clk0_32k_out */
+ <0 RK_PB0 2 &pcfg_pull_none>;
+ };
+ };
+
+ clk1 {
+ /omit-if-no-ref/
+ clk1_32k_out: clk1-32k-out {
+ rockchip,pins =
+ /* clk1_32k_out */
+ <2 RK_PA1 3 &pcfg_pull_none>;
+ };
+ };
+
+ cpu {
+ /omit-if-no-ref/
+ cpu_pins: cpu-pins {
+ rockchip,pins =
+ /* cpu_avs */
+ <0 RK_PB7 3 &pcfg_pull_none>;
+ };
+ };
+
+ dsm {
+ /omit-if-no-ref/
+ dsm_pins: dsm-pins {
+ rockchip,pins =
+ /* dsm_aud_ln */
+ <1 RK_PB4 5 &pcfg_pull_none>,
+ /* dsm_aud_lp */
+ <1 RK_PB3 5 &pcfg_pull_none>,
+ /* dsm_aud_rn */
+ <1 RK_PB6 6 &pcfg_pull_none>,
+ /* dsm_aud_rp */
+ <1 RK_PB5 6 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clk */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_strb: emmc-strb {
+ rockchip,pins =
+ /* emmc_strb */
+ <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth {
+ /omit-if-no-ref/
+ ethm0_pins: ethm0-pins {
+ rockchip,pins =
+ /* eth_clk_25m_out_m0 */
+ <4 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ethm1_pins: ethm1-pins {
+ rockchip,pins =
+ /* eth_clk_25m_out_m1 */
+ <2 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspi_pins: fspi-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PB1 2 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PA0 2 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PA1 2 &pcfg_pull_none>,
+ /* fspi_d2 */
+ <1 RK_PA2 2 &pcfg_pull_none>,
+ /* fspi_d3 */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi_csn0: fspi-csn0 {
+ rockchip,pins =
+ /* fspi_csn0 */
+ <1 RK_PB0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ fspi_csn1: fspi-csn1 {
+ rockchip,pins =
+ /* fspi_csn1 */
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+ };
+
+ gpu {
+ /omit-if-no-ref/
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <0 RK_PC0 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB1 1 &pcfg_pull_none_smt>,
+ /* i2c0_sda */
+ <0 RK_PB2 1 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1m0_xfer: i2c1m0-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <0 RK_PB3 1 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m0 */
+ <0 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m1_xfer: i2c1m1-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m1 */
+ <4 RK_PB4 5 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m1 */
+ <4 RK_PB5 5 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m0 */
+ <0 RK_PB5 1 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m0 */
+ <0 RK_PB6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m1 */
+ <3 RK_PD2 5 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m1 */
+ <3 RK_PD3 5 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <3 RK_PA0 1 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m0 */
+ <3 RK_PA1 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <4 RK_PA5 5 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m1 */
+ <4 RK_PA6 5 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <3 RK_PB6 5 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m0 */
+ <3 RK_PB7 5 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <0 RK_PA5 2 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m1 */
+ <0 RK_PA4 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <3 RK_PC2 1 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m0 */
+ <3 RK_PC3 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <1 RK_PC7 4 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m1 */
+ <1 RK_PD0 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s0 {
+ /omit-if-no-ref/
+ i2s0m0_lrck: i2s0m0-lrck {
+ rockchip,pins =
+ /* i2s0_lrck_m0 */
+ <3 RK_PA4 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_mclk: i2s0m0-mclk {
+ rockchip,pins =
+ /* i2s0_mclk_m0 */
+ <3 RK_PA2 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sclk: i2s0m0-sclk {
+ rockchip,pins =
+ /* i2s0_sclk_m0 */
+ <3 RK_PA3 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdi0: i2s0m0-sdi0 {
+ rockchip,pins =
+ /* i2s0_sdi0_m0 */
+ <3 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdi1: i2s0m0-sdi1 {
+ rockchip,pins =
+ /* i2s0_sdi1_m0 */
+ <3 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdi2: i2s0m0-sdi2 {
+ rockchip,pins =
+ /* i2s0_sdi2_m0 */
+ <3 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdi3: i2s0m0-sdi3 {
+ rockchip,pins =
+ /* i2s0_sdi3_m0 */
+ <3 RK_PA6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdo0: i2s0m0-sdo0 {
+ rockchip,pins =
+ /* i2s0_sdo0_m0 */
+ <3 RK_PA5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdo1: i2s0m0-sdo1 {
+ rockchip,pins =
+ /* i2s0_sdo1_m0 */
+ <3 RK_PA6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdo2: i2s0m0-sdo2 {
+ rockchip,pins =
+ /* i2s0_sdo2_m0 */
+ <3 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdo3: i2s0m0-sdo3 {
+ rockchip,pins =
+ /* i2s0_sdo3_m0 */
+ <3 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_lrck: i2s0m1-lrck {
+ rockchip,pins =
+ /* i2s0_lrck_m1 */
+ <1 RK_PC4 3 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_mclk: i2s0m1-mclk {
+ rockchip,pins =
+ /* i2s0_mclk_m1 */
+ <1 RK_PC6 3 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sclk: i2s0m1-sclk {
+ rockchip,pins =
+ /* i2s0_sclk_m1 */
+ <1 RK_PC5 3 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdi0: i2s0m1-sdi0 {
+ rockchip,pins =
+ /* i2s0_sdi0_m1 */
+ <1 RK_PC1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdi1: i2s0m1-sdi1 {
+ rockchip,pins =
+ /* i2s0_sdi1_m1 */
+ <1 RK_PC2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdi2: i2s0m1-sdi2 {
+ rockchip,pins =
+ /* i2s0_sdi2_m1 */
+ <1 RK_PD3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdi3: i2s0m1-sdi3 {
+ rockchip,pins =
+ /* i2s0_sdi3_m1 */
+ <1 RK_PD4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdo0: i2s0m1-sdo0 {
+ rockchip,pins =
+ /* i2s0_sdo0_m1 */
+ <1 RK_PC3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdo1: i2s0m1-sdo1 {
+ rockchip,pins =
+ /* i2s0_sdo1_m1 */
+ <1 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdo2: i2s0m1-sdo2 {
+ rockchip,pins =
+ /* i2s0_sdo2_m1 */
+ <1 RK_PD2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdo3: i2s0m1-sdo3 {
+ rockchip,pins =
+ /* i2s0_sdo3_m1 */
+ <2 RK_PA1 5 &pcfg_pull_none>;
+ };
+ };
+
+ i2s1 {
+ /omit-if-no-ref/
+ i2s1m0_lrck: i2s1m0-lrck {
+ rockchip,pins =
+ /* i2s1_lrck_m0 */
+ <3 RK_PC6 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_mclk: i2s1m0-mclk {
+ rockchip,pins =
+ /* i2s1_mclk_m0 */
+ <3 RK_PC4 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sclk: i2s1m0-sclk {
+ rockchip,pins =
+ /* i2s1_sclk_m0 */
+ <3 RK_PC5 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi0: i2s1m0-sdi0 {
+ rockchip,pins =
+ /* i2s1_sdi0_m0 */
+ <3 RK_PD0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi1: i2s1m0-sdi1 {
+ rockchip,pins =
+ /* i2s1_sdi1_m0 */
+ <3 RK_PD1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi2: i2s1m0-sdi2 {
+ rockchip,pins =
+ /* i2s1_sdi2_m0 */
+ <3 RK_PD2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi3: i2s1m0-sdi3 {
+ rockchip,pins =
+ /* i2s1_sdi3_m0 */
+ <3 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo0: i2s1m0-sdo0 {
+ rockchip,pins =
+ /* i2s1_sdo0_m0 */
+ <3 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo1: i2s1m0-sdo1 {
+ rockchip,pins =
+ /* i2s1_sdo1_m0 */
+ <4 RK_PB4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo2: i2s1m0-sdo2 {
+ rockchip,pins =
+ /* i2s1_sdo2_m0 */
+ <4 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo3: i2s1m0-sdo3 {
+ rockchip,pins =
+ /* i2s1_sdo3_m0 */
+ <4 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_lrck: i2s1m1-lrck {
+ rockchip,pins =
+ /* i2s1_lrck_m1 */
+ <3 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_mclk: i2s1m1-mclk {
+ rockchip,pins =
+ /* i2s1_mclk_m1 */
+ <3 RK_PB2 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sclk: i2s1m1-sclk {
+ rockchip,pins =
+ /* i2s1_sclk_m1 */
+ <3 RK_PB3 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi0: i2s1m1-sdi0 {
+ rockchip,pins =
+ /* i2s1_sdi0_m1 */
+ <3 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi1: i2s1m1-sdi1 {
+ rockchip,pins =
+ /* i2s1_sdi1_m1 */
+ <3 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi2: i2s1m1-sdi2 {
+ rockchip,pins =
+ /* i2s1_sdi2_m1 */
+ <3 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi3: i2s1m1-sdi3 {
+ rockchip,pins =
+ /* i2s1_sdi3_m1 */
+ <3 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo0: i2s1m1-sdo0 {
+ rockchip,pins =
+ /* i2s1_sdo0_m1 */
+ <3 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo1: i2s1m1-sdo1 {
+ rockchip,pins =
+ /* i2s1_sdo1_m1 */
+ <3 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo2: i2s1m1-sdo2 {
+ rockchip,pins =
+ /* i2s1_sdo2_m1 */
+ <3 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo3: i2s1m1-sdo3 {
+ rockchip,pins =
+ /* i2s1_sdo3_m1 */
+ <3 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s2 {
+ /omit-if-no-ref/
+ i2s2m0_lrck: i2s2m0-lrck {
+ rockchip,pins =
+ /* i2s2_lrck_m0 */
+ <1 RK_PD6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_mclk: i2s2m0-mclk {
+ rockchip,pins =
+ /* i2s2_mclk_m0 */
+ <2 RK_PA1 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sclk: i2s2m0-sclk {
+ rockchip,pins =
+ /* i2s2_sclk_m0 */
+ <1 RK_PD5 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdi: i2s2m0-sdi {
+ rockchip,pins =
+ /* i2s2_sdi_m0 */
+ <2 RK_PA0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdo: i2s2m0-sdo {
+ rockchip,pins =
+ /* i2s2_sdo_m0 */
+ <1 RK_PD7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_lrck: i2s2m1-lrck {
+ rockchip,pins =
+ /* i2s2_lrck_m1 */
+ <4 RK_PA1 3 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_mclk: i2s2m1-mclk {
+ rockchip,pins =
+ /* i2s2_mclk_m1 */
+ <3 RK_PD6 3 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sclk: i2s2m1-sclk {
+ rockchip,pins =
+ /* i2s2_sclk_m1 */
+ <4 RK_PB1 4 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdi: i2s2m1-sdi {
+ rockchip,pins =
+ /* i2s2_sdi_m1 */
+ <3 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdo: i2s2m1-sdo {
+ rockchip,pins =
+ /* i2s2_sdo_m1 */
+ <3 RK_PD5 4 &pcfg_pull_none>;
+ };
+ };
+
+ isp {
+ /omit-if-no-ref/
+ isp_pins: isp-pins {
+ rockchip,pins =
+ /* isp_flash_trigin */
+ <3 RK_PC1 2 &pcfg_pull_none>,
+ /* isp_flash_trigout */
+ <3 RK_PC3 2 &pcfg_pull_none>,
+ /* isp_prelight_trigout */
+ <3 RK_PC2 2 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtagm0_pins: jtagm0-pins {
+ rockchip,pins =
+ /* jtag_cpu_mcu_tck_m0 */
+ <0 RK_PD1 2 &pcfg_pull_none>,
+ /* jtag_cpu_mcu_tms_m0 */
+ <0 RK_PD0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm1_pins: jtagm1-pins {
+ rockchip,pins =
+ /* jtag_cpu_mcu_tck_m1 */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* jtag_cpu_mcu_tms_m1 */
+ <1 RK_PB6 2 &pcfg_pull_none>;
+ };
+ };
+
+ npu {
+ /omit-if-no-ref/
+ npu_pins: npu-pins {
+ rockchip,pins =
+ /* npu_avs */
+ <0 RK_PC1 3 &pcfg_pull_none>;
+ };
+ };
+
+ pcie20 {
+ /omit-if-no-ref/
+ pcie20m0_pins: pcie20m0-pins {
+ rockchip,pins =
+ /* pcie20_clkreqn_m0 */
+ <0 RK_PA6 1 &pcfg_pull_none>,
+ /* pcie20_perstn_m0 */
+ <0 RK_PB5 2 &pcfg_pull_none>,
+ /* pcie20_waken_m0 */
+ <0 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20m1_pins: pcie20m1-pins {
+ rockchip,pins =
+ /* pcie20_clkreqn_m1 */
+ <3 RK_PA6 4 &pcfg_pull_none>,
+ /* pcie20_perstn_m1 */
+ <3 RK_PB0 4 &pcfg_pull_none>,
+ /* pcie20_waken_m1 */
+ <3 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20_buttonrstn: pcie20-buttonrstn {
+ rockchip,pins =
+ /* pcie20_buttonrstn */
+ <0 RK_PB0 3 &pcfg_pull_none>;
+ };
+ };
+
+ pdm {
+ /omit-if-no-ref/
+ pdmm0_clk0: pdmm0-clk0 {
+ rockchip,pins =
+ /* pdm_clk0_m0 */
+ <3 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_clk1: pdmm0-clk1 {
+ rockchip,pins =
+ /* pdm_clk1_m0 */
+ <3 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi0: pdmm0-sdi0 {
+ rockchip,pins =
+ /* pdm_sdi0_m0 */
+ <3 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi1: pdmm0-sdi1 {
+ rockchip,pins =
+ /* pdm_sdi1_m0 */
+ <3 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi2: pdmm0-sdi2 {
+ rockchip,pins =
+ /* pdm_sdi2_m0 */
+ <3 RK_PA7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi3: pdmm0-sdi3 {
+ rockchip,pins =
+ /* pdm_sdi3_m0 */
+ <3 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk0: pdmm1-clk0 {
+ rockchip,pins =
+ /* pdm_clk0_m1 */
+ <4 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk1: pdmm1-clk1 {
+ rockchip,pins =
+ /* pdm_clk1_m1 */
+ <4 RK_PB1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi0: pdmm1-sdi0 {
+ rockchip,pins =
+ /* pdm_sdi0_m1 */
+ <4 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi1: pdmm1-sdi1 {
+ rockchip,pins =
+ /* pdm_sdi1_m1 */
+ <4 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi2: pdmm1-sdi2 {
+ rockchip,pins =
+ /* pdm_sdi2_m1 */
+ <4 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi3: pdmm1-sdi3 {
+ rockchip,pins =
+ /* pdm_sdi3_m1 */
+ <4 RK_PA6 4 &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ /omit-if-no-ref/
+ pmic_int: pmic-int {
+ rockchip,pins =
+ <0 RK_PA3 0 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ soc_slppin_gpio: soc-slppin-gpio {
+ rockchip,pins =
+ <0 RK_PA2 0 &pcfg_output_low>;
+ };
+
+ /omit-if-no-ref/
+ soc_slppin_slp: soc-slppin-slp {
+ rockchip,pins =
+ <0 RK_PA2 1 &pcfg_pull_none>;
+ };
+ };
+
+ pmu {
+ /omit-if-no-ref/
+ pmu_pins: pmu-pins {
+ rockchip,pins =
+ /* pmu_debug */
+ <0 RK_PA5 3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_pins: pwm0m0-pins {
+ rockchip,pins =
+ /* pwm0_m0 */
+ <0 RK_PC3 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_pins: pwm0m1-pins {
+ rockchip,pins =
+ /* pwm0_m1 */
+ <1 RK_PC5 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_pins: pwm1m0-pins {
+ rockchip,pins =
+ /* pwm1_m0 */
+ <0 RK_PC4 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_pins: pwm1m1-pins {
+ rockchip,pins =
+ /* pwm1_m1 */
+ <1 RK_PC6 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_pins: pwm2m0-pins {
+ rockchip,pins =
+ /* pwm2_m0 */
+ <0 RK_PC5 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_pins: pwm2m1-pins {
+ rockchip,pins =
+ /* pwm2_m1 */
+ <1 RK_PC7 3 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm3 {
+ /omit-if-no-ref/
+ pwm3m0_pins: pwm3m0-pins {
+ rockchip,pins =
+ /* pwm3_m0 */
+ <0 RK_PA7 1 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm3m1_pins: pwm3m1-pins {
+ rockchip,pins =
+ /* pwm3_m1 */
+ <1 RK_PD0 3 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm4 {
+ /omit-if-no-ref/
+ pwm4m0_pins: pwm4m0-pins {
+ rockchip,pins =
+ /* pwm4_m0 */
+ <0 RK_PB7 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm4m1_pins: pwm4m1-pins {
+ rockchip,pins =
+ /* pwm4_m1 */
+ <1 RK_PD1 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm5 {
+ /omit-if-no-ref/
+ pwm5m0_pins: pwm5m0-pins {
+ rockchip,pins =
+ /* pwm5_m0 */
+ <0 RK_PC2 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm5m1_pins: pwm5m1-pins {
+ rockchip,pins =
+ /* pwm5_m1 */
+ <1 RK_PD2 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm6 {
+ /omit-if-no-ref/
+ pwm6m0_pins: pwm6m0-pins {
+ rockchip,pins =
+ /* pwm6_m0 */
+ <0 RK_PC1 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm6m1_pins: pwm6m1-pins {
+ rockchip,pins =
+ /* pwm6_m1 */
+ <1 RK_PD3 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm7 {
+ /omit-if-no-ref/
+ pwm7m0_pins: pwm7m0-pins {
+ rockchip,pins =
+ /* pwm7_m0 */
+ <0 RK_PC0 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm7m1_pins: pwm7m1-pins {
+ rockchip,pins =
+ /* pwm7_m1 */
+ <1 RK_PD4 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm8 {
+ /omit-if-no-ref/
+ pwm8m0_pins: pwm8m0-pins {
+ rockchip,pins =
+ /* pwm8_m0 */
+ <3 RK_PA4 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm8m1_pins: pwm8m1-pins {
+ rockchip,pins =
+ /* pwm8_m1 */
+ <1 RK_PC1 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm9 {
+ /omit-if-no-ref/
+ pwm9m0_pins: pwm9m0-pins {
+ rockchip,pins =
+ /* pwm9_m0 */
+ <3 RK_PA5 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm9m1_pins: pwm9m1-pins {
+ rockchip,pins =
+ /* pwm9_m1 */
+ <1 RK_PC2 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm10 {
+ /omit-if-no-ref/
+ pwm10m0_pins: pwm10m0-pins {
+ rockchip,pins =
+ /* pwm10_m0 */
+ <1 RK_PB5 5 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm10m1_pins: pwm10m1-pins {
+ rockchip,pins =
+ /* pwm10_m1 */
+ <1 RK_PC3 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm11 {
+ /omit-if-no-ref/
+ pwm11m0_pins: pwm11m0-pins {
+ rockchip,pins =
+ /* pwm11_m0 */
+ <1 RK_PB6 5 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm11m1_pins: pwm11m1-pins {
+ rockchip,pins =
+ /* pwm11_m1 */
+ <1 RK_PC4 4 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm12 {
+ /omit-if-no-ref/
+ pwm12m0_pins: pwm12m0-pins {
+ rockchip,pins =
+ /* pwm12_m0 */
+ <4 RK_PA1 4 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm12m1_pins: pwm12m1-pins {
+ rockchip,pins =
+ /* pwm12_m1 */
+ <3 RK_PB4 5 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm13 {
+ /omit-if-no-ref/
+ pwm13m0_pins: pwm13m0-pins {
+ rockchip,pins =
+ /* pwm13_m0 */
+ <4 RK_PA4 3 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm13m1_pins: pwm13m1-pins {
+ rockchip,pins =
+ /* pwm13_m1 */
+ <3 RK_PB5 5 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm14 {
+ /omit-if-no-ref/
+ pwm14m0_pins: pwm14m0-pins {
+ rockchip,pins =
+ /* pwm14_m0 */
+ <3 RK_PC5 4 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm14m1_pins: pwm14m1-pins {
+ rockchip,pins =
+ /* pwm14_m1 */
+ <1 RK_PD7 5 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwm15 {
+ /omit-if-no-ref/
+ pwm15m0_pins: pwm15m0-pins {
+ rockchip,pins =
+ /* pwm15_m0 */
+ <3 RK_PC6 4 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ pwm15m1_pins: pwm15m1-pins {
+ rockchip,pins =
+ /* pwm15_m1 */
+ <2 RK_PA0 5 &pcfg_pull_none_drv_level_1>;
+ };
+ };
+
+ pwr {
+ /omit-if-no-ref/
+ pwr_pins: pwr-pins {
+ rockchip,pins =
+ /* pwr_ctrl0 */
+ <0 RK_PA2 1 &pcfg_pull_none>,
+ /* pwr_ctrl1 */
+ <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ };
+
+ ref {
+ /omit-if-no-ref/
+ ref_pins: ref-pins {
+ rockchip,pins =
+ /* ref_clk_out */
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+
+ rgmii {
+ /omit-if-no-ref/
+ rgmiim0_miim: rgmiim0-miim {
+ rockchip,pins =
+ /* rgmii_mdc_m0 */
+ <4 RK_PB2 2 &pcfg_pull_none>,
+ /* rgmii_mdio_m0 */
+ <4 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim0_rx_er: rgmiim0-rx_er {
+ rockchip,pins =
+ /* rgmii_rxer_m0 */
+ <4 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim0_rx_bus2: rgmiim0-rx_bus2 {
+ rockchip,pins =
+ /* rgmii_rxd0_m0 */
+ <4 RK_PA5 2 &pcfg_pull_none>,
+ /* rgmii_rxd1_m0 */
+ <4 RK_PA6 2 &pcfg_pull_none>,
+ /* rgmii_rxdv_m0 */
+ <4 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim0_tx_bus2: rgmiim0-tx_bus2 {
+ rockchip,pins =
+ /* rgmii_txd0_m0 */
+ <4 RK_PA2 2 &pcfg_pull_none>,
+ /* rgmii_txd1_m0 */
+ <4 RK_PA3 2 &pcfg_pull_none>,
+ /* rgmii_txen_m0 */
+ <4 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim0_rgmii_clk: rgmiim0-rgmii_clk {
+ rockchip,pins =
+ /* rgmii_rxclk_m0 */
+ <4 RK_PA1 2 &pcfg_pull_none>,
+ /* rgmii_txclk_m0 */
+ <3 RK_PD6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim0_rgmii_bus: rgmiim0-rgmii_bus {
+ rockchip,pins =
+ /* rgmii_rxd2_m0 */
+ <3 RK_PD7 2 &pcfg_pull_none>,
+ /* rgmii_rxd3_m0 */
+ <4 RK_PA0 2 &pcfg_pull_none>,
+ /* rgmii_txd2_m0 */
+ <3 RK_PD4 2 &pcfg_pull_none>,
+ /* rgmii_txd3_m0 */
+ <3 RK_PD5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim0_clk: rgmiim0-clk {
+ rockchip,pins =
+ /* rgmiim0_clk */
+ <4 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim1_miim: rgmiim1-miim {
+ rockchip,pins =
+ /* rgmii_mdc_m1 */
+ <1 RK_PC7 2 &pcfg_pull_none>,
+ /* rgmii_mdio_m1 */
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim1_rx_er: rgmiim1-rx_er {
+ rockchip,pins =
+ /* rgmii_rxer_m1 */
+ <2 RK_PA0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim1_rx_bus2: rgmiim1-rx_bus2 {
+ rockchip,pins =
+ /* rgmii_rxd0_m1 */
+ <1 RK_PD4 2 &pcfg_pull_none>,
+ /* rgmii_rxd1_m1 */
+ <1 RK_PD7 2 &pcfg_pull_none>,
+ /* rgmii_rxdv_m1 */
+ <1 RK_PD6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim1_tx_bus2: rgmiim1-tx_bus2 {
+ rockchip,pins =
+ /* rgmii_txd0_m1 */
+ <1 RK_PD1 2 &pcfg_pull_none>,
+ /* rgmii_txd1_m1 */
+ <1 RK_PD2 2 &pcfg_pull_none>,
+ /* rgmii_txen_m1 */
+ <1 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim1_rgmii_clk: rgmiim1-rgmii_clk {
+ rockchip,pins =
+ /* rgmii_rxclk_m1 */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* rgmii_txclk_m1 */
+ <1 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim1_rgmii_bus: rgmiim1-rgmii_bus {
+ rockchip,pins =
+ /* rgmii_rxd2_m1 */
+ <1 RK_PC4 2 &pcfg_pull_none>,
+ /* rgmii_rxd3_m1 */
+ <1 RK_PC5 2 &pcfg_pull_none>,
+ /* rgmii_txd2_m1 */
+ <1 RK_PC1 2 &pcfg_pull_none>,
+ /* rgmii_txd3_m1 */
+ <1 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmiim1_clk: rgmiim1-clk {
+ rockchip,pins =
+ /* rgmiim1_clk */
+ <1 RK_PD5 2 &pcfg_pull_none>;
+ };
+ };
+
+ rmii {
+ /omit-if-no-ref/
+ rmii_pins: rmii-pins {
+ rockchip,pins =
+ /* rmii_clk */
+ <1 RK_PD5 5 &pcfg_pull_none>,
+ /* rmii_mdc */
+ <1 RK_PC7 5 &pcfg_pull_none>,
+ /* rmii_mdio */
+ <1 RK_PD0 5 &pcfg_pull_none>,
+ /* rmii_rxd0 */
+ <1 RK_PD4 5 &pcfg_pull_none>,
+ /* rmii_rxd1 */
+ <1 RK_PD7 6 &pcfg_pull_none>,
+ /* rmii_rxdv_crs */
+ <1 RK_PD6 5 &pcfg_pull_none>,
+ /* rmii_rxer */
+ <2 RK_PA0 6 &pcfg_pull_none>,
+ /* rmii_txd0 */
+ <1 RK_PD1 5 &pcfg_pull_none>,
+ /* rmii_txd1 */
+ <1 RK_PD2 5 &pcfg_pull_none>,
+ /* rmii_txen */
+ <1 RK_PD3 5 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ /* sdmmc0_detn */
+ <0 RK_PA4 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_pwren: sdmmc0-pwren {
+ rockchip,pins =
+ /* sdmmc0_pwren */
+ <0 RK_PA5 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ /* sdmmc1_detn */
+ <1 RK_PD0 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_pwren: sdmmc1-pwren {
+ rockchip,pins =
+ /* sdmmc1_pwren */
+ <1 RK_PC7 1 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ /omit-if-no-ref/
+ spdifm0_pins: spdifm0-pins {
+ rockchip,pins =
+ /* spdif_tx_m0 */
+ <3 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_pins: spdifm1-pins {
+ rockchip,pins =
+ /* spdif_tx_m1 */
+ <0 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_pins: spdifm2-pins {
+ rockchip,pins =
+ /* spdif_tx_m2 */
+ <1 RK_PB7 2 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0m0_pins: spi0m0-pins {
+ rockchip,pins =
+ /* spi0_clk_m0 */
+ <0 RK_PC3 3 &pcfg_pull_none_drv_level_3>,
+ /* spi0_miso_m0 */
+ <0 RK_PC5 3 &pcfg_pull_none_drv_level_3>,
+ /* spi0_mosi_m0 */
+ <0 RK_PC4 3 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_csn0: spi0m0-csn0 {
+ rockchip,pins =
+ /* spi0m0_csn0 */
+ <0 RK_PC2 3 &pcfg_pull_none_drv_level_3>;
+ };
+ /omit-if-no-ref/
+ spi0m0_csn1: spi0m0-csn1 {
+ rockchip,pins =
+ /* spi0m0_csn1 */
+ <0 RK_PB7 1 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_pins: spi0m1-pins {
+ rockchip,pins =
+ /* spi0_clk_m1 */
+ <3 RK_PB5 4 &pcfg_pull_none_drv_level_3>,
+ /* spi0_miso_m1 */
+ <3 RK_PC0 4 &pcfg_pull_none_drv_level_3>,
+ /* spi0_mosi_m1 */
+ <3 RK_PB4 4 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_csn0: spi0m1-csn0 {
+ rockchip,pins =
+ /* spi0m1_csn0 */
+ <3 RK_PB7 4 &pcfg_pull_none_drv_level_3>;
+ };
+ /omit-if-no-ref/
+ spi0m1_csn1: spi0m1-csn1 {
+ rockchip,pins =
+ /* spi0m1_csn1 */
+ <3 RK_PB6 4 &pcfg_pull_none_drv_level_3>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1m0_pins: spi1m0-pins {
+ rockchip,pins =
+ /* spi1_clk_m0 */
+ <3 RK_PD6 4 &pcfg_pull_none_drv_level_3>,
+ /* spi1_miso_m0 */
+ <4 RK_PA3 4 &pcfg_pull_none_drv_level_3>,
+ /* spi1_mosi_m0 */
+ <4 RK_PA2 4 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_csn0: spi1m0-csn0 {
+ rockchip,pins =
+ /* spi1m0_csn0 */
+ <3 RK_PD7 4 &pcfg_pull_none_drv_level_3>;
+ };
+ /omit-if-no-ref/
+ spi1m0_csn1: spi1m0-csn1 {
+ rockchip,pins =
+ /* spi1m0_csn1 */
+ <4 RK_PA0 4 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_pins: spi1m1-pins {
+ rockchip,pins =
+ /* spi1_clk_m1 */
+ <1 RK_PC0 4 &pcfg_pull_none_drv_level_3>,
+ /* spi1_miso_m1 */
+ <1 RK_PB4 4 &pcfg_pull_none_drv_level_3>,
+ /* spi1_mosi_m1 */
+ <1 RK_PB3 4 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_csn0: spi1m1-csn0 {
+ rockchip,pins =
+ /* spi1m1_csn0 */
+ <1 RK_PB6 4 &pcfg_pull_none_drv_level_3>;
+ };
+ /omit-if-no-ref/
+ spi1m1_csn1: spi1m1-csn1 {
+ rockchip,pins =
+ /* spi1m1_csn1 */
+ <1 RK_PB5 4 &pcfg_pull_none_drv_level_3>;
+ };
+ };
+
+ spi2 {
+ /omit-if-no-ref/
+ spi2m0_pins: spi2m0-pins {
+ rockchip,pins =
+ /* spi2_clk_m0 */
+ <4 RK_PB6 4 &pcfg_pull_none_drv_level_3>,
+ /* spi2_miso_m0 */
+ <3 RK_PD2 4 &pcfg_pull_none_drv_level_3>,
+ /* spi2_mosi_m0 */
+ <3 RK_PD3 4 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_csn0: spi2m0-csn0 {
+ rockchip,pins =
+ /* spi2m0_csn0 */
+ <4 RK_PB5 4 &pcfg_pull_none_drv_level_3>;
+ };
+ /omit-if-no-ref/
+ spi2m0_csn1: spi2m0-csn1 {
+ rockchip,pins =
+ /* spi2m0_csn1 */
+ <4 RK_PB4 4 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_pins: spi2m1-pins {
+ rockchip,pins =
+ /* spi2_clk_m1 */
+ <2 RK_PA1 4 &pcfg_pull_none_drv_level_3>,
+ /* spi2_miso_m1 */
+ <2 RK_PA0 4 &pcfg_pull_none_drv_level_3>,
+ /* spi2_mosi_m1 */
+ <1 RK_PD7 4 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_csn0: spi2m1-csn0 {
+ rockchip,pins =
+ /* spi2m1_csn0 */
+ <1 RK_PD6 4 &pcfg_pull_none_drv_level_3>;
+ };
+ /omit-if-no-ref/
+ spi2m1_csn1: spi2m1-csn1 {
+ rockchip,pins =
+ /* spi2m1_csn1 */
+ <1 RK_PD5 4 &pcfg_pull_none_drv_level_3>;
+ };
+ };
+
+ tsadc {
+ /omit-if-no-ref/
+ tsadcm0_pins: tsadcm0-pins {
+ rockchip,pins =
+ /* tsadc_shut_m0 */
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadcm1_pins: tsadcm1-pins {
+ rockchip,pins =
+ /* tsadc_shut_m1 */
+ <0 RK_PA2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadc_shut_org: tsadc-shut-org {
+ rockchip,pins =
+ /* tsadc_shut_org */
+ <0 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0m0_xfer: uart0m0-xfer {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <0 RK_PD0 1 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <0 RK_PD1 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m1_xfer: uart0m1-xfer {
+ rockchip,pins =
+ /* uart0_rx_m1 */
+ <1 RK_PB3 2 &pcfg_pull_up>,
+ /* uart0_tx_m1 */
+ <1 RK_PB4 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <1 RK_PD1 1 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <1 RK_PD2 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_ctsn: uart1m0-ctsn {
+ rockchip,pins =
+ /* uart1m0_ctsn */
+ <1 RK_PD4 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1m0_rtsn: uart1m0-rtsn {
+ rockchip,pins =
+ /* uart1m0_rtsn */
+ <1 RK_PD3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rx_m1 */
+ <4 RK_PA6 3 &pcfg_pull_up>,
+ /* uart1_tx_m1 */
+ <4 RK_PA5 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_ctsn: uart1m1-ctsn {
+ rockchip,pins =
+ /* uart1m1_ctsn */
+ <4 RK_PB0 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1m1_rtsn: uart1m1-rtsn {
+ rockchip,pins =
+ /* uart1m1_rtsn */
+ <4 RK_PA7 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <0 RK_PC1 1 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <0 RK_PC0 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m0_ctsn: uart2m0-ctsn {
+ rockchip,pins =
+ /* uart2m0_ctsn */
+ <0 RK_PC2 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m0_rtsn: uart2m0-rtsn {
+ rockchip,pins =
+ /* uart2m0_rtsn */
+ <0 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <3 RK_PA1 2 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <3 RK_PA0 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_ctsn: uart2m1-ctsn {
+ rockchip,pins =
+ /* uart2m1_ctsn */
+ <3 RK_PA2 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m1_rtsn: uart2m1-rtsn {
+ rockchip,pins =
+ /* uart2m1_rtsn */
+ <3 RK_PA3 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <4 RK_PB5 6 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <4 RK_PB4 6 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m0_ctsn: uart3m0-ctsn {
+ rockchip,pins =
+ /* uart3m0_ctsn */
+ <4 RK_PB6 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart3m0_rtsn: uart3m0-rtsn {
+ rockchip,pins =
+ /* uart3m0_rtsn */
+ <3 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rx_m1 */
+ <3 RK_PC0 3 &pcfg_pull_up>,
+ /* uart3_tx_m1 */
+ <3 RK_PB7 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_ctsn: uart3m1-ctsn {
+ rockchip,pins =
+ /* uart3m1_ctsn */
+ <3 RK_PB6 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart3m1_rtsn: uart3m1-rtsn {
+ rockchip,pins =
+ /* uart3m1_rtsn */
+ <3 RK_PC1 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <3 RK_PD1 3 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <3 RK_PD0 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m0_ctsn: uart4m0-ctsn {
+ rockchip,pins =
+ /* uart4m0_ctsn */
+ <3 RK_PC5 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart4m0_rtsn: uart4m0-rtsn {
+ rockchip,pins =
+ /* uart4m0_rtsn */
+ <3 RK_PC6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_xfer: uart4m1-xfer {
+ rockchip,pins =
+ /* uart4_rx_m1 */
+ <1 RK_PD5 3 &pcfg_pull_up>,
+ /* uart4_tx_m1 */
+ <1 RK_PD6 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_ctsn: uart4m1-ctsn {
+ rockchip,pins =
+ /* uart4m1_ctsn */
+ <2 RK_PA0 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart4m1_rtsn: uart4m1-rtsn {
+ rockchip,pins =
+ /* uart4m1_rtsn */
+ <1 RK_PD7 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <1 RK_PB7 3 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <1 RK_PC0 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <1 RK_PB5 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <1 RK_PB6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rx_m1 */
+ <3 RK_PA7 5 &pcfg_pull_up>,
+ /* uart5_tx_m1 */
+ <3 RK_PA6 5 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_ctsn: uart5m1-ctsn {
+ rockchip,pins =
+ /* uart5m1_ctsn */
+ <3 RK_PA0 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart5m1_rtsn: uart5m1-rtsn {
+ rockchip,pins =
+ /* uart5m1_rtsn */
+ <3 RK_PA1 5 &pcfg_pull_none>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rx_m0 */
+ <0 RK_PC7 1 &pcfg_pull_up>,
+ /* uart6_tx_m0 */
+ <0 RK_PC6 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_ctsn: uart6m0-ctsn {
+ rockchip,pins =
+ /* uart6m0_ctsn */
+ <0 RK_PC4 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart6m0_rtsn: uart6m0-rtsn {
+ rockchip,pins =
+ /* uart6m0_rtsn */
+ <0 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rx_m1 */
+ <4 RK_PB0 5 &pcfg_pull_up>,
+ /* uart6_tx_m1 */
+ <4 RK_PA7 5 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_ctsn: uart6m1-ctsn {
+ rockchip,pins =
+ /* uart6m1_ctsn */
+ <4 RK_PA2 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart6m1_rtsn: uart6m1-rtsn {
+ rockchip,pins =
+ /* uart6m1_rtsn */
+ <4 RK_PA3 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rx_m0 */
+ <3 RK_PC7 3 &pcfg_pull_up>,
+ /* uart7_tx_m0 */
+ <3 RK_PC4 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <3 RK_PD2 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <3 RK_PD3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rx_m1 */
+ <1 RK_PB3 3 &pcfg_pull_up>,
+ /* uart7_tx_m1 */
+ <1 RK_PB4 3 &pcfg_pull_up>;
+ };
+ };
+
+ uart8 {
+ /omit-if-no-ref/
+ uart8m0_xfer: uart8m0-xfer {
+ rockchip,pins =
+ /* uart8_rx_m0 */
+ <3 RK_PB3 3 &pcfg_pull_up>,
+ /* uart8_tx_m0 */
+ <3 RK_PB2 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_ctsn: uart8m0-ctsn {
+ rockchip,pins =
+ /* uart8m0_ctsn */
+ <3 RK_PB4 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart8m0_rtsn: uart8m0-rtsn {
+ rockchip,pins =
+ /* uart8m0_rtsn */
+ <3 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_xfer: uart8m1-xfer {
+ rockchip,pins =
+ /* uart8_rx_m1 */
+ <3 RK_PD5 3 &pcfg_pull_up>,
+ /* uart8_tx_m1 */
+ <3 RK_PD4 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_ctsn: uart8m1-ctsn {
+ rockchip,pins =
+ /* uart8m1_ctsn */
+ <3 RK_PD7 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart8m1_rtsn: uart8m1-rtsn {
+ rockchip,pins =
+ /* uart8m1_rtsn */
+ <4 RK_PA0 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart9 {
+ /omit-if-no-ref/
+ uart9m0_xfer: uart9m0-xfer {
+ rockchip,pins =
+ /* uart9_rx_m0 */
+ <4 RK_PB3 3 &pcfg_pull_up>,
+ /* uart9_tx_m0 */
+ <4 RK_PB2 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_ctsn: uart9m0-ctsn {
+ rockchip,pins =
+ /* uart9m0_ctsn */
+ <4 RK_PB4 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart9m0_rtsn: uart9m0-rtsn {
+ rockchip,pins =
+ /* uart9m0_rtsn */
+ <4 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_xfer: uart9m1-xfer {
+ rockchip,pins =
+ /* uart9_rx_m1 */
+ <3 RK_PC3 3 &pcfg_pull_up>,
+ /* uart9_tx_m1 */
+ <3 RK_PC2 3 &pcfg_pull_up>;
+ };
+ };
+
+ vo {
+ /omit-if-no-ref/
+ vo_pins: vo-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
+ /* vo_lcdc_d0 */
+ <4 RK_PA4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d1 */
+ <4 RK_PA5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d2 */
+ <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d3 */
+ <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d7 */
+ <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d8 */
+ <4 RK_PA6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d9 */
+ <4 RK_PA7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d10 */
+ <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d11 */
+ <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d12 */
+ <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d13 */
+ <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d14 */
+ <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d15 */
+ <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d16 */
+ <4 RK_PB0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d17 */
+ <4 RK_PB1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d18 */
+ <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d19 */
+ <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d20 */
+ <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d21 */
+ <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d22 */
+ <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d23 */
+ <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_den */
+ <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_hsync */
+ <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_vsync */
+ <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
+ };
+ };
+};
+
+/*
+ * This part is edited handly.
+ */
+&pinctrl {
+ vo {
+ /omit-if-no-ref/
+ bt1120_pins: bt1120-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
+ /* vo_lcdc_d3 */
+ <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d7 */
+ <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d10 */
+ <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d11 */
+ <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d12 */
+ <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d13 */
+ <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d14 */
+ <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d15 */
+ <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d19 */
+ <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d20 */
+ <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d21 */
+ <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d22 */
+ <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d23 */
+ <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ bt656_pins: bt656-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
+ /* vo_lcdc_d3 */
+ <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d7 */
+ <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d10 */
+ <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d11 */
+ <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d12 */
+ <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ rgb3x8_pins_m0: rgb3x8-pins-m0 {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
+ /* vo_lcdc_d3 */
+ <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d7 */
+ <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d10 */
+ <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d11 */
+ <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d12 */
+ <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_den */
+ <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_hsync */
+ <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_vsync */
+ <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ rgb3x8_pins_m1: rgb3x8-pins-m1 {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
+ /* vo_lcdc_d13 */
+ <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d14 */
+ <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d15 */
+ <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d19 */
+ <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d20 */
+ <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d21 */
+ <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d22 */
+ <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d23 */
+ <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_den */
+ <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_hsync */
+ <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_vsync */
+ <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ rgb565_pins: rgb565-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
+ /* vo_lcdc_d3 */
+ <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d7 */
+ <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d10 */
+ <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d11 */
+ <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d12 */
+ <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d13 */
+ <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d14 */
+ <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d15 */
+ <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d19 */
+ <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d20 */
+ <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d21 */
+ <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d22 */
+ <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d23 */
+ <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_den */
+ <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_hsync */
+ <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_vsync */
+ <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ rgb666_pins: rgb666-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
+ /* vo_lcdc_d2 */
+ <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d3 */
+ <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d7 */
+ <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d10 */
+ <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d11 */
+ <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d12 */
+ <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d13 */
+ <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d14 */
+ <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d15 */
+ <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d18 */
+ <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d19 */
+ <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d20 */
+ <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d21 */
+ <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d22 */
+ <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_d23 */
+ <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_den */
+ <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_hsync */
+ <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
+ /* vo_lcdc_vsync */
+ <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
new file mode 100644
index 000000000000..b867b879d1d7
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
@@ -0,0 +1,1187 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rockchip,rk3562-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/rockchip,rk3562-power.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/reset/rockchip,rk3562-cru.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "rockchip,rk3562";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ };
+
+ xin32k: clock-xin32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+
+ xin24m: clock-xin24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clocks = <&scmi_clk ARMCLK>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <138>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ clocks = <&scmi_clk ARMCLK>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <138>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ clocks = <&scmi_clk ARMCLK>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <138>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ clocks = <&scmi_clk ARMCLK>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <138>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ };
+ };
+ };
+
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <825000 825000 1150000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <825000 825000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <825000 825000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <850000 850000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <925000 925000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1000000 1000000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-supported-hw = <0xf9 0xffff>;
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1037500 1037500 1150000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1125000 1125000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1150000 1150000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+
+ };
+
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <825000 825000 1000000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <825000 825000 1000000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <825000 825000 1000000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <825000 825000 1000000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <900000 900000 1000000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <950000 950000 1000000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ };
+ };
+
+ arm_pmu: arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ shmem = <&scmi_shmem>;
+ arm,smc-id = <0x82000010>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scmi_shmem: shmem@10f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ no-map;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@fe901000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xfe901000 0 0x1000>,
+ <0x0 0xfe902000 0 0x2000>,
+ <0x0 0xfe904000 0 0x2000>,
+ <0x0 0xfe906000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ qos_dma2ddr: qos@fee03800 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee03800 0x0 0x20>;
+ };
+
+ qos_mcu: qos@fee10000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee10000 0x0 0x20>;
+ };
+
+ qos_dft_apb: qos@fee10100 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee10100 0x0 0x20>;
+ };
+
+ qos_gmac: qos@fee10200 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee10200 0x0 0x20>;
+ };
+
+ qos_mac100: qos@fee10300 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee10300 0x0 0x20>;
+ };
+
+ qos_dcf: qos@fee10400 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee10400 0x0 0x20>;
+ };
+
+ qos_cpu: qos@fee20000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee20000 0x0 0x20>;
+ };
+
+ qos_gpu: qos@fee30000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee30000 0x0 0x20>;
+ };
+
+ qos_npu: qos@fee40000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee40000 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@fee50000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee50000 0x0 0x20>;
+ };
+
+ qos_vepu: qos@fee60000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee60000 0x0 0x20>;
+ };
+
+ qos_isp: qos@fee70000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee70000 0x0 0x20>;
+ };
+
+ qos_vicap: qos@fee70100 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee70100 0x0 0x20>;
+ };
+
+ qos_vop: qos@fee80000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee80000 0x0 0x20>;
+ };
+
+ qos_jpeg: qos@fee90000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee90000 0x0 0x20>;
+ };
+
+ qos_rga_rd: qos@fee90100 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee90100 0x0 0x20>;
+ };
+
+ qos_rga_wr: qos@fee90200 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfee90200 0x0 0x20>;
+ };
+
+ qos_pcie: qos@feea0000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeea0000 0x0 0x20>;
+ };
+
+ qos_usb3: qos@feea0100 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeea0100 0x0 0x20>;
+ };
+
+ qos_crypto_apb: qos@feeb0000 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeeb0000 0x0 0x20>;
+ };
+
+ qos_crypto: qos@feeb0100 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeeb0100 0x0 0x20>;
+ };
+
+ qos_dmac: qos@feeb0200 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeeb0200 0x0 0x20>;
+ };
+
+ qos_emmc: qos@feeb0300 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeeb0300 0x0 0x20>;
+ };
+
+ qos_fspi: qos@feeb0400 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeeb0400 0x0 0x20>;
+ };
+
+ qos_rkdma: qos@feeb0500 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeeb0500 0x0 0x20>;
+ };
+
+ qos_sdmmc0: qos@feeb0600 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeeb0600 0x0 0x20>;
+ };
+
+ qos_sdmmc1: qos@feeb0700 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeeb0700 0x0 0x20>;
+ };
+
+ qos_usb2: qos@feeb0800 {
+ compatible = "rockchip,rk3562-qos", "syscon";
+ reg = <0x0 0xfeeb0800 0x0 0x20>;
+ };
+
+ pmu_grf: syscon@ff010000 {
+ compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff010000 0x0 0x10000>;
+
+ reboot_mode: reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x220>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ };
+ };
+
+ sys_grf: syscon@ff030000 {
+ compatible = "rockchip,rk3562-sys-grf", "syscon";
+ reg = <0x0 0xff030000 0x0 0x10000>;
+ };
+
+ peri_grf: syscon@ff040000 {
+ compatible = "rockchip,rk3562-peri-grf", "syscon";
+ reg = <0x0 0xff040000 0x0 0x10000>;
+ };
+
+ ioc_grf: syscon@ff060000 {
+ compatible = "rockchip,rk3562-ioc-grf", "syscon";
+ reg = <0x0 0xff060000 0x0 0x30000>;
+ };
+
+ usbphy_grf: syscon@ff090000 {
+ compatible = "rockchip,rk3562-usbphy-grf", "syscon";
+ reg = <0x0 0xff090000 0x0 0x8000>;
+ };
+
+ pipephy_grf: syscon@ff098000 {
+ compatible = "rockchip,rk3562-pipephy-grf", "syscon";
+ reg = <0x0 0xff098000 0x0 0x8000>;
+ };
+
+ cru: clock-controller@ff100000 {
+ compatible = "rockchip,rk3562-cru";
+ reg = <0x0 0xff100000 0x0 0x40000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ <&cru PLL_HPLL>;
+ assigned-clock-rates = <1188000000>, <1000000000>,
+ <983040000>;
+ };
+
+ i2c0: i2c@ff200000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff200000 0x0 0x1000>;
+ clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@ff210000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff210000 0x0 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi0: spi@ff220000 {
+ compatible = "rockchip,rk3562-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xff220000 0x0 0x1000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 13>, <&dmac 12>;
+ dma-names = "tx", "rx";
+ num-cs = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@ff230000 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff230000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm0m0_pins>;
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@ff230010 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff230010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm1m0_pins>;
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm2: pwm@ff230020 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff230020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2m0_pins>;
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm3: pwm@ff230030 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff230030 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm3m0_pins>;
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pmu: power-management@ff258000 {
+ compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff258000 0x0 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3562-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+
+ power-domain@RK3562_PD_GPU {
+ reg = <RK3562_PD_GPU>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3562_PD_NPU {
+ reg = <RK3562_PD_NPU>;
+ pm_qos = <&qos_npu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3562_PD_VDPU {
+ reg = <RK3562_PD_VDPU>;
+ pm_qos = <&qos_rkvdec>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3562_PD_VI {
+ reg = <RK3562_PD_VI>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pm_qos = <&qos_isp>,
+ <&qos_vicap>;
+
+ power-domain@RK3562_PD_VEPU {
+ reg = <RK3562_PD_VEPU>;
+ pm_qos = <&qos_vepu>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@RK3562_PD_VO {
+ reg = <RK3562_PD_VO>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pm_qos = <&qos_vop>;
+
+ power-domain@RK3562_PD_RGA {
+ reg = <RK3562_PD_RGA>;
+ pm_qos = <&qos_rga_rd>,
+ <&qos_rga_wr>,
+ <&qos_jpeg>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@RK3562_PD_PHP {
+ reg = <RK3562_PD_PHP>;
+ pm_qos = <&qos_pcie>,
+ <&qos_usb3>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ gpu: gpu@ff320000 {
+ compatible = "rockchip,rk3562-mali", "arm,mali-bifrost";
+ reg = <0x0 0xff320000 0x0 0x4000>;
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_BRG>,
+ <&cru ACLK_GPU_PRE>;
+ clock-names = "clk_gpu", "clk_gpu_brg", "aclk_gpu";
+ dynamic-power-coefficient = <820>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3562_PD_GPU>;
+ #cooling-cells = <2>;
+ status = "disabled";
+ };
+
+ pcie2x1: pcie@ff500000 {
+ compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
+ <&cru CLK_PCIE20_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
+ <0 0 0 2 &pcie2x1_intc 1>,
+ <0 0 0 3 &pcie2x1_intc 2>,
+ <0 0 0 4 &pcie2x1_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
+ phys = <&combphy_pu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3562_PD_PHP>;
+ ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
+ 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
+ 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
+ reg = <0x0 0xfe000000 0x0 0x400000>,
+ <0x0 0xff500000 0x0 0x10000>,
+ <0x0 0xfc000000 0x0 0x100000>;
+ reg-names = "dbi", "apb", "config";
+ resets = <&cru SRST_PCIE20_POWERUP>;
+ reset-names = "pipe";
+ status = "disabled";
+
+ pcie2x1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ spi1: spi@ff640000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xff640000 0x0 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 15>, <&dmac 14>;
+ dma-names = "tx", "rx";
+ num-cs = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
+ status = "disabled";
+ };
+
+ spi2: spi@ff650000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xff650000 0x0 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 17>, <&dmac 16>;
+ dma-names = "tx", "rx";
+ num-cs = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
+ status = "disabled";
+ };
+
+ uart1: serial@ff670000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff670000 0x0 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@ff680000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff680000 0x0 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@ff690000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff690000 0x0 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial@ff6a0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart5: serial@ff6b0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6b0000 0x0 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart6: serial@ff6c0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6c0000 0x0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart7: serial@ff6d0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6d0000 0x0 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart8: serial@ff6e0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6e0000 0x0 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart9: serial@ff6f0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6f0000 0x0 0x100>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@ff700000 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff700000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm4m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm5: pwm@ff700010 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff700010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm5m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm6: pwm@ff700020 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff700020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm6m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm7: pwm@ff700030 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff700030 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm7m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm8: pwm@ff710000 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff710000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm8m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm9: pwm@ff710010 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff710010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm9m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm10: pwm@ff710020 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff710020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm10m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm11: pwm@ff710030 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff710030 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm11m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm12: pwm@ff720000 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff720000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm12m0_pins>;
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm13: pwm@ff720010 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff720010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm13m0_pins>;
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm14: pwm@ff720020 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff720020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm14m0_pins>;
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm15: pwm@ff720030 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff720030 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm15m0_pins>;
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ saradc0: adc@ff730000 {
+ compatible = "rockchip,rk3562-saradc";
+ reg = <0x0 0xff730000 0x0 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ combphy_pu: phy@ff750000 {
+ compatible = "rockchip,rk3562-naneng-combphy";
+ reg = <0x0 0xff750000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>,
+ <&cru PCLK_PHP>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&cru CLK_PIPEPHY_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY>;
+ reset-names = "phy";
+ rockchip,pipe-grf = <&peri_grf>;
+ rockchip,pipe-phy-grf = <&pipephy_grf>;
+ status = "disabled";
+ };
+
+ sfc: spi@ff860000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff860000 0x0 0x10000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sdhci: mmc@ff870000 {
+ compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3588-dwcmshc";
+ reg = <0x0 0xff870000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>;
+ assigned-clock-rates = <200000000>, <200000000>;
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TMCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ sdmmc0: mmc@ff880000 {
+ compatible = "rockchip,rk3562-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff880000 0x0 0x10000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>,
+ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ resets = <&cru SRST_H_SDMMC0>;
+ reset-names = "reset";
+ fifo-depth = <0x100>;
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@ff890000 {
+ compatible = "rockchip,rk3562-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff890000 0x0 0x10000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>,
+ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ resets = <&cru SRST_H_SDMMC1>;
+ reset-names = "reset";
+ fifo-depth = <0x100>;
+ status = "disabled";
+ };
+
+ dmac: dma-controller@ff990000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff990000 0x0 0x4000>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ };
+
+ i2c1: i2c@ffa00000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa00000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ffa10000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa10000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ffa20000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa20000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@ffa30000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa30000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@ffa40000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa40000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ saradc1: adc@ffaa0000 {
+ compatible = "rockchip,rk3562-saradc";
+ reg = <0x0 0xffaa0000 0x0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC_VCCIO156>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3562-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff260000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff260000 0x0 0x100>;
+ clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ff620000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff620000 0x0 0x100>;
+ clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ff630000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff630000 0x0 0x100>;
+ clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffac0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffac0000 0x0 0x100>;
+ clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffad0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffad0000 0x0 0x100>;
+ clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+ };
+ };
+};
+
+#include "rk3562-pinctrl.dtsi"
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC
[not found] ` <20250511100022.31465-1-amadeus@jmu.edu.cn>
@ 2025-05-11 10:14 ` Heiko Stübner
[not found] ` <20250511120009.37031-1-amadeus@jmu.edu.cn>
0 siblings, 1 reply; 8+ messages in thread
From: Heiko Stübner @ 2025-05-11 10:14 UTC (permalink / raw)
To: ziyao, Chukun Pan
Cc: andyshrk, conor+dt, damon.ding, devicetree, didi.debian, dsimic,
jbx6244, jing, krzk+dt, linux-arm-kernel, linux-kernel,
linux-rockchip, sebastian.reichel, Chukun Pan
Hi,
Am Sonntag, 11. Mai 2025, 12:00:22 Mitteleuropäische Sommerzeit schrieb Chukun Pan:
> > <snip>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> > @@ -0,0 +1,1187 @@
> > <snip>
> > +#include <dt-bindings/phy/phy.h>
> > +#include <dt-bindings/power/rockchip,rk3562-power.h>
> > +#include <dt-bindings/pinctrl/rockchip.h>
>
> Does this need to be sorted alphabetically?
the rk3562-power header is gone temporarily anyway (in another tree),
so I moved things to numbers temporarily and created
https://lore.kernel.org/r/20250510161531.2086706-1-heiko@sntech.de
to be applied after the merge-window.
>
> > <snip>
> > + idle-states {
> > + entry-method = "psci";
>
> It would be better to leave a blank line here.
added
> > + CPU_SLEEP: cpu-sleep {
>
> > <snip>
> > + pwm0: pwm@ff230000 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff230000 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
>
> It should be `pinctrl-names = "default";` for pwm, see also [1]
fixed the pinctrl
> > + pinctrl-0 = <&pwm0m0_pins>;
> > + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
> > + clock-names = "pwm", "pclk";
> > + status = "disabled";
> > + };
>
> The pinctrl should be placed below the clock.
fixed ordering
>
> > <snip>
> > + power: power-controller {
> > + compatible = "rockchip,rk3562-power-controller";
> > + #power-domain-cells = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "okay";
> > +
>
> `status = "okay"` is not needed here.
> Also remove extra blank lines.
dropped okay ... extra blank was already removing when applying
>
> > +
> > + power-domain@RK3562_PD_GPU {
> > <snip>
> > + power-domain@RK3562_PD_VI {
> > + reg = <RK3562_PD_VI>;
> > + #power-domain-cells = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + pm_qos = <&qos_isp>,
> > + <&qos_vicap>;
> > +
> > + power-domain@RK3562_PD_VEPU {
> > + reg = <RK3562_PD_VEPU>;
> > + pm_qos = <&qos_vepu>;
> > + #power-domain-cells = <0>;
>
> This line is missing a tab, resulting in an indentation error.
fixed the indentation
> > + };
> > + };
> > <snip>
>
> > + pcie2x1: pcie@ff500000 {
> > + compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
>
> #address-cells/#size-cells should be placed above `status = "disabled";`
> I think other nodes also need to change this. (Some for #pwm-cells)
moved them (and the #pwm-cells above)
> > + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
>
> I noticed that the bsp 5.10 kernel said that pcie only has 8 MSI vectors,
> [2][3] but in the bsp 6.1 kernel it changed to 32 MSI vectors [4].
>
> The rockchip documentation also says there are only 8 MSI vectors:
>
> [5] Page37 8.8 "RK3528/RK3562/RK3576可分配的MSI或者MSI-X总数是8个"
> Translate into English: "The total number of MSI or MSI-X that
> can be allocated by RK3528/RK3562/RK3576 is 8"
>
> We noticed this when supporting rk3528, so which one is correct?
I'll leave that for a fixup patch or further discussion ;-)
> > + phys = <&combphy_pu PHY_TYPE_PCIE>;
>
> s/combphy_pu/combphy
>
> > <snip>
> + combphy_pu: phy@ff750000 {
>
> Please change it to `combphy` like rk3568.
changed the naming.
> Heiko I know you just merged this, it's a bit offensive but I think
> it would be better to drop these patches and fix them further.
> Or kever would you like to send a fix patch? Although most of
> them are typo issues, it will take a few patches to fix it.
First of all, thanks for noticing all the bits and pieces to improve.
I di think I have now fixed up all the "regular" pieces you mentioned
and amended the commit accordingly:
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?id=1d2f65fa98ddcafdfd1ebcdb87105141861b584a
Heiko
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC
[not found] ` <20250511120009.37031-1-amadeus@jmu.edu.cn>
@ 2025-05-11 13:48 ` Heiko Stübner
2025-05-11 15:01 ` Chukun Pan
0 siblings, 1 reply; 8+ messages in thread
From: Heiko Stübner @ 2025-05-11 13:48 UTC (permalink / raw)
To: Chukun Pan
Cc: amadeus, andyshrk, conor+dt, damon.ding, devicetree, didi.debian,
dsimic, jbx6244, jing, krzk+dt, linux-arm-kernel, linux-kernel,
linux-rockchip, sebastian.reichel, ziyao
Am Sonntag, 11. Mai 2025, 14:00:09 Mitteleuropäische Sommerzeit schrieb Chukun Pan:
> > First of all, thanks for noticing all the bits and pieces to improve.
> > I di think I have now fixed up all the "regular" pieces you mentioned
> > and amended the commit accordingly:
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?id=1d2f65fa98ddcafdfd1ebcdb87105141861b584a
>
> Thanks a lot for the quick fix! It seems there is still a little problem:
>
> > <snip>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> > <snip>
> + gpu_opp_table: opp-table-gpu {
> + compatible = "operating-points-v2";
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + opp-microvolt = <825000 825000 1000000>;
> + };
> + opp-400000000 {
> + opp-hz = /bits/ 64 <400000000>;
>
> This line is missing a tab.
fixed :-) .
> + opp-microvolt = <825000 825000 1000000>;
> + };
> > <snip>
> + spi0: spi@ff220000 {
> + compatible = "rockchip,rk3562-spi", "rockchip,rk3066-spi";
> + reg = <0x0 0xff220000 0x0 0x1000>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
>
> Also needed here.
I might be blind, but I don't see a tab missing here? #adress-cells and
#size-cells are in the same level of indentation as the other properties
of spi0? I did move the -cells down though now.
> > <snip>
> > + pwm3: pwm@ff230030 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff230030 0x0 0x10>;
> > + #pwm-cells = <3>;
>
> Missed here.
adapted like the other pwm-nodes
> > <snip>
> > + power-domain@12 {
> > + reg = <12>;
> > + #power-domain-cells = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > ...
> > + power-domain@13 {
> > + reg = <13>;
> > + #power-domain-cells = <1>;
>
> Does #power/#address/#size need to be put under pm_qos?
moved
> > <snip>
> > + spi1: spi@ff640000 {
> > + compatible = "rockchip,rk3066-spi";
> > + reg = <0x0 0xff640000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > ...
> > + spi2: spi@ff650000 {
> > + compatible = "rockchip,rk3066-spi";
> > + reg = <0x0 0xff650000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Same here.
moved
>
> > <snip>
> > + pwm4: pwm@ff700000 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff700000 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm5: pwm@ff700010 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff700010 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm6: pwm@ff700020 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff700020 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm7: pwm@ff700030 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff700030 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm8: pwm@ff710000 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff710000 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm9: pwm@ff710010 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff710010 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm10: pwm@ff710020 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff710020 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm11: pwm@ff710030 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff710030 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm12: pwm@ff720000 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff720000 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm13: pwm@ff720010 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff720010 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm14: pwm@ff720020 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff720020 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
> > ...
> > + pwm15: pwm@ff720030 {
> > + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
> > + reg = <0x0 0xff720030 0x0 0x10>;
> > + #pwm-cells = <3>;
> > + pinctrl-names = "active";
>
> pinctrl and #pwm-cells forgot to change.
hopefully caught all pwms now
> > <snip>
> > + sdmmc0: mmc@ff880000 {
> > + compatible = "rockchip,rk3562-dw-mshc",
> > + "rockchip,rk3288-dw-mshc";
> > + reg = <0x0 0xff880000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> > + max-frequency = <200000000>;
> > ...
> > + sdmmc1: mmc@ff890000 {
> > + compatible = "rockchip,rk3562-dw-mshc",
> > + "rockchip,rk3288-dw-mshc";
> > + reg = <0x0 0xff890000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> > + max-frequency = <200000000>;
>
> max-frequency should be placed below clock
moved and also moved fifo-depth upwards between clock-names
and max-frequency
> > <snip>
> > + saradc0: adc@ff730000 {
> > + compatible = "rockchip,rk3562-saradc";
> > + reg = <0x0 0xff730000 0x0 0x100>;
> > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > + #io-channel-cells = <1>;
> > ...
> > + saradc1: adc@ffaa0000 {
> > + compatible = "rockchip,rk3562-saradc";
> > + reg = <0x0 0xffaa0000 0x0 0x100>;
> > + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
> > + #io-channel-cells = <1>;
>
> `#io-channel-cells` should be put above `status = "disabled";`
moved now :-)
Hopefully this now caught all the smallish issues.
Thanks a lot
Heiko
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC
2025-05-11 13:48 ` Heiko Stübner
@ 2025-05-11 15:01 ` Chukun Pan
2025-05-11 15:32 ` Heiko Stübner
0 siblings, 1 reply; 8+ messages in thread
From: Chukun Pan @ 2025-05-11 15:01 UTC (permalink / raw)
To: heiko
Cc: amadeus, ziyao, devicetree, linux-arm-kernel, linux-kernel,
linux-rockchip
Hi,
> I might be blind, but I don't see a tab missing here? #adress-cells and
> #size-cells are in the same level of indentation as the other properties
> of spi0? I did move the -cells down though now.
Sorry I didn't make it clear. This refers to -cells.
> hopefully caught all pwms now
The pinctrl-names of pwm4 to pwm15 are still "active".
> + saradc0: adc@ff730000 {
> + compatible = "rockchip,rk3562-saradc";
> + reg = <0x0 0xff730000 0x0 0x100>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> + #io-channel-cells = <1>;
> > `#io-channel-cells` should be put above `status = "disabled";`
>
> moved now :-)
It looks like saradc0 forgot to change.
Thanks,
Chukun
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC
2025-05-11 15:01 ` Chukun Pan
@ 2025-05-11 15:32 ` Heiko Stübner
0 siblings, 0 replies; 8+ messages in thread
From: Heiko Stübner @ 2025-05-11 15:32 UTC (permalink / raw)
To: Chukun Pan
Cc: amadeus, ziyao, devicetree, linux-arm-kernel, linux-kernel,
linux-rockchip
Am Sonntag, 11. Mai 2025, 17:01:01 Mitteleuropäische Sommerzeit schrieb Chukun Pan:
> Hi,
>
> > I might be blind, but I don't see a tab missing here? #adress-cells and
> > #size-cells are in the same level of indentation as the other properties
> > of spi0? I did move the -cells down though now.
>
> Sorry I didn't make it clear. This refers to -cells.
>
> > hopefully caught all pwms now
>
> The pinctrl-names of pwm4 to pwm15 are still "active".
>
> > + saradc0: adc@ff730000 {
> > + compatible = "rockchip,rk3562-saradc";
> > + reg = <0x0 0xff730000 0x0 0x100>;
> > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > + #io-channel-cells = <1>;
>
> > > `#io-channel-cells` should be put above `status = "disabled";`
> >
> > moved now :-)
>
> It looks like saradc0 forgot to change.
adapted the rk3562 dtsi again, with those last remants :-)
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC
2025-05-09 10:23 ` [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC Kever Yang
@ 2025-05-16 7:01 ` Chukun Pan
0 siblings, 0 replies; 8+ messages in thread
From: Chukun Pan @ 2025-05-16 7:01 UTC (permalink / raw)
To: kever.yang
Cc: conor+dt, devicetree, finley.xiao, heiko, krzk+dt,
linux-arm-kernel, linux-kernel, linux-rockchip, Chukun Pan
Hi,
I posted to the wrong thread before, so I resent this.
Sorry for the noise.
> <snip>
> + pcie2x1: pcie@ff500000 {
> + compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie";
> + bus-range = <0x0 0xff>;
> <snip>
> + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
I noticed that the bsp 5.10 kernel said that pcie only has 8 MSI vectors,
[1][2] but in the bsp 6.1 kernel it changed to 32 MSI vectors [3].
The rockchip documentation also says there are only 8 MSI vectors:
[4] Page37 8.8 "RK3528/RK3562/RK3576可分配的MSI或者MSI-X总数是8个"
Translate into English: "The total number of MSI or MSI-X that
can be allocated by RK3528/RK3562/RK3576 is 8"
We noticed this when supporting rk3528, so which one is correct?
[1] https://github.com/rockchip-linux/kernel/commit/4f0c9ccc79c373aa97084b3b1ab0651ca4248227
[2] https://github.com/rockchip-linux/kernel/commit/afb85c759cfadc4051c42a9703860071a9877f2e
[3] https://github.com/coolpi-george/coolpi-kernel/commit/522b94122ec797760dcd466851250cbdfafff50f
[4] https://github.com/ArmSoM/rk3506-rkr4.2-sdk/blob/main/docs/cn/Common/PCIe/Rockchip_Developer_Guide_PCIe_CN.pdf
Thanks,
Chukun
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-05-16 7:01 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-03-10 14:09 [PATCH] arm64: dts: rockchip: Fix PWM pinctrl names Yao Zi
2025-03-12 7:46 ` Heiko Stuebner
[not found] ` <20250511100022.31465-1-amadeus@jmu.edu.cn>
2025-05-11 10:14 ` [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC Heiko Stübner
[not found] ` <20250511120009.37031-1-amadeus@jmu.edu.cn>
2025-05-11 13:48 ` Heiko Stübner
2025-05-11 15:01 ` Chukun Pan
2025-05-11 15:32 ` Heiko Stübner
-- strict thread matches above, loose matches on Subject: below --
2025-05-09 10:23 [PATCH v7 0/5] rockchip: Add rk3562 SoC and evb support Kever Yang
2025-05-09 10:23 ` [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC Kever Yang
2025-05-16 7:01 ` Chukun Pan
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