From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8AD5C433E0 for ; Mon, 1 Mar 2021 16:35:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 812D964FD1 for ; Mon, 1 Mar 2021 16:35:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234518AbhCAQfX (ORCPT ); Mon, 1 Mar 2021 11:35:23 -0500 Received: from mailoutvs27.siol.net ([185.57.226.218]:37159 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231958AbhCAQbY (ORCPT ); Mon, 1 Mar 2021 11:31:24 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id C0EB3523279; Mon, 1 Mar 2021 17:30:19 +0100 (CET) X-Virus-Scanned: amavisd-new at psrvmta09.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta09.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id IJQ__SflOFvg; Mon, 1 Mar 2021 17:30:19 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 801E8524751; Mon, 1 Mar 2021 17:30:19 +0100 (CET) Received: from kista.localnet (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: jernej.skrabec@siol.net) by mail.siol.net (Postfix) with ESMTPA id DE7EC523279; Mon, 1 Mar 2021 17:30:18 +0100 (CET) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Maxime Ripard , Chen-Yu Tsai Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: allwinner: h6: Switch to macros for RSB clock/reset indices Date: Mon, 01 Mar 2021 17:30:18 +0100 Message-ID: <13801193.qezBNLBNKl@kista> In-Reply-To: <20210301162309.1225-1-wens@kernel.org> References: <20210301162309.1225-1-wens@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Chen-Yu, Dne ponedeljek, 01. marec 2021 ob 17:23:09 CET je Chen-Yu Tsai napisal(a): > From: Chen-Yu Tsai > > The macros for the clock and reset indices for the RSB hardware block > were replaced with raw numbers when the RSB controller node was added. > This was done to avoid cross-tree dependencies. > > Now that both the clk and DT changes have been merged, we can switch > back to using the macros. > > Fixes: aaad900757a6 ("arm64: dts: allwinner: h6: Add RSB controller node") > Signed-off-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec Best regards, Jernej