[PATCH 0/4] SoCFPGA: dts cleanups and SoCkit support

[PATCH 0/4] SoCFPGA: dts cleanups and SoCkit support

[Steffen Trumtrar]

Hi!

This series includes some minor cleanups (indentation and clock labels) and
reorders the socfpga dts hierarchy from
	socfpga.dtsi
	-> socfpga_$board.dts
	-> socfpga_$otherboard.dts
to
	socfpga.dtsi
	-> socfpga_cyclone5.dtsi
	--> socfpga_cyclone5_$board.dts
	--> socfpga_cyclone5_$otherboard.dts

The Socfpga is a SoC with an FPGA on board. This FPGA does not have to be a
Cyclone5.
The current socfpga_cyclone5.dts is however not specific to a SoC with this
combination, but describes one specific board: the Altera Cyclone5 Development Kit.
Therefore, I propose moving the common stuff to socfpga_cyclone5.dtsi as long as
it is as easy as now.

Finally, the series adds minimal support for the terasic SoCkit.

BTW: It seems there is no official maintainer(tree) for the socfpga dt stuff.
So, I rebased onto next-20130927.

Regards,
Steffen


Steffen Trumtrar (4):
  ARM: socfpga: dts: Move common nodes to cyclone5 dtsi
  ARM: socfpga: dts: Add support for terasic SoCkit
  ARM: socfpga: dts: cleanup indentation
  ARM: socfpga: dts: fix s2f_* clock name

 arch/arm/boot/dts/Makefile                         |   3 +-
 arch/arm/boot/dts/socfpga.dtsi                     | 296 ++++++++++-----------
 ...{socfpga_cyclone5.dts => socfpga_cyclone5.dtsi} |  20 --
 arch/arm/boot/dts/socfpga_cyclone5_socdk.dts       |  40 +++
 arch/arm/boot/dts/socfpga_cyclone5_sockit.dts      |  37 +++
 5 files changed, 227 insertions(+), 169 deletions(-)
 rename arch/arm/boot/dts/{socfpga_cyclone5.dts => socfpga_cyclone5.dtsi} (78%)
 create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
 create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_sockit.dts

-- 
1.8.4.rc3

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[PATCH 1/4] ARM: socfpga: dts: Move common nodes to cyclone5 dtsi

[Steffen Trumtrar]

The current socfpga_cyclone5.dts describes the Altera Cyclone5 SoC Development
Kit. The Cyclone5 includes a SoCFPGA, which itself can be included in other
SoC+FPGA combinations.

Instead of having to describe all Cyclone5 common nodes in every board specific
dts, move socfpga_cyclone5.dts to a dtsi and include this in a new dts for the
Development Kit.

Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 arch/arm/boot/dts/Makefile                         |  2 +-
 ...{socfpga_cyclone5.dts => socfpga_cyclone5.dtsi} | 20 -----------
 arch/arm/boot/dts/socfpga_cyclone5_socdk.dts       | 40 ++++++++++++++++++++++
 3 files changed, 41 insertions(+), 21 deletions(-)
 rename arch/arm/boot/dts/{socfpga_cyclone5.dts => socfpga_cyclone5.dtsi} (78%)
 create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_socdk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cf75889..fcace86 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -216,7 +216,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
 	r8a73a4-ape6evm-reference.dtb \
 	sh7372-mackerel.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb
-dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_socdk.dtb \
 	socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
 	spear1340-evb.dtb
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
similarity index 78%
rename from arch/arm/boot/dts/socfpga_cyclone5.dts
rename to arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 973999d..a8716f6 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -19,26 +19,6 @@
 /include/ "socfpga.dtsi"
 
 / {
-	model = "Altera SOCFPGA Cyclone V";
-	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
-
-	chosen {
-		bootargs = "console=ttyS0,57600";
-	};
-
-	memory {
-		name = "memory";
-		device_type = "memory";
-		reg = <0x0 0x40000000>; /* 1GB */
-	};
-
-	aliases {
-		/* this allow the ethaddr uboot environmnet variable contents
-		 * to be added to the gmac1 device tree blob.
-		 */
-		ethernet0 = &gmac1;
-	};
-
 	soc {
 		clkmgr@ffd04000 {
 			clocks {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
new file mode 100644
index 0000000..0ea6399
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -0,0 +1,40 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "Altera SOCFPGA Cyclone V SoC Development Kit";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,57600";
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		 * to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+};
-- 
1.8.4.rc3

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Re: [PATCH 1/4] ARM: socfpga: dts: Move common nodes to cyclone5 dtsi

[Dinh Nguyen]

Hi Steffen,

On Wed, 2013-10-02 at 09:35 +0200, Steffen Trumtrar wrote:
> The current socfpga_cyclone5.dts describes the Altera Cyclone5 SoC Development
> Kit. The Cyclone5 includes a SoCFPGA, which itself can be included in other
> SoC+FPGA combinations.
> 
> Instead of having to describe all Cyclone5 common nodes in every board specific
> dts, move socfpga_cyclone5.dts to a dtsi and include this in a new dts for the
> Development Kit.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
>  arch/arm/boot/dts/Makefile                         |  2 +-
>  ...{socfpga_cyclone5.dts => socfpga_cyclone5.dtsi} | 20 -----------
>  arch/arm/boot/dts/socfpga_cyclone5_socdk.dts       | 40 ++++++++++++++++++++++
>  3 files changed, 41 insertions(+), 21 deletions(-)
>  rename arch/arm/boot/dts/{socfpga_cyclone5.dts => socfpga_cyclone5.dtsi} (78%)
>  create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index cf75889..fcace86 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -216,7 +216,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
>  	r8a73a4-ape6evm-reference.dtb \
>  	sh7372-mackerel.dtb
>  dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb
> -dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
> +dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_socdk.dtb \
>  	socfpga_vt.dtb
>  dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
>  	spear1340-evb.dtb
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> similarity index 78%
> rename from arch/arm/boot/dts/socfpga_cyclone5.dts
> rename to arch/arm/boot/dts/socfpga_cyclone5.dtsi
> index 973999d..a8716f6 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> @@ -19,26 +19,6 @@
>  /include/ "socfpga.dtsi"
>  
>  / {
> -	model = "Altera SOCFPGA Cyclone V";
> -	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> -
> -	chosen {
> -		bootargs = "console=ttyS0,57600";
> -	};
> -
> -	memory {
> -		name = "memory";
> -		device_type = "memory";
> -		reg = <0x0 0x40000000>; /* 1GB */
> -	};
> -
> -	aliases {
> -		/* this allow the ethaddr uboot environmnet variable contents
> -		 * to be added to the gmac1 device tree blob.
> -		 */
> -		ethernet0 = &gmac1;
> -	};
> -
>  	soc {
>  		clkmgr@ffd04000 {
>  			clocks {
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> new file mode 100644
> index 0000000..0ea6399
> --- /dev/null
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> @@ -0,0 +1,40 @@
> +/*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/include/ "socfpga_cyclone5.dtsi"
> +
> +/ {
> +	model = "Altera SOCFPGA Cyclone V SoC Development Kit";
> +	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> +
> +	chosen {
> +		bootargs = "console=ttyS0,57600";

Thanks for doing this. It looks good. While you're at it can you make
this 115200? 57600 was early in the bring-up stage.

> +	};
> +
> +	memory {
> +		name = "memory";
> +		device_type = "memory";
> +		reg = <0x0 0x40000000>; /* 1GB */
> +	};
> +
> +	aliases {
> +		/* this allow the ethaddr uboot environmnet variable contents
> +		 * to be added to the gmac1 device tree blob.
> +		 */
> +		ethernet0 = &gmac1;
> +	};
> +};

With the change to 115200,

Acked-by: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>

I guess I need to get an Ack from the DTS maintainer(s) and I'll apply
it to my next-dt tree.

Dinh


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Re: [PATCH 1/4] ARM: socfpga: dts: Move common nodes to cyclone5 dtsi

[Steffen Trumtrar]

Hi Dinh,

On Thu, Oct 03, 2013 at 09:58:41AM -0500, Dinh Nguyen wrote:
> On Wed, 2013-10-02 at 09:35 +0200, Steffen Trumtrar wrote:
> > +/include/ "socfpga_cyclone5.dtsi"
> > +
> > +/ {
> > +	model = "Altera SOCFPGA Cyclone V SoC Development Kit";
> > +	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> > +
> > +	chosen {
> > +		bootargs = "console=ttyS0,57600";
> 
> Thanks for doing this. It looks good. While you're at it can you make
> this 115200? 57600 was early in the bring-up stage.
> 

I can also completely remove this. The question is: does u-boot need this
line or does it add this line itself?
We added basic support for SoCFPGA to barebox (well, it will go live with the
october release AFAIK. With SoCKit and SoCrates boards) and we normally do not
need to put the bootargs in the DT. So, I would be okay to remove this line
OR if u-boot uses it, change it to 115200. What do you think?

> > +	};
> > +
> > +	memory {
> > +		name = "memory";
> > +		device_type = "memory";
> > +		reg = <0x0 0x40000000>; /* 1GB */
> > +	};
> > +
> > +	aliases {
> > +		/* this allow the ethaddr uboot environmnet variable contents
> > +		 * to be added to the gmac1 device tree blob.
> > +		 */
> > +		ethernet0 = &gmac1;
> > +	};
> > +};
> 
> With the change to 115200,
> 
> Acked-by: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
> 

Thanks.

Regards,
Steffen

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Re: [PATCH 1/4] ARM: socfpga: dts: Move common nodes to cyclone5 dtsi

[Dinh Nguyen]

On Thu, 2013-10-03 at 18:37 +0200, Steffen Trumtrar wrote:
> Hi Dinh,
> 
> On Thu, Oct 03, 2013 at 09:58:41AM -0500, Dinh Nguyen wrote:
> > On Wed, 2013-10-02 at 09:35 +0200, Steffen Trumtrar wrote:
> > > +/include/ "socfpga_cyclone5.dtsi"
> > > +
> > > +/ {
> > > +	model = "Altera SOCFPGA Cyclone V SoC Development Kit";
> > > +	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> > > +
> > > +	chosen {
> > > +		bootargs = "console=ttyS0,57600";
> > 
> > Thanks for doing this. It looks good. While you're at it can you make
> > this 115200? 57600 was early in the bring-up stage.
> > 
> 
> I can also completely remove this. The question is: does u-boot need this
> line or does it add this line itself?
> We added basic support for SoCFPGA to barebox (well, it will go live with the
> october release AFAIK. With SoCKit and SoCrates boards) and we normally do not
> need to put the bootargs in the DT. So, I would be okay to remove this line
> OR if u-boot uses it, change it to 115200. What do you think?

If bootargs is not specified in uboot, then this dts bootargs will be
used. So yes, please change it to 115200.

Thanks,
Dinh
> 
> > > +	};
> > > +
> > > +	memory {
> > > +		name = "memory";
> > > +		device_type = "memory";
> > > +		reg = <0x0 0x40000000>; /* 1GB */
> > > +	};
> > > +
> > > +	aliases {
> > > +		/* this allow the ethaddr uboot environmnet variable contents
> > > +		 * to be added to the gmac1 device tree blob.
> > > +		 */
> > > +		ethernet0 = &gmac1;
> > > +	};
> > > +};
> > 
> > With the change to 115200,
> > 
> > Acked-by: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
> > 
> 
> Thanks.
> 
> Regards,
> Steffen
> 



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[PATCH 2/4] ARM: socfpga: dts: Add support for terasic SoCkit

[Steffen Trumtrar]

This adds basic support for the terasic SoCkit board.
The board includes an Altera Cyclone 5 SoC.

Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 arch/arm/boot/dts/Makefile                    |  1 +
 arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 37 +++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_sockit.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fcace86..7ce51f2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -217,6 +217,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
 	sh7372-mackerel.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_socdk.dtb \
+	socfpga_cyclone5_sockit.dtb \
 	socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
 	spear1340-evb.dtb
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
new file mode 100644
index 0000000..a194a4e
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2013 Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "Terasic SoCkit";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,57600";
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+};
+
+&gmac1 {
+	status = "okay";
+};
-- 
1.8.4.rc3

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Re: [PATCH 2/4] ARM: socfpga: dts: Add support for terasic SoCkit

[Dinh Nguyen]

On Wed, 2013-10-02 at 09:35 +0200, Steffen Trumtrar wrote:
> This adds basic support for the terasic SoCkit board.
> The board includes an Altera Cyclone 5 SoC.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
>  arch/arm/boot/dts/Makefile                    |  1 +
>  arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 37 +++++++++++++++++++++++++++
>  2 files changed, 38 insertions(+)
>  create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index fcace86..7ce51f2 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -217,6 +217,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
>  	sh7372-mackerel.dtb
>  dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb
>  dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_socdk.dtb \
> +	socfpga_cyclone5_sockit.dtb \
>  	socfpga_vt.dtb
>  dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
>  	spear1340-evb.dtb
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> new file mode 100644
> index 0000000..a194a4e
> --- /dev/null
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> @@ -0,0 +1,37 @@
> +/*
> + *  Copyright (C) 2013 Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/include/ "socfpga_cyclone5.dtsi"
> +
> +/ {
> +	model = "Terasic SoCkit";
> +	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> +
> +	chosen {
> +		bootargs = "console=ttyS0,57600";
> +	};
> +
> +	memory {
> +		name = "memory";
> +		device_type = "memory";
> +		reg = <0x0 0x40000000>; /* 1GB */
> +	};
> +};
> +
> +&gmac1 {
> +	status = "okay";
> +};

Acked-by: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>

Thanks,
Dinh



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[PATCH 3/4] ARM: socfpga: dts: cleanup indentation

[Steffen Trumtrar]

Some of the clock nodes and the rst-/sysmgr use wrong indentation.
Fix it.

Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 arch/arm/boot/dts/socfpga.dtsi | 290 ++++++++++++++++++++---------------------
 1 file changed, 145 insertions(+), 145 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index e273fa9..587096e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -243,197 +243,197 @@
 						};
 					};
 
-				mpu_periph_clk: mpu_periph_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&mpuclk>;
-					fixed-divider = <4>;
+					mpu_periph_clk: mpu_periph_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&mpuclk>;
+						fixed-divider = <4>;
 					};
 
-				mpu_l2_ram_clk: mpu_l2_ram_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&mpuclk>;
-					fixed-divider = <2>;
+					mpu_l2_ram_clk: mpu_l2_ram_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&mpuclk>;
+						fixed-divider = <2>;
 					};
 
-				l4_main_clk: l4_main_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&mainclk>;
-					clk-gate = <0x60 0>;
+					l4_main_clk: l4_main_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&mainclk>;
+						clk-gate = <0x60 0>;
 					};
 
-				l3_main_clk: l3_main_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&mainclk>;
+					l3_main_clk: l3_main_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&mainclk>;
 					};
 
-				l3_mp_clk: l3_mp_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&mainclk>;
-					div-reg = <0x64 0 2>;
-					clk-gate = <0x60 1>;
+					l3_mp_clk: l3_mp_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&mainclk>;
+						div-reg = <0x64 0 2>;
+						clk-gate = <0x60 1>;
 					};
 
-				l3_sp_clk: l3_sp_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&mainclk>;
-					div-reg = <0x64 2 2>;
-				};
+					l3_sp_clk: l3_sp_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&mainclk>;
+						div-reg = <0x64 2 2>;
+					};
 
-				l4_mp_clk: l4_mp_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&mainclk>, <&per_base_clk>;
-					div-reg = <0x64 4 3>;
-					clk-gate = <0x60 2>;
+					l4_mp_clk: l4_mp_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&mainclk>, <&per_base_clk>;
+						div-reg = <0x64 4 3>;
+						clk-gate = <0x60 2>;
 					};
 
-				l4_sp_clk: l4_sp_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&mainclk>, <&per_base_clk>;
-					div-reg = <0x64 7 3>;
-					clk-gate = <0x60 3>;
+					l4_sp_clk: l4_sp_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&mainclk>, <&per_base_clk>;
+						div-reg = <0x64 7 3>;
+						clk-gate = <0x60 3>;
 					};
 
-				dbg_at_clk: dbg_at_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&dbg_base_clk>;
-					div-reg = <0x68 0 2>;
-					clk-gate = <0x60 4>;
+					dbg_at_clk: dbg_at_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&dbg_base_clk>;
+						div-reg = <0x68 0 2>;
+						clk-gate = <0x60 4>;
 					};
 
-				dbg_clk: dbg_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&dbg_base_clk>;
-					div-reg = <0x68 2 2>;
-					clk-gate = <0x60 5>;
+					dbg_clk: dbg_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&dbg_base_clk>;
+						div-reg = <0x68 2 2>;
+						clk-gate = <0x60 5>;
 					};
 
-				dbg_trace_clk: dbg_trace_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&dbg_base_clk>;
-					div-reg = <0x6C 0 3>;
-					clk-gate = <0x60 6>;
+					dbg_trace_clk: dbg_trace_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&dbg_base_clk>;
+						div-reg = <0x6C 0 3>;
+						clk-gate = <0x60 6>;
 					};
 
-				dbg_timer_clk: dbg_timer_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&dbg_base_clk>;
-					clk-gate = <0x60 7>;
+					dbg_timer_clk: dbg_timer_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&dbg_base_clk>;
+						clk-gate = <0x60 7>;
 					};
 
-				cfg_clk: cfg_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&cfg_s2f_usr0_clk>;
-					clk-gate = <0x60 8>;
+					cfg_clk: cfg_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&cfg_s2f_usr0_clk>;
+						clk-gate = <0x60 8>;
 					};
 
-				s2f_user0_clk: s2f_user0_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&cfg_s2f_usr0_clk>;
-					clk-gate = <0x60 9>;
+					s2f_user0_clk: s2f_user0_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&cfg_s2f_usr0_clk>;
+						clk-gate = <0x60 9>;
 					};
 
-				emac_0_clk: emac_0_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&emac0_clk>;
-					clk-gate = <0xa0 0>;
+					emac_0_clk: emac_0_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&emac0_clk>;
+						clk-gate = <0xa0 0>;
 					};
 
-				emac_1_clk: emac_1_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&emac1_clk>;
-					clk-gate = <0xa0 1>;
+					emac_1_clk: emac_1_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&emac1_clk>;
+						clk-gate = <0xa0 1>;
 					};
 
-				usb_mp_clk: usb_mp_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&per_base_clk>;
-					clk-gate = <0xa0 2>;
-					div-reg = <0xa4 0 3>;
+					usb_mp_clk: usb_mp_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&per_base_clk>;
+						clk-gate = <0xa0 2>;
+						div-reg = <0xa4 0 3>;
 					};
 
-				spi_m_clk: spi_m_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&per_base_clk>;
-					clk-gate = <0xa0 3>;
-					div-reg = <0xa4 3 3>;
+					spi_m_clk: spi_m_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&per_base_clk>;
+						clk-gate = <0xa0 3>;
+						div-reg = <0xa4 3 3>;
 					};
 
-				can0_clk: can0_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&per_base_clk>;
-					clk-gate = <0xa0 4>;
-					div-reg = <0xa4 6 3>;
+					can0_clk: can0_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&per_base_clk>;
+						clk-gate = <0xa0 4>;
+						div-reg = <0xa4 6 3>;
 					};
 
-				can1_clk: can1_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&per_base_clk>;
-					clk-gate = <0xa0 5>;
-					div-reg = <0xa4 9 3>;
+					can1_clk: can1_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&per_base_clk>;
+						clk-gate = <0xa0 5>;
+						div-reg = <0xa4 9 3>;
 					};
 
-				gpio_db_clk: gpio_db_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&per_base_clk>;
-					clk-gate = <0xa0 6>;
-					div-reg = <0xa8 0 24>;
+					gpio_db_clk: gpio_db_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&per_base_clk>;
+						clk-gate = <0xa0 6>;
+						div-reg = <0xa8 0 24>;
 					};
 
-				s2f_user1_clk: s2f_user1_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&s2f_usr1_clk>;
-					clk-gate = <0xa0 7>;
+					s2f_user1_clk: s2f_user1_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&s2f_usr1_clk>;
+						clk-gate = <0xa0 7>;
 					};
 
-				sdmmc_clk: sdmmc_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
-					clk-gate = <0xa0 8>;
+					sdmmc_clk: sdmmc_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+						clk-gate = <0xa0 8>;
 					};
 
-				nand_x_clk: nand_x_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
-					clk-gate = <0xa0 9>;
+					nand_x_clk: nand_x_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+						clk-gate = <0xa0 9>;
 					};
 
-				nand_clk: nand_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
-					clk-gate = <0xa0 10>;
-					fixed-divider = <4>;
+					nand_clk: nand_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+						clk-gate = <0xa0 10>;
+						fixed-divider = <4>;
 					};
 
-				qspi_clk: qspi_clk {
-					#clock-cells = <0>;
-					compatible = "altr,socfpga-gate-clk";
-					clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
-					clk-gate = <0xa0 11>;
+					qspi_clk: qspi_clk {
+						#clock-cells = <0>;
+						compatible = "altr,socfpga-gate-clk";
+						clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+						clk-gate = <0xa0 11>;
 					};
 				};
 			};
@@ -516,9 +516,9 @@
 		};
 
 		rstmgr@ffd05000 {
-				compatible = "altr,rst-mgr";
-				reg = <0xffd05000 0x1000>;
-			};
+			compatible = "altr,rst-mgr";
+			reg = <0xffd05000 0x1000>;
+		};
 
 		sysmgr@ffd08000 {
 				compatible = "altr,sys-mgr";
-- 
1.8.4.rc3

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Re: [PATCH 3/4] ARM: socfpga: dts: cleanup indentation

[Dinh Nguyen]

On Wed, 2013-10-02 at 09:35 +0200, Steffen Trumtrar wrote:
> Some of the clock nodes and the rst-/sysmgr use wrong indentation.
> Fix it.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
>  arch/arm/boot/dts/socfpga.dtsi | 290 ++++++++++++++++++++---------------------
>  1 file changed, 145 insertions(+), 145 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index e273fa9..587096e 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -243,197 +243,197 @@
>  						};
>  					};
>  
> -				mpu_periph_clk: mpu_periph_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&mpuclk>;
> -					fixed-divider = <4>;
> +					mpu_periph_clk: mpu_periph_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&mpuclk>;
> +						fixed-divider = <4>;
>  					};
>  
> -				mpu_l2_ram_clk: mpu_l2_ram_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&mpuclk>;
> -					fixed-divider = <2>;
> +					mpu_l2_ram_clk: mpu_l2_ram_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&mpuclk>;
> +						fixed-divider = <2>;
>  					};
>  
> -				l4_main_clk: l4_main_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&mainclk>;
> -					clk-gate = <0x60 0>;
> +					l4_main_clk: l4_main_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&mainclk>;
> +						clk-gate = <0x60 0>;
>  					};
>  
> -				l3_main_clk: l3_main_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&mainclk>;
> +					l3_main_clk: l3_main_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&mainclk>;
>  					};
>  
> -				l3_mp_clk: l3_mp_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&mainclk>;
> -					div-reg = <0x64 0 2>;
> -					clk-gate = <0x60 1>;
> +					l3_mp_clk: l3_mp_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&mainclk>;
> +						div-reg = <0x64 0 2>;
> +						clk-gate = <0x60 1>;
>  					};
>  
> -				l3_sp_clk: l3_sp_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&mainclk>;
> -					div-reg = <0x64 2 2>;
> -				};
> +					l3_sp_clk: l3_sp_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&mainclk>;
> +						div-reg = <0x64 2 2>;
> +					};
>  
> -				l4_mp_clk: l4_mp_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&mainclk>, <&per_base_clk>;
> -					div-reg = <0x64 4 3>;
> -					clk-gate = <0x60 2>;
> +					l4_mp_clk: l4_mp_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&mainclk>, <&per_base_clk>;
> +						div-reg = <0x64 4 3>;
> +						clk-gate = <0x60 2>;
>  					};
>  
> -				l4_sp_clk: l4_sp_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&mainclk>, <&per_base_clk>;
> -					div-reg = <0x64 7 3>;
> -					clk-gate = <0x60 3>;
> +					l4_sp_clk: l4_sp_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&mainclk>, <&per_base_clk>;
> +						div-reg = <0x64 7 3>;
> +						clk-gate = <0x60 3>;
>  					};
>  
> -				dbg_at_clk: dbg_at_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&dbg_base_clk>;
> -					div-reg = <0x68 0 2>;
> -					clk-gate = <0x60 4>;
> +					dbg_at_clk: dbg_at_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&dbg_base_clk>;
> +						div-reg = <0x68 0 2>;
> +						clk-gate = <0x60 4>;
>  					};
>  
> -				dbg_clk: dbg_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&dbg_base_clk>;
> -					div-reg = <0x68 2 2>;
> -					clk-gate = <0x60 5>;
> +					dbg_clk: dbg_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&dbg_base_clk>;
> +						div-reg = <0x68 2 2>;
> +						clk-gate = <0x60 5>;
>  					};
>  
> -				dbg_trace_clk: dbg_trace_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&dbg_base_clk>;
> -					div-reg = <0x6C 0 3>;
> -					clk-gate = <0x60 6>;
> +					dbg_trace_clk: dbg_trace_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&dbg_base_clk>;
> +						div-reg = <0x6C 0 3>;
> +						clk-gate = <0x60 6>;
>  					};
>  
> -				dbg_timer_clk: dbg_timer_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&dbg_base_clk>;
> -					clk-gate = <0x60 7>;
> +					dbg_timer_clk: dbg_timer_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&dbg_base_clk>;
> +						clk-gate = <0x60 7>;
>  					};
>  
> -				cfg_clk: cfg_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&cfg_s2f_usr0_clk>;
> -					clk-gate = <0x60 8>;
> +					cfg_clk: cfg_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&cfg_s2f_usr0_clk>;
> +						clk-gate = <0x60 8>;
>  					};
>  
> -				s2f_user0_clk: s2f_user0_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&cfg_s2f_usr0_clk>;
> -					clk-gate = <0x60 9>;
> +					s2f_user0_clk: s2f_user0_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&cfg_s2f_usr0_clk>;
> +						clk-gate = <0x60 9>;
>  					};
>  
> -				emac_0_clk: emac_0_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&emac0_clk>;
> -					clk-gate = <0xa0 0>;
> +					emac_0_clk: emac_0_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&emac0_clk>;
> +						clk-gate = <0xa0 0>;
>  					};
>  
> -				emac_1_clk: emac_1_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&emac1_clk>;
> -					clk-gate = <0xa0 1>;
> +					emac_1_clk: emac_1_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&emac1_clk>;
> +						clk-gate = <0xa0 1>;
>  					};
>  
> -				usb_mp_clk: usb_mp_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&per_base_clk>;
> -					clk-gate = <0xa0 2>;
> -					div-reg = <0xa4 0 3>;
> +					usb_mp_clk: usb_mp_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&per_base_clk>;
> +						clk-gate = <0xa0 2>;
> +						div-reg = <0xa4 0 3>;
>  					};
>  
> -				spi_m_clk: spi_m_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&per_base_clk>;
> -					clk-gate = <0xa0 3>;
> -					div-reg = <0xa4 3 3>;
> +					spi_m_clk: spi_m_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&per_base_clk>;
> +						clk-gate = <0xa0 3>;
> +						div-reg = <0xa4 3 3>;
>  					};
>  
> -				can0_clk: can0_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&per_base_clk>;
> -					clk-gate = <0xa0 4>;
> -					div-reg = <0xa4 6 3>;
> +					can0_clk: can0_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&per_base_clk>;
> +						clk-gate = <0xa0 4>;
> +						div-reg = <0xa4 6 3>;
>  					};
>  
> -				can1_clk: can1_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&per_base_clk>;
> -					clk-gate = <0xa0 5>;
> -					div-reg = <0xa4 9 3>;
> +					can1_clk: can1_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&per_base_clk>;
> +						clk-gate = <0xa0 5>;
> +						div-reg = <0xa4 9 3>;
>  					};
>  
> -				gpio_db_clk: gpio_db_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&per_base_clk>;
> -					clk-gate = <0xa0 6>;
> -					div-reg = <0xa8 0 24>;
> +					gpio_db_clk: gpio_db_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&per_base_clk>;
> +						clk-gate = <0xa0 6>;
> +						div-reg = <0xa8 0 24>;
>  					};
>  
> -				s2f_user1_clk: s2f_user1_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&s2f_usr1_clk>;
> -					clk-gate = <0xa0 7>;
> +					s2f_user1_clk: s2f_user1_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&s2f_usr1_clk>;
> +						clk-gate = <0xa0 7>;
>  					};
>  
> -				sdmmc_clk: sdmmc_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
> -					clk-gate = <0xa0 8>;
> +					sdmmc_clk: sdmmc_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
> +						clk-gate = <0xa0 8>;
>  					};
>  
> -				nand_x_clk: nand_x_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
> -					clk-gate = <0xa0 9>;
> +					nand_x_clk: nand_x_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
> +						clk-gate = <0xa0 9>;
>  					};
>  
> -				nand_clk: nand_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
> -					clk-gate = <0xa0 10>;
> -					fixed-divider = <4>;
> +					nand_clk: nand_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
> +						clk-gate = <0xa0 10>;
> +						fixed-divider = <4>;
>  					};
>  
> -				qspi_clk: qspi_clk {
> -					#clock-cells = <0>;
> -					compatible = "altr,socfpga-gate-clk";
> -					clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
> -					clk-gate = <0xa0 11>;
> +					qspi_clk: qspi_clk {
> +						#clock-cells = <0>;
> +						compatible = "altr,socfpga-gate-clk";
> +						clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
> +						clk-gate = <0xa0 11>;
>  					};
>  				};
>  			};
> @@ -516,9 +516,9 @@
>  		};
>  
>  		rstmgr@ffd05000 {
> -				compatible = "altr,rst-mgr";
> -				reg = <0xffd05000 0x1000>;
> -			};
> +			compatible = "altr,rst-mgr";
> +			reg = <0xffd05000 0x1000>;
> +		};
>  
>  		sysmgr@ffd08000 {
>  				compatible = "altr,sys-mgr";

Acked-by: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>



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[PATCH 4/4] ARM: socfpga: dts: fix s2f_* clock name

[Steffen Trumtrar]

The s2f_* clocks are called h2f_* in the datasheets.
Rename them accordingly in the socfpga.dtsi.

Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
 arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 587096e..e245924 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -147,7 +147,7 @@
 							reg = <0x58>;
 						};
 
-						cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
+						cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
 							#clock-cells = <0>;
 							compatible = "altr,socfpga-perip-clk";
 							clocks = <&main_pll>;
@@ -198,7 +198,7 @@
 							reg = <0x98>;
 						};
 
-						s2f_usr1_clk: s2f_usr1_clk {
+						h2f_usr1_clk: h2f_usr1_clk {
 							#clock-cells = <0>;
 							compatible = "altr,socfpga-perip-clk";
 							clocks = <&periph_pll>;
@@ -235,7 +235,7 @@
 							reg = <0xD0>;
 						};
 
-						s2f_usr2_clk: s2f_usr2_clk {
+						h2f_usr2_clk: h2f_usr2_clk {
 							#clock-cells = <0>;
 							compatible = "altr,socfpga-perip-clk";
 							clocks = <&sdram_pll>;
@@ -335,14 +335,14 @@
 					cfg_clk: cfg_clk {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-gate-clk";
-						clocks = <&cfg_s2f_usr0_clk>;
+						clocks = <&cfg_h2f_usr0_clk>;
 						clk-gate = <0x60 8>;
 					};
 
-					s2f_user0_clk: s2f_user0_clk {
+					h2f_user0_clk: h2f_user0_clk {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-gate-clk";
-						clocks = <&cfg_s2f_usr0_clk>;
+						clocks = <&cfg_h2f_usr0_clk>;
 						clk-gate = <0x60 9>;
 					};
 
@@ -400,10 +400,10 @@
 						div-reg = <0xa8 0 24>;
 					};
 
-					s2f_user1_clk: s2f_user1_clk {
+					h2f_user1_clk: h2f_user1_clk {
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-gate-clk";
-						clocks = <&s2f_usr1_clk>;
+						clocks = <&h2f_usr1_clk>;
 						clk-gate = <0xa0 7>;
 					};
 
-- 
1.8.4.rc3

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Re: [PATCH 4/4] ARM: socfpga: dts: fix s2f_* clock name

[Dinh Nguyen]

On Wed, 2013-10-02 at 09:35 +0200, Steffen Trumtrar wrote:
> The s2f_* clocks are called h2f_* in the datasheets.
> Rename them accordingly in the socfpga.dtsi.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
>  arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 587096e..e245924 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -147,7 +147,7 @@
>  							reg = <0x58>;
>  						};
>  
> -						cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
> +						cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
>  							#clock-cells = <0>;
>  							compatible = "altr,socfpga-perip-clk";
>  							clocks = <&main_pll>;
> @@ -198,7 +198,7 @@
>  							reg = <0x98>;
>  						};
>  
> -						s2f_usr1_clk: s2f_usr1_clk {
> +						h2f_usr1_clk: h2f_usr1_clk {
>  							#clock-cells = <0>;
>  							compatible = "altr,socfpga-perip-clk";
>  							clocks = <&periph_pll>;
> @@ -235,7 +235,7 @@
>  							reg = <0xD0>;
>  						};
>  
> -						s2f_usr2_clk: s2f_usr2_clk {
> +						h2f_usr2_clk: h2f_usr2_clk {
>  							#clock-cells = <0>;
>  							compatible = "altr,socfpga-perip-clk";
>  							clocks = <&sdram_pll>;
> @@ -335,14 +335,14 @@
>  					cfg_clk: cfg_clk {
>  						#clock-cells = <0>;
>  						compatible = "altr,socfpga-gate-clk";
> -						clocks = <&cfg_s2f_usr0_clk>;
> +						clocks = <&cfg_h2f_usr0_clk>;
>  						clk-gate = <0x60 8>;
>  					};
>  
> -					s2f_user0_clk: s2f_user0_clk {
> +					h2f_user0_clk: h2f_user0_clk {
>  						#clock-cells = <0>;
>  						compatible = "altr,socfpga-gate-clk";
> -						clocks = <&cfg_s2f_usr0_clk>;
> +						clocks = <&cfg_h2f_usr0_clk>;
>  						clk-gate = <0x60 9>;
>  					};
>  
> @@ -400,10 +400,10 @@
>  						div-reg = <0xa8 0 24>;
>  					};
>  
> -					s2f_user1_clk: s2f_user1_clk {
> +					h2f_user1_clk: h2f_user1_clk {
>  						#clock-cells = <0>;
>  						compatible = "altr,socfpga-gate-clk";
> -						clocks = <&s2f_usr1_clk>;
> +						clocks = <&h2f_usr1_clk>;
>  						clk-gate = <0xa0 7>;
>  					};
>  

Acked-by: Dinh Nguyen <dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>



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Re: [PATCH 0/4] SoCFPGA: dts cleanups and SoCkit support

[Dinh Nguyen]

On Wed, 2013-10-02 at 09:35 +0200, Steffen Trumtrar wrote:
> Hi!
> 
> This series includes some minor cleanups (indentation and clock labels) and
> reorders the socfpga dts hierarchy from
> 	socfpga.dtsi
> 	-> socfpga_$board.dts
> 	-> socfpga_$otherboard.dts
> to
> 	socfpga.dtsi
> 	-> socfpga_cyclone5.dtsi
> 	--> socfpga_cyclone5_$board.dts
> 	--> socfpga_cyclone5_$otherboard.dts
> 
> The Socfpga is a SoC with an FPGA on board. This FPGA does not have to be a
> Cyclone5.
> The current socfpga_cyclone5.dts is however not specific to a SoC with this
> combination, but describes one specific board: the Altera Cyclone5 Development Kit.
> Therefore, I propose moving the common stuff to socfpga_cyclone5.dtsi as long as
> it is as easy as now.
> 
> Finally, the series adds minimal support for the terasic SoCkit.
> 
> BTW: It seems there is no official maintainer(tree) for the socfpga dt stuff.
> So, I rebased onto next-20130927.

I've pretty much Acked this whole series, with the minor comment of a
baudrate change.

I think Rob had mentioned in a another patch(that since the patch
doesn't involve a binding change, it may not get too many comments), and
since this patch series is not making a binding change at all, comments
may not come, but we still need an Ack from a DTS binding maintainer
before the arm-soc maintainer(s) will take it.

Thanks,
Dinh
> Regards,
> Steffen
> 
> 
> Steffen Trumtrar (4):
>   ARM: socfpga: dts: Move common nodes to cyclone5 dtsi
>   ARM: socfpga: dts: Add support for terasic SoCkit
>   ARM: socfpga: dts: cleanup indentation
>   ARM: socfpga: dts: fix s2f_* clock name
> 
>  arch/arm/boot/dts/Makefile                         |   3 +-
>  arch/arm/boot/dts/socfpga.dtsi                     | 296 ++++++++++-----------
>  ...{socfpga_cyclone5.dts => socfpga_cyclone5.dtsi} |  20 --
>  arch/arm/boot/dts/socfpga_cyclone5_socdk.dts       |  40 +++
>  arch/arm/boot/dts/socfpga_cyclone5_sockit.dts      |  37 +++
>  5 files changed, 227 insertions(+), 169 deletions(-)
>  rename arch/arm/boot/dts/{socfpga_cyclone5.dts => socfpga_cyclone5.dtsi} (78%)
>  create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
>  create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
> 



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Re: [PATCH 0/4] SoCFPGA: dts cleanups and SoCkit support

[Steffen Trumtrar]

On Thu, Oct 03, 2013 at 10:12:01AM -0500, Dinh Nguyen wrote:
> On Wed, 2013-10-02 at 09:35 +0200, Steffen Trumtrar wrote:
> > Hi!
> > 
> > This series includes some minor cleanups (indentation and clock labels) and
> > reorders the socfpga dts hierarchy from
> > 	socfpga.dtsi
> > 	-> socfpga_$board.dts
> > 	-> socfpga_$otherboard.dts
> > to
> > 	socfpga.dtsi
> > 	-> socfpga_cyclone5.dtsi
> > 	--> socfpga_cyclone5_$board.dts
> > 	--> socfpga_cyclone5_$otherboard.dts
> > 
> > The Socfpga is a SoC with an FPGA on board. This FPGA does not have to be a
> > Cyclone5.
> > The current socfpga_cyclone5.dts is however not specific to a SoC with this
> > combination, but describes one specific board: the Altera Cyclone5 Development Kit.
> > Therefore, I propose moving the common stuff to socfpga_cyclone5.dtsi as long as
> > it is as easy as now.
> > 
> > Finally, the series adds minimal support for the terasic SoCkit.
> > 
> > BTW: It seems there is no official maintainer(tree) for the socfpga dt stuff.
> > So, I rebased onto next-20130927.
> 
> I've pretty much Acked this whole series, with the minor comment of a
> baudrate change.
> 

Thank you!

> I think Rob had mentioned in a another patch(that since the patch
> doesn't involve a binding change, it may not get too many comments), and
> since this patch series is not making a binding change at all, comments
> may not come, but we still need an Ack from a DTS binding maintainer
> before the arm-soc maintainer(s) will take it.
> 

Hm, I don't think we need that here, as this is really just reordering
and doesn't change any API or binding at all. We need someone responsible
for arch/arm/boot/dts to take it (as there is no maintainer for socfpga*.dts(i),
yet). The arm-soc maintainers than get it from the dts maintainer.
I guess with your ACK there shouldn't be any more problems. But, we'll see.

Thanks,
Steffen

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