[PATCH 0/6] Krait L1/L2 EDAC driver

[PATCH 0/6] Krait L1/L2 EDAC driver

[Stephen Boyd]

This patchset adds support for the Krait L1/L2 cache error detection
hardware. The first patch fixes a generic framework bug. The next
two patches lay the groundwork for this driver to be added by 
exporting percpu irq functions as well as adding the Krait l2 indirection
register code. The next two patches add the driver and the binding and 
the final patch hooks it all up by adding the device tree node.

I'm not sure which tree this is supposed to go through. Ideally we could
send the first 3 plus the 5th one through an edac tree. The final dts changes
could go through arm-soc via davidb's tree and the Documentation patch could
go through the devicetree tree.

Stephen Boyd (6):
  edac: Don't try to cancel workqueue when it's never setup
  genirq: export percpu irq functions for module usage
  ARM: Add Krait L2 accessor functions
  edac: Document Krait L1/L2 EDAC driver binding
  edac: Add support for Krait CPU cache error detection
  ARM: dts: msm: Add Krait edac node

 .../bindings/arm/qcom,krait-cache-erp.txt          |  16 +
 arch/arm/boot/dts/qcom-msm8974.dtsi                |   5 +
 arch/arm/common/Kconfig                            |   3 +
 arch/arm/common/Makefile                           |   1 +
 arch/arm/common/krait-l2-accessors.c               |  52 ++++
 arch/arm/include/asm/krait-l2-accessors.h          |  20 ++
 drivers/edac/Kconfig                               |   8 +
 drivers/edac/Makefile                              |   2 +
 drivers/edac/edac_device.c                         |   3 +
 drivers/edac/krait_edac.c                          | 335 +++++++++++++++++++++
 kernel/irq/manage.c                                |   2 +
 11 files changed, 447 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
 create mode 100644 arch/arm/common/krait-l2-accessors.c
 create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
 create mode 100644 drivers/edac/krait_edac.c

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[PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Stephen Boyd]

The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 .../devicetree/bindings/arm/qcom,krait-cache-erp.txt     | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt

diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
new file mode 100644
index 0000000..01fe8a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
@@ -0,0 +1,16 @@
+* Qualcomm Krait L1 / L2 cache error reporting
+
+Required properties:
+- compatible: Should be "qcom,krait-cache-erp"
+- interrupts: Should contain the L1/CPU error interrupt number and
+  then the L2 cache error interrupt number
+
+Optional properties:
+- interrupt-names: Should contain the interrupt names "l1_irq" and
+  "l2_irq"
+
+Example:
+	edac {
+		compatible = "qcom,krait-cache-erp";
+		interrupts = <1 9 0xf04>, <0 2 0x4>;
+	};
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Re: [PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Mark Rutland]

On Tue, Oct 29, 2013 at 12:31:28AM +0000, Stephen Boyd wrote:
> The Krait L1/L2 error reporting device is made up of two
> interrupts, one per-CPU interrupt for the L1 caches and one
> interrupt for the L2 cache.
> 
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  .../devicetree/bindings/arm/qcom,krait-cache-erp.txt     | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> new file mode 100644
> index 0000000..01fe8a8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> @@ -0,0 +1,16 @@
> +* Qualcomm Krait L1 / L2 cache error reporting
> +
> +Required properties:
> +- compatible: Should be "qcom,krait-cache-erp"
> +- interrupts: Should contain the L1/CPU error interrupt number and
> +  then the L2 cache error interrupt number
> +
> +Optional properties:
> +- interrupt-names: Should contain the interrupt names "l1_irq" and
> +  "l2_irq"

As with my comment on the parsing code, I'd prefer that if interrupt-names was
present it defined the order of interrupts. Otherwise it's redundant and of no
value.

Otherwise, the binding looks fine to me:

Acked-by: Mark Rutland <mark.rutland@arm.com>

> +
> +Example:
> +	edac {
> +		compatible = "qcom,krait-cache-erp";
> +		interrupts = <1 9 0xf04>, <0 2 0x4>;
> +	};
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> hosted by The Linux Foundation
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Re: [PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Stephen Boyd]

On 10/28, Mark Rutland wrote:
> On Tue, Oct 29, 2013 at 12:31:28AM +0000, Stephen Boyd wrote:
> > +
> > +Optional properties:
> > +- interrupt-names: Should contain the interrupt names "l1_irq" and
> > +  "l2_irq"
> 
> As with my comment on the parsing code, I'd prefer that if interrupt-names was
> present it defined the order of interrupts. Otherwise it's redundant and of no
> value.
> 
> Otherwise, the binding looks fine to me:
> 
> Acked-by: Mark Rutland <mark.rutland@arm.com>

How about I just drop the interrupt-names property? It isn't
adding much and is a holdover from the vendor kernel.

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Re: [PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Mark Rutland]

On Tue, Oct 29, 2013 at 05:06:45AM +0000, Stephen Boyd wrote:
> On 10/28, Mark Rutland wrote:
> > On Tue, Oct 29, 2013 at 12:31:28AM +0000, Stephen Boyd wrote:
> > > +
> > > +Optional properties:
> > > +- interrupt-names: Should contain the interrupt names "l1_irq" and
> > > +  "l2_irq"
> > 
> > As with my comment on the parsing code, I'd prefer that if interrupt-names was
> > present it defined the order of interrupts. Otherwise it's redundant and of no
> > value.
> > 
> > Otherwise, the binding looks fine to me:
> > 
> > Acked-by: Mark Rutland <mark.rutland@arm.com>
> 
> How about I just drop the interrupt-names property? It isn't
> adding much and is a holdover from the vendor kernel.

That's also fine given that this is a very specific binding.

Mark.

Re: [PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Kumar Gala]

On Oct 28, 2013, at 7:31 PM, Stephen Boyd wrote:

> The Krait L1/L2 error reporting device is made up of two
> interrupts, one per-CPU interrupt for the L1 caches and one
> interrupt for the L2 cache.
> 
> Cc: <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
> .../devicetree/bindings/arm/qcom,krait-cache-erp.txt     | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> new file mode 100644
> index 0000000..01fe8a8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> @@ -0,0 +1,16 @@
> +* Qualcomm Krait L1 / L2 cache error reporting
> +
> +Required properties:
> +- compatible: Should be "qcom,krait-cache-erp"
> +- interrupts: Should contain the L1/CPU error interrupt number and
> +  then the L2 cache error interrupt number
> +
> +Optional properties:
> +- interrupt-names: Should contain the interrupt names "l1_irq" and
> +  "l2_irq"
> +
> +Example:
> +	edac {
> +		compatible = "qcom,krait-cache-erp";
> +		interrupts = <1 9 0xf04>, <0 2 0x4>;
> +	};

Why wouldn't we have these as part of cache nodes in the dts?  (which begs the question why we don't have cache nodes?)

- k

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Re: [PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Stephen Boyd]

On 10/29/13 01:21, Kumar Gala wrote:
> On Oct 28, 2013, at 7:31 PM, Stephen Boyd wrote:
>
>> The Krait L1/L2 error reporting device is made up of two
>> interrupts, one per-CPU interrupt for the L1 caches and one
>> interrupt for the L2 cache.
>>
>> Cc: <devicetree@vger.kernel.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>> .../devicetree/bindings/arm/qcom,krait-cache-erp.txt     | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
>> new file mode 100644
>> index 0000000..01fe8a8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
>> @@ -0,0 +1,16 @@
>> +* Qualcomm Krait L1 / L2 cache error reporting
>> +
>> +Required properties:
>> +- compatible: Should be "qcom,krait-cache-erp"
>> +- interrupts: Should contain the L1/CPU error interrupt number and
>> +  then the L2 cache error interrupt number
>> +
>> +Optional properties:
>> +- interrupt-names: Should contain the interrupt names "l1_irq" and
>> +  "l2_irq"
>> +
>> +Example:
>> +	edac {
>> +		compatible = "qcom,krait-cache-erp";
>> +		interrupts = <1 9 0xf04>, <0 2 0x4>;
>> +	};
> Why wouldn't we have these as part of cache nodes in the dts?  (which begs the question why we don't have cache nodes?)
>

I can certainly add cache nodes and cpu nodes and then put the
interrupts in those nodes. I was thinking along those same lines when I
ported this driver but figured it would be good to get something out
there. The only question I have is how am I supposed to hook that up
into the linux device model? Will the edac driver bind to the device
created for the cpus node and the cache node? I guess it will have to be
a driver that binds to two devices.

One could argue that we should put the cp15 based architected timers in
the cpus node also but so far nobody has done that and I think there was
some reasoning behind that, Mark?

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Re: [PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Olof Johansson]

On Tue, Oct 29, 2013 at 11:00 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 10/29/13 01:21, Kumar Gala wrote:
>> On Oct 28, 2013, at 7:31 PM, Stephen Boyd wrote:
>>
>>> The Krait L1/L2 error reporting device is made up of two
>>> interrupts, one per-CPU interrupt for the L1 caches and one
>>> interrupt for the L2 cache.
>>>
>>> Cc: <devicetree@vger.kernel.org>
>>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>>> ---
>>> .../devicetree/bindings/arm/qcom,krait-cache-erp.txt     | 16 ++++++++++++++++
>>> 1 file changed, 16 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
>>> new file mode 100644
>>> index 0000000..01fe8a8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
>>> @@ -0,0 +1,16 @@
>>> +* Qualcomm Krait L1 / L2 cache error reporting
>>> +
>>> +Required properties:
>>> +- compatible: Should be "qcom,krait-cache-erp"
>>> +- interrupts: Should contain the L1/CPU error interrupt number and
>>> +  then the L2 cache error interrupt number
>>> +
>>> +Optional properties:
>>> +- interrupt-names: Should contain the interrupt names "l1_irq" and
>>> +  "l2_irq"
>>> +
>>> +Example:
>>> +    edac {
>>> +            compatible = "qcom,krait-cache-erp";
>>> +            interrupts = <1 9 0xf04>, <0 2 0x4>;
>>> +    };
>> Why wouldn't we have these as part of cache nodes in the dts?  (which begs the question why we don't have cache nodes?)

In particular, naming the node edac seems like a suboptimal choice,
since that's a very linux-specific name for the error reporting
framework.

> I can certainly add cache nodes and cpu nodes and then put the
> interrupts in those nodes. I was thinking along those same lines when I
> ported this driver but figured it would be good to get something out
> there. The only question I have is how am I supposed to hook that up
> into the linux device model? Will the edac driver bind to the device
> created for the cpus node and the cache node? I guess it will have to be
> a driver that binds to two devices.

Or it could bind to one device and look up the info for the other from
the devicetree without relying on the driver core to instantiate
devices.


-Olof

Re: [PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Stephen Boyd]

On 10/29, Stephen Boyd wrote:
> On 10/29/13 01:21, Kumar Gala wrote:
> > On Oct 28, 2013, at 7:31 PM, Stephen Boyd wrote:
> >
> >> The Krait L1/L2 error reporting device is made up of two
> >> interrupts, one per-CPU interrupt for the L1 caches and one
> >> interrupt for the L2 cache.
> >>
> >> Cc: <devicetree@vger.kernel.org>
> >> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> >> ---
> >> .../devicetree/bindings/arm/qcom,krait-cache-erp.txt     | 16 ++++++++++++++++
> >> 1 file changed, 16 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> >> new file mode 100644
> >> index 0000000..01fe8a8
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> >> @@ -0,0 +1,16 @@
> >> +* Qualcomm Krait L1 / L2 cache error reporting
> >> +
> >> +Required properties:
> >> +- compatible: Should be "qcom,krait-cache-erp"
> >> +- interrupts: Should contain the L1/CPU error interrupt number and
> >> +  then the L2 cache error interrupt number
> >> +
> >> +Optional properties:
> >> +- interrupt-names: Should contain the interrupt names "l1_irq" and
> >> +  "l2_irq"
> >> +
> >> +Example:
> >> +	edac {
> >> +		compatible = "qcom,krait-cache-erp";
> >> +		interrupts = <1 9 0xf04>, <0 2 0x4>;
> >> +	};
> > Why wouldn't we have these as part of cache nodes in the dts?  (which begs the question why we don't have cache nodes?)
> >
> 
> I can certainly add cache nodes and cpu nodes and then put the
> interrupts in those nodes. I was thinking along those same lines when I
> ported this driver but figured it would be good to get something out
> there. The only question I have is how am I supposed to hook that up
> into the linux device model? Will the edac driver bind to the device
> created for the cpus node and the cache node? I guess it will have to be
> a driver that binds to two devices.
> 
> One could argue that we should put the cp15 based architected timers in
> the cpus node also but so far nobody has done that and I think there was
> some reasoning behind that, Mark?
> 

Ok I've come up with this:

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "qcom,krait";
		interrupts = <1 9 0xf04>;

		cpu@0 {
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			reg = <1>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			reg = <2>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			reg = <3>;
			next-level-cache = <&L2>;
		};

		L2: l2-cache {
			compatible = "qcom,krait-l2", "cache";
			cache-level = <2>;
			interrupts = <0 2 0x4>;
		};
	};

But now I don't know where to document this. Should I make a
krait-edac.txt file and document it there? The problem is now
we're documenting more than the error interrupts.

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Re: [PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Mark Rutland]

On Tue, Oct 29, 2013 at 06:00:59PM +0000, Stephen Boyd wrote:
> On 10/29/13 01:21, Kumar Gala wrote:
> > On Oct 28, 2013, at 7:31 PM, Stephen Boyd wrote:
> >
> >> The Krait L1/L2 error reporting device is made up of two
> >> interrupts, one per-CPU interrupt for the L1 caches and one
> >> interrupt for the L2 cache.
> >>
> >> Cc: <devicetree@vger.kernel.org>
> >> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> >> ---
> >> .../devicetree/bindings/arm/qcom,krait-cache-erp.txt     | 16 ++++++++++++++++
> >> 1 file changed, 16 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> >> new file mode 100644
> >> index 0000000..01fe8a8
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
> >> @@ -0,0 +1,16 @@
> >> +* Qualcomm Krait L1 / L2 cache error reporting
> >> +
> >> +Required properties:
> >> +- compatible: Should be "qcom,krait-cache-erp"
> >> +- interrupts: Should contain the L1/CPU error interrupt number and
> >> +  then the L2 cache error interrupt number
> >> +
> >> +Optional properties:
> >> +- interrupt-names: Should contain the interrupt names "l1_irq" and
> >> +  "l2_irq"
> >> +
> >> +Example:
> >> +	edac {
> >> +		compatible = "qcom,krait-cache-erp";
> >> +		interrupts = <1 9 0xf04>, <0 2 0x4>;
> >> +	};
> > Why wouldn't we have these as part of cache nodes in the dts?  (which begs the question why we don't have cache nodes?)
> >
> 
> I can certainly add cache nodes and cpu nodes and then put the
> interrupts in those nodes. I was thinking along those same lines when I
> ported this driver but figured it would be good to get something out
> there. The only question I have is how am I supposed to hook that up
> into the linux device model? Will the edac driver bind to the device
> created for the cpus node and the cache node? I guess it will have to be
> a driver that binds to two devices.
> 
> One could argue that we should put the cp15 based architected timers in
> the cpus node also but so far nobody has done that and I think there was
> some reasoning behind that, Mark?

The architected timer binding was created at a time I wasn't involved in kernel
development, and I'm not aware of any particular reasoning. I've heard that
there was a decision to not duplicate banked resources, which would explain not
having the timer under /cpus/cpu@N, but doesn't imply that having it under
/cpus is bad.

Do we have precedent for putting any devices other than CPUs in /cpus?

Thanks,
Mark.

Re: [PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

[Kumar Gala]

On Oct 29, 2013, at 7:38 PM, Mark Rutland wrote:

> On Tue, Oct 29, 2013 at 06:00:59PM +0000, Stephen Boyd wrote:
>> On 10/29/13 01:21, Kumar Gala wrote:
>>> On Oct 28, 2013, at 7:31 PM, Stephen Boyd wrote:
>>> 
>>>> The Krait L1/L2 error reporting device is made up of two
>>>> interrupts, one per-CPU interrupt for the L1 caches and one
>>>> interrupt for the L2 cache.
>>>> 
>>>> Cc: <devicetree@vger.kernel.org>
>>>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>>>> ---
>>>> .../devicetree/bindings/arm/qcom,krait-cache-erp.txt     | 16 ++++++++++++++++
>>>> 1 file changed, 16 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
>>>> 
>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
>>>> new file mode 100644
>>>> index 0000000..01fe8a8
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
>>>> @@ -0,0 +1,16 @@
>>>> +* Qualcomm Krait L1 / L2 cache error reporting
>>>> +
>>>> +Required properties:
>>>> +- compatible: Should be "qcom,krait-cache-erp"
>>>> +- interrupts: Should contain the L1/CPU error interrupt number and
>>>> +  then the L2 cache error interrupt number
>>>> +
>>>> +Optional properties:
>>>> +- interrupt-names: Should contain the interrupt names "l1_irq" and
>>>> +  "l2_irq"
>>>> +
>>>> +Example:
>>>> +	edac {
>>>> +		compatible = "qcom,krait-cache-erp";
>>>> +		interrupts = <1 9 0xf04>, <0 2 0x4>;
>>>> +	};
>>> Why wouldn't we have these as part of cache nodes in the dts?  (which begs the question why we don't have cache nodes?)
>>> 
>> 
>> I can certainly add cache nodes and cpu nodes and then put the
>> interrupts in those nodes. I was thinking along those same lines when I
>> ported this driver but figured it would be good to get something out
>> there. The only question I have is how am I supposed to hook that up
>> into the linux device model? Will the edac driver bind to the device
>> created for the cpus node and the cache node? I guess it will have to be
>> a driver that binds to two devices.
>> 
>> One could argue that we should put the cp15 based architected timers in
>> the cpus node also but so far nobody has done that and I think there was
>> some reasoning behind that, Mark?
> 
> The architected timer binding was created at a time I wasn't involved in kernel
> development, and I'm not aware of any particular reasoning. I've heard that
> there was a decision to not duplicate banked resources, which would explain not
> having the timer under /cpus/cpu@N, but doesn't imply that having it under
> /cpus is bad.
> 
> Do we have precedent for putting any devices other than CPUs in /cpus?

On PPC we had core cache's (depending on topology) that would be there, and thus why I raised the suggestion.

- k

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