From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: [PATCH v3 4/6] edac: Document Krait L1/L2 EDAC driver binding Date: Fri, 1 Nov 2013 09:31:54 -0700 Message-ID: <1383323516-31357-5-git-send-email-sboyd@codeaurora.org> References: <1383323516-31357-1-git-send-email-sboyd@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1383323516-31357-1-git-send-email-sboyd@codeaurora.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: linux-edac@vger.kernel.org Cc: Mark Rutland , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org The Krait L1/L2 error reporting device is made up of two interrupts, one per-CPU interrupt for the L1 caches and one interrupt for the L2 cache. Cc: Mark Rutland Acked-by: Kumar Gala Cc: Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/arm/cpus.txt | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index f32494d..c30d547 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -44,6 +44,8 @@ For the ARM architecture every CPU node must contain the following properties: "marvell,mohawk" "marvell,xsc3" "marvell,xscale" + "qcom,scorpion" + "qcom,krait" Example: @@ -75,3 +77,50 @@ Example: reg = <0x101>; }; }; + +If the compatible string contains "qcom,krait" there shall be an interrupts +property containing the L1/CPU error interrupt number. There shall also be a +l2-cache node containing the following properties: + + - compatible: Shall contain at least "cache" + - cache-level: Must be 2 + - interrupts: Shall contain the L2 error interrupt + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 9 0xf04>; + compatible = "qcom,krait"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + }; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation