[PATCH 1/8] irqchip: add DesignWare APB ICTL interrupt controller

[PATCH 1/8] irqchip: add DesignWare APB ICTL interrupt controller

[Sebastian Hesselbarth]

This adds an irqchip driver and corresponding devicetree binding for the
secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
RFCv1->RFCv2:
- added copyright reference

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../interrupt-controller/snps,dw-apb-ictl.txt      |   29 ++++
 drivers/irqchip/Kconfig                            |    4 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-dw-apb-ictl.c                  |  142 ++++++++++++++++++++
 4 files changed, 176 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
 create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c

diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
new file mode 100644
index 0000000..7ccd1ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
@@ -0,0 +1,29 @@
+Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
+
+Synopsys DesignWare provides interrupt controller IP for APB known as
+dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
+APB bus, e.g. Marvell Armada 1500.
+
+Required properties:
+- compatible: shall be "snps,dw-apb-ictl"
+- reg: base address of interrupt registers starting with ENABLE_LOW register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
+- interrupts: interrupt reference to primary interrupt controller
+- interrupt-parent: (optional) reference specific primary interrupt controller
+
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of low interrupts,
+- 1 maps to bit 1 of low interrupts,
+- 32 maps to bit 0 of high interrupts, and so on.
+
+Example:
+	aic: interrupt-controller@3000 {
+		compatible = "snps,dw-apb-ictl";
+		reg = <0x3000 0xc00>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+	};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3792a1a..940638d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -30,6 +30,10 @@ config ARM_VIC_NR
 	  The maximum number of VICs available in the system, for
 	  power management.
 
+config DW_APB_ICTL
+	bool
+	select IRQ_DOMAIN
+
 config IMGPDC_IRQ
 	bool
 	select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c60b901..6427323 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o
 obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o
+obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)			+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
 obj-$(CONFIG_ARCH_MOXART)		+= irq-moxart.o
diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
new file mode 100644
index 0000000..bbcacee
--- /dev/null
+++ b/drivers/irqchip/irq-dw-apb-ictl.c
@@ -0,0 +1,142 @@
+/*
+ * Synopsys DW APB ICTL irqchip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "irqchip.h"
+
+#define APB_INT_ENABLE_L	0x00
+#define APB_INT_ENABLE_H	0x04
+#define APB_INT_MASK_L		0x08
+#define APB_INT_MASK_H		0x0c
+#define APB_INT_FINALSTATUS_L	0x30
+#define APB_INT_FINALSTATUS_H	0x34
+
+static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	struct irq_chip_generic *gc = irq_get_handler_data(irq);
+	struct irq_domain *d = gc->private;
+	u32 stat;
+	int n;
+
+	chained_irq_enter(chip, desc);
+
+	for (n = 0; n < gc->num_ct; n++) {
+		stat = readl_relaxed(gc->reg_base +
+				     APB_INT_FINALSTATUS_L + 4 * n);
+		while (stat) {
+			u32 hwirq = ffs(stat) - 1;
+			generic_handle_irq(irq_find_mapping(d,
+					    gc->irq_base + hwirq + 32 * n));
+			stat &= ~(1 << hwirq);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static int __init dw_apb_ictl_init(struct device_node *np,
+				   struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	struct resource r;
+	struct irq_domain *domain;
+	struct irq_chip_generic *gc;
+	void __iomem *iobase;
+	int ret, nrirqs, irq;
+	u32 reg;
+
+	/* Map the parent interrupt for the chained handler */
+	irq = irq_of_parse_and_map(np, 0);
+	if (irq <= 0) {
+		pr_err("%s: unable to parse irq\n", np->name);
+		return -EINVAL;
+	}
+
+	ret = of_address_to_resource(np, 0, &r);
+	if (ret) {
+		pr_err("%s: unable to get resource\n", np->name);
+		return ret;
+	}
+
+	if (!request_mem_region(r.start, resource_size(&r), np->name)) {
+		pr_err("%s: unable to request mem region\n", np->name);
+		return -ENOMEM;
+	}
+
+	iobase = ioremap(r.start, resource_size(&r));
+	if (!iobase) {
+		pr_err("%s: unable to map resource\n", np->name);
+		return -ENOMEM;
+	}
+
+	/*
+	 * DW IP can be configured to allow 2-64 irqs. We can determine
+	 * the number of irqs supported by writing into enable register
+	 * and look for bits not set, as corresponding flip-flops will
+	 * have been removed by sythesis tool.
+	 */
+
+	/* mask and enable all interrupts */
+	writel(~0, iobase + APB_INT_MASK_L);
+	writel(~0, iobase + APB_INT_MASK_H);
+	writel(~0, iobase + APB_INT_ENABLE_L);
+	writel(~0, iobase + APB_INT_ENABLE_H);
+
+	reg = readl(iobase + APB_INT_ENABLE_H);
+	if (reg)
+		nrirqs = 32 + fls(reg);
+	else
+		nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
+
+	domain = irq_domain_add_linear(np, nrirqs,
+				       &irq_generic_chip_ops, NULL);
+	if (!domain) {
+		pr_err("%s: unable to add irq domain\n", np->name);
+		return -ENOMEM;
+	}
+
+	ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
+					     np->name, handle_level_irq, clr, 0,
+					     IRQ_GC_INIT_MASK_CACHE);
+	if (ret) {
+		pr_err("%s: unable to alloc irq domain gc\n", np->name);
+		return ret;
+	}
+
+	gc = irq_get_domain_generic_chip(domain, 0);
+	gc->private = domain;
+	gc->reg_base = iobase;
+
+	gc->chip_types[0].regs.mask = APB_INT_MASK_L;
+	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
+	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
+
+	if (nrirqs > 32) {
+		gc->chip_types[1].regs.mask = APB_INT_MASK_H;
+		gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
+		gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
+	}
+
+	irq_set_handler_data(irq, gc);
+	irq_set_chained_handler(irq, dw_apb_ictl_handler);
+
+	return 0;
+}
+IRQCHIP_DECLARE(dw_apb_ictl,
+		"snps,dw-apb-ictl", dw_apb_ictl_init);
-- 
1.7.10.4

Re: [PATCH 1/8] irqchip: add DesignWare APB ICTL interrupt controller

[Mark Rutland]

On Tue, Oct 08, 2013 at 01:24:26PM +0100, Sebastian Hesselbarth wrote:
> This adds an irqchip driver and corresponding devicetree binding for the
> secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Changelog:
> RFCv1->RFCv2:
> - added copyright reference
> 
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: devicetree@vger.kernel.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../interrupt-controller/snps,dw-apb-ictl.txt      |   29 ++++
>  drivers/irqchip/Kconfig                            |    4 +
>  drivers/irqchip/Makefile                           |    1 +
>  drivers/irqchip/irq-dw-apb-ictl.c                  |  142 ++++++++++++++++++++
>  4 files changed, 176 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
>  create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> new file mode 100644
> index 0000000..7ccd1ba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> @@ -0,0 +1,29 @@
> +Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
> +
> +Synopsys DesignWare provides interrupt controller IP for APB known as
> +dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
> +APB bus, e.g. Marvell Armada 1500.
> +
> +Required properties:
> +- compatible: shall be "snps,dw-apb-ictl"
> +- reg: base address of interrupt registers starting with ENABLE_LOW register

Is ENABLE_LOW the first register? Or are there registers before?

Is there only one bank of registers that needs to be defined?

This isn't just a base address, as it has a size too. The terminology's
rather inconsistent for reg properties in general...

> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: number of cells to encode an interrupt source, shall be 1

s/interrupt source/interrupt-specifier/

> +- interrupts: interrupt reference to primary interrupt controller

- interrupts: interrupts specifier for the sole interrupt fed to the
              parent interrupt controller.

Is there only a single output interrupt?

Is this required? Is it possible for this to be wired directly into a
CPU rather than another interrupt controller?

> +- interrupt-parent: (optional) reference specific primary interrupt controller
> +
> +The interrupt sources map to the corresponding bits in the interrupt
> +registers, i.e.
> +- 0 maps to bit 0 of low interrupts,
> +- 1 maps to bit 1 of low interrupts,
> +- 32 maps to bit 0 of high interrupts, and so on.

I couldn't see any public documentation for this, so I can't really
follow the "and so on", but I saw that this had optional FIQ support so
I assume there are more interrupt values that can be encoded?

> +
> +Example:
> +	aic: interrupt-controller@3000 {
> +		compatible = "snps,dw-apb-ictl";
> +		reg = <0x3000 0xc00>;
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 3792a1a..940638d 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -30,6 +30,10 @@ config ARM_VIC_NR
>  	  The maximum number of VICs available in the system, for
>  	  power management.
>  
> +config DW_APB_ICTL
> +	bool
> +	select IRQ_DOMAIN
> +
>  config IMGPDC_IRQ
>  	bool
>  	select GENERIC_IRQ_CHIP
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index c60b901..6427323 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
>  obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
>  obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o
>  obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o
> +obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
>  obj-$(CONFIG_METAG)			+= irq-metag-ext.o
>  obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
>  obj-$(CONFIG_ARCH_MOXART)		+= irq-moxart.o
> diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
> new file mode 100644
> index 0000000..bbcacee
> --- /dev/null
> +++ b/drivers/irqchip/irq-dw-apb-ictl.c
> @@ -0,0 +1,142 @@
> +/*
> + * Synopsys DW APB ICTL irqchip driver.
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * based on GPL'ed 2.6 kernel sources
> + *  (c) Marvell International Ltd.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#include "irqchip.h"
> +
> +#define APB_INT_ENABLE_L	0x00
> +#define APB_INT_ENABLE_H	0x04
> +#define APB_INT_MASK_L		0x08
> +#define APB_INT_MASK_H		0x0c
> +#define APB_INT_FINALSTATUS_L	0x30
> +#define APB_INT_FINALSTATUS_H	0x34
> +
> +static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
> +{
> +	struct irq_chip *chip = irq_get_chip(irq);
> +	struct irq_chip_generic *gc = irq_get_handler_data(irq);
> +	struct irq_domain *d = gc->private;
> +	u32 stat;
> +	int n;
> +
> +	chained_irq_enter(chip, desc);
> +
> +	for (n = 0; n < gc->num_ct; n++) {
> +		stat = readl_relaxed(gc->reg_base +
> +				     APB_INT_FINALSTATUS_L + 4 * n);
> +		while (stat) {
> +			u32 hwirq = ffs(stat) - 1;
> +			generic_handle_irq(irq_find_mapping(d,
> +					    gc->irq_base + hwirq + 32 * n));
> +			stat &= ~(1 << hwirq);
> +		}
> +	}
> +
> +	chained_irq_exit(chip, desc);
> +}
> +
> +static int __init dw_apb_ictl_init(struct device_node *np,
> +				   struct device_node *parent)
> +{
> +	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
> +	struct resource r;
> +	struct irq_domain *domain;
> +	struct irq_chip_generic *gc;
> +	void __iomem *iobase;
> +	int ret, nrirqs, irq;
> +	u32 reg;
> +
> +	/* Map the parent interrupt for the chained handler */
> +	irq = irq_of_parse_and_map(np, 0);
> +	if (irq <= 0) {
> +		pr_err("%s: unable to parse irq\n", np->name);
> +		return -EINVAL;
> +	}
> +
> +	ret = of_address_to_resource(np, 0, &r);
> +	if (ret) {
> +		pr_err("%s: unable to get resource\n", np->name);
> +		return ret;
> +	}
> +
> +	if (!request_mem_region(r.start, resource_size(&r), np->name)) {
> +		pr_err("%s: unable to request mem region\n", np->name);
> +		return -ENOMEM;
> +	}
> +
> +	iobase = ioremap(r.start, resource_size(&r));
> +	if (!iobase) {
> +		pr_err("%s: unable to map resource\n", np->name);
> +		return -ENOMEM;
> +	}

Could you not use of_iomap?

Also, I'd recommend using np->full_name for error messages, as that
gives you the full path for the node, which is far more helpful for
debugging than just the unqualified node name.

> +
> +	/*
> +	 * DW IP can be configured to allow 2-64 irqs. We can determine
> +	 * the number of irqs supported by writing into enable register
> +	 * and look for bits not set, as corresponding flip-flops will
> +	 * have been removed by sythesis tool.
> +	 */

Is that always true?

Cheers,
Mark.

Re: [PATCH 1/8] irqchip: add DesignWare APB ICTL interrupt controller

[Sebastian Hesselbarth]

On 10/08/2013 03:24 PM, Mark Rutland wrote:
> On Tue, Oct 08, 2013 at 01:24:26PM +0100, Sebastian Hesselbarth wrote:
>> This adds an irqchip driver and corresponding devicetree binding for the
>> secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> ---
[...]
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
>> new file mode 100644
>> index 0000000..7ccd1ba
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
>> @@ -0,0 +1,29 @@
>> +Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
>> +
>> +Synopsys DesignWare provides interrupt controller IP for APB known as
>> +dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
>> +APB bus, e.g. Marvell Armada 1500.
>> +
>> +Required properties:
>> +- compatible: shall be "snps,dw-apb-ictl"
>> +- reg: base address of interrupt registers starting with ENABLE_LOW register
>
> Is ENABLE_LOW the first register? Or are there registers before?

ENABLE_LOW is the first register.

> Is there only one bank of registers that needs to be defined?

The u-boot sources which this driver is based on have registers from
0x00 to 0xe0. So, yes it is one register block.

> This isn't just a base address, as it has a size too. The terminology's
> rather inconsistent for reg properties in general...

Ok, I will reword the reg related property descriptions.

>> +- interrupt-controller: identifies the node as an interrupt controller
>> +- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
>
> s/interrupt source/interrupt-specifier/

Ok.

>> +- interrupts: interrupt reference to primary interrupt controller
>
> - interrupts: interrupts specifier for the sole interrupt fed to the
>                parent interrupt controller.
>
> Is there only a single output interrupt?

At least for the SoC I am working with, yes.

> Is this required? Is it possible for this to be wired directly into a
> CPU rather than another interrupt controller?

Again, possible.

In general, for me it is impossible to foresee all possible scenarios
where this DW (!) IP is used in. Based on my current knowledge, this IP
is a secondary interrupt controller with 2-64 normal IRQs and one
upstream irq, FIQs are optional.

Synopsys website isn't a real chatterbox about their IP, googling
"dw_apb_ictl" gives e.g. [1]

[1] 
http://kona.ee.pitt.edu/socvlsi/lib/exe/fetch.php?media=dw_digital_ip_quickref.pdf

>> +- interrupt-parent: (optional) reference specific primary interrupt controller
>> +
>> +The interrupt sources map to the corresponding bits in the interrupt
>> +registers, i.e.
>> +- 0 maps to bit 0 of low interrupts,
>> +- 1 maps to bit 1 of low interrupts,
>> +- 32 maps to bit 0 of high interrupts, and so on.
>
> I couldn't see any public documentation for this, so I can't really
> follow the "and so on", but I saw that this had optional FIQ support so
> I assume there are more interrupt values that can be encoded?

Well, there is no public documentation.

As there can be 2-64 normal IRQs, I have chosen to number them according
to their bit position, starting with lower register bit 0 as hwirq 0.
Bit 0 of higher register gives hwirq 32 "and so on".

If FIQs are configured on a specific irq controller, that may give more
than 64 normal IRQs. If someone ever finds this IP with FIQs enabled,
I suggest to put them on 64+n. According to [1], it allows 1-8 optional
FIQs.

>> +Example:
>> +	aic: interrupt-controller@3000 {
>> +		compatible = "snps,dw-apb-ictl";
>> +		reg = <0x3000 0xc00>;
>> +		interrupt-controller;
>> +		#interrupt-cells = <1>;
>> +		interrupt-parent = <&gic>;
>> +		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> +	};
[...]
>> diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
>> new file mode 100644
>> index 0000000..bbcacee
>> --- /dev/null
>> +++ b/drivers/irqchip/irq-dw-apb-ictl.c
>> @@ -0,0 +1,142 @@
>> +/*
>> + * Synopsys DW APB ICTL irqchip driver.
>> + *
>> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> + *
>> + * based on GPL'ed 2.6 kernel sources
>> + *  (c) Marvell International Ltd.
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
[...]
>> +static int __init dw_apb_ictl_init(struct device_node *np,
>> +				   struct device_node *parent)
>> +{
>> +	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
>> +	struct resource r;
>> +	struct irq_domain *domain;
>> +	struct irq_chip_generic *gc;
>> +	void __iomem *iobase;
>> +	int ret, nrirqs, irq;
>> +	u32 reg;
>> +
>> +	/* Map the parent interrupt for the chained handler */
>> +	irq = irq_of_parse_and_map(np, 0);
>> +	if (irq <= 0) {
>> +		pr_err("%s: unable to parse irq\n", np->name);
>> +		return -EINVAL;
>> +	}
>> +
>> +	ret = of_address_to_resource(np, 0, &r);
>> +	if (ret) {
>> +		pr_err("%s: unable to get resource\n", np->name);
>> +		return ret;
>> +	}
>> +
>> +	if (!request_mem_region(r.start, resource_size(&r), np->name)) {
>> +		pr_err("%s: unable to request mem region\n", np->name);
>> +		return -ENOMEM;
>> +	}
>> +
>> +	iobase = ioremap(r.start, resource_size(&r));
>> +	if (!iobase) {
>> +		pr_err("%s: unable to map resource\n", np->name);
>> +		return -ENOMEM;
>> +	}
>
> Could you not use of_iomap?

Sure, but - correct me if I am wrong - while of_iomap just translates
and maps the resource, the above additionally protects the resource
from others mapping it.

> Also, I'd recommend using np->full_name for error messages, as that
> gives you the full path for the node, which is far more helpful for
> debugging than just the unqualified node name.

Ok.

>> +
>> +	/*
>> +	 * DW IP can be configured to allow 2-64 irqs. We can determine
>> +	 * the number of irqs supported by writing into enable register
>> +	 * and look for bits not set, as corresponding flip-flops will
>> +	 * have been removed by sythesis tool.
>> +	 */
>
> Is that always true?

 From my personal experience with hardware description and synthesis
tools, I'd say "yes, it is always true".

Even if it is not true, you register some irqs more than neccessary
and those will never trigger. What you know is, this number will never
be less than the real number of irqs supported.

Usually, for DW IP the number of configured features is somewhere in
the IPs registers. But without any documentation it is really not that
easy to guess the meaning of those bits.

Sebastian

Re: [PATCH 1/8] irqchip: add DesignWare APB ICTL interrupt controller

[Jisheng Zhang]

On Tue, 8 Oct 2013 05:24:26 -0700
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> wrote:

> This adds an irqchip driver and corresponding devicetree binding for the
> secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Changelog:
> RFCv1->RFCv2:
> - added copyright reference
> 
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: devicetree@vger.kernel.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../interrupt-controller/snps,dw-apb-ictl.txt      |   29 ++++
>  drivers/irqchip/Kconfig                            |    4 +
>  drivers/irqchip/Makefile                           |    1 +
>  drivers/irqchip/irq-dw-apb-ictl.c                  |  142
> ++++++++++++++++++++ 4 files changed, 176 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c
> 
> diff --git
> a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> new file mode 100644 index 0000000..7ccd1ba --- /dev/null
> +++
> b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> @@ -0,0 +1,29 @@ +Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
> +
> +Synopsys DesignWare provides interrupt controller IP for APB known as
> +dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs
> with +APB bus, e.g. Marvell Armada 1500.
> +
> +Required properties:
> +- compatible: shall be "snps,dw-apb-ictl"
> +- reg: base address of interrupt registers starting with ENABLE_LOW
> register +- interrupt-controller: identifies the node as an interrupt
> controller +- #interrupt-cells: number of cells to encode an interrupt
> source, shall be 1 +- interrupts: interrupt reference to primary interrupt
> controller +- interrupt-parent: (optional) reference specific primary
> interrupt controller +
> +The interrupt sources map to the corresponding bits in the interrupt
> +registers, i.e.
> +- 0 maps to bit 0 of low interrupts,
> +- 1 maps to bit 1 of low interrupts,
> +- 32 maps to bit 0 of high interrupts, and so on.
> +
> +Example:
> +       aic: interrupt-controller@3000 {
> +               compatible = "snps,dw-apb-ictl";
> +               reg = <0x3000 0xc00>;
> +               interrupt-controller;
> +               #interrupt-cells = <1>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 3792a1a..940638d 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -30,6 +30,10 @@ config ARM_VIC_NR
>           The maximum number of VICs available in the system, for
>           power management.
> 
> +config DW_APB_ICTL
> +       bool
> +       select IRQ_DOMAIN
> +
>  config IMGPDC_IRQ
>         bool
>         select GENERIC_IRQ_CHIP
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index c60b901..6427323 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP)                  += irq-mmp.o
>  obj-$(CONFIG_ARCH_MVEBU)               += irq-armada-370-xp.o
>  obj-$(CONFIG_ARCH_MXS)                 += irq-mxs.o
>  obj-$(CONFIG_ARCH_S3C24XX)             += irq-s3c24xx.o
> +obj-$(CONFIG_DW_APB_ICTL)              += irq-dw-apb-ictl.o
>  obj-$(CONFIG_METAG)                    += irq-metag-ext.o
>  obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)   += irq-metag.o
>  obj-$(CONFIG_ARCH_MOXART)              += irq-moxart.o
> diff --git a/drivers/irqchip/irq-dw-apb-ictl.c
> b/drivers/irqchip/irq-dw-apb-ictl.c new file mode 100644
> index 0000000..bbcacee
> --- /dev/null
> +++ b/drivers/irqchip/irq-dw-apb-ictl.c
> @@ -0,0 +1,142 @@
> +/*
> + * Synopsys DW APB ICTL irqchip driver.
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * based on GPL'ed 2.6 kernel sources
> + *  (c) Marvell International Ltd.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#include "irqchip.h"
> +
> +#define APB_INT_ENABLE_L       0x00
> +#define APB_INT_ENABLE_H       0x04
> +#define APB_INT_MASK_L         0x08
> +#define APB_INT_MASK_H         0x0c
> +#define APB_INT_FINALSTATUS_L  0x30
> +#define APB_INT_FINALSTATUS_H  0x34
> +
> +static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
> +{
> +       struct irq_chip *chip = irq_get_chip(irq);
> +       struct irq_chip_generic *gc = irq_get_handler_data(irq);
> +       struct irq_domain *d = gc->private;
> +       u32 stat;
> +       int n;
> +
> +       chained_irq_enter(chip, desc);
> +
> +       for (n = 0; n < gc->num_ct; n++) {
> +               stat = readl_relaxed(gc->reg_base +
> +                                    APB_INT_FINALSTATUS_L + 4 * n);
> +               while (stat) {
> +                       u32 hwirq = ffs(stat) - 1;
> +                       generic_handle_irq(irq_find_mapping(d,
> +                                           gc->irq_base + hwirq + 32 * n));
> +                       stat &= ~(1 << hwirq);
> +               }
> +       }
> +
> +       chained_irq_exit(chip, desc);
> +}
> +
> +static int __init dw_apb_ictl_init(struct device_node *np,
> +                                  struct device_node *parent)
> +{
> +       unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
> +       struct resource r;
> +       struct irq_domain *domain;
> +       struct irq_chip_generic *gc;
> +       void __iomem *iobase;
> +       int ret, nrirqs, irq;
> +       u32 reg;
> +
> +       /* Map the parent interrupt for the chained handler */
> +       irq = irq_of_parse_and_map(np, 0);
> +       if (irq <= 0) {
> +               pr_err("%s: unable to parse irq\n", np->name);
> +               return -EINVAL;
> +       }
> +
> +       ret = of_address_to_resource(np, 0, &r);
> +       if (ret) {
> +               pr_err("%s: unable to get resource\n", np->name);
> +               return ret;
> +       }
> +
> +       if (!request_mem_region(r.start, resource_size(&r), np->name)) {
> +               pr_err("%s: unable to request mem region\n", np->name);
> +               return -ENOMEM;
> +       }
> +
> +       iobase = ioremap(r.start, resource_size(&r));
> +       if (!iobase) {
> +               pr_err("%s: unable to map resource\n", np->name);
release_mem_region() is missing
> +               return -ENOMEM;
> +       }
> +
> +       /*
> +        * DW IP can be configured to allow 2-64 irqs. We can determine
> +        * the number of irqs supported by writing into enable register
> +        * and look for bits not set, as corresponding flip-flops will
> +        * have been removed by sythesis tool.
> +        */
> +
> +       /* mask and enable all interrupts */
> +       writel(~0, iobase + APB_INT_MASK_L);
> +       writel(~0, iobase + APB_INT_MASK_H);
> +       writel(~0, iobase + APB_INT_ENABLE_L);
> +       writel(~0, iobase + APB_INT_ENABLE_H);
> +
> +       reg = readl(iobase + APB_INT_ENABLE_H);
> +       if (reg)
> +               nrirqs = 32 + fls(reg);
> +       else
> +               nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
> +
> +       domain = irq_domain_add_linear(np, nrirqs,
> +                                      &irq_generic_chip_ops, NULL);
> +       if (!domain) {
> +               pr_err("%s: unable to add irq domain\n", np->name);
iounmap() and release_mem_region() is missing
> +               return -ENOMEM;
> +       }
> +
> +       ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ?
> 2 : 1,
> +                                            np->name, handle_level_irq,
> clr, 0,
> +                                            IRQ_GC_INIT_MASK_CACHE);
> +       if (ret) {
> +               pr_err("%s: unable to alloc irq domain gc\n", np->name);
> +               return ret;
> +       }
> +
> +       gc = irq_get_domain_generic_chip(domain, 0);
> +       gc->private = domain;
> +       gc->reg_base = iobase;
> +
> +       gc->chip_types[0].regs.mask = APB_INT_MASK_L;
> +       gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
> +       gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
> +
> +       if (nrirqs > 32) {
> +               gc->chip_types[1].regs.mask = APB_INT_MASK_H;
> +               gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
> +               gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
> +       }
> +
> +       irq_set_handler_data(irq, gc);
> +       irq_set_chained_handler(irq, dw_apb_ictl_handler);
> +
> +       return 0;
> +}
> +IRQCHIP_DECLARE(dw_apb_ictl,
> +               "snps,dw-apb-ictl", dw_apb_ictl_init);
> --
> 1.7.10.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 1/8] irqchip: add DesignWare APB ICTL interrupt controller

[Sebastian Hesselbarth]

This adds an irqchip driver and corresponding devicetree binding for the
secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
---
Changelog:
v1->v2:
- reword binding docu for reg property and add FIQ decoding note
  (Suggested by Mark Rutland)
- add cleanup on error path (Reported by Jisheng Zhang)
RFCv1->RFCv2:
- added copyright reference

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Jisheng Zhang <jszhang@marvell.com>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../interrupt-controller/snps,dw-apb-ictl.txt      |   32 +++++
 drivers/irqchip/Kconfig                            |    4 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-dw-apb-ictl.c                  |  150 ++++++++++++++++++++
 4 files changed, 187 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
 create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c

diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
new file mode 100644
index 0000000..4929117
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
@@ -0,0 +1,32 @@
+Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
+
+Synopsys DesignWare provides interrupt controller IP for APB known as
+dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
+APB bus, e.g. Marvell Armada 1500.
+
+Required properties:
+- compatible: shall be "snps,dw-apb-ictl"
+- reg: physical base address of the controller and length of memory mapped
+  region starting with ENABLE_LOW register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
+- interrupts: interrupt reference to primary interrupt controller
+- interrupt-parent: (optional) reference specific primary interrupt controller
+
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of low interrupts,
+- 1 maps to bit 1 of low interrupts,
+- 32 maps to bit 0 of high interrupts,
+- 33 maps to bit 1 of high interrupts,
+- (optional) fast interrupts start at 64.
+
+Example:
+	aic: interrupt-controller@3000 {
+		compatible = "snps,dw-apb-ictl";
+		reg = <0x3000 0xc00>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+	};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3792a1a..940638d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -30,6 +30,10 @@ config ARM_VIC_NR
 	  The maximum number of VICs available in the system, for
 	  power management.
 
+config DW_APB_ICTL
+	bool
+	select IRQ_DOMAIN
+
 config IMGPDC_IRQ
 	bool
 	select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c60b901..6427323 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o
 obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o
+obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)			+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
 obj-$(CONFIG_ARCH_MOXART)		+= irq-moxart.o
diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
new file mode 100644
index 0000000..31e231e
--- /dev/null
+++ b/drivers/irqchip/irq-dw-apb-ictl.c
@@ -0,0 +1,150 @@
+/*
+ * Synopsys DW APB ICTL irqchip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "irqchip.h"
+
+#define APB_INT_ENABLE_L	0x00
+#define APB_INT_ENABLE_H	0x04
+#define APB_INT_MASK_L		0x08
+#define APB_INT_MASK_H		0x0c
+#define APB_INT_FINALSTATUS_L	0x30
+#define APB_INT_FINALSTATUS_H	0x34
+
+static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	struct irq_chip_generic *gc = irq_get_handler_data(irq);
+	struct irq_domain *d = gc->private;
+	u32 stat;
+	int n;
+
+	chained_irq_enter(chip, desc);
+
+	for (n = 0; n < gc->num_ct; n++) {
+		stat = readl_relaxed(gc->reg_base +
+				     APB_INT_FINALSTATUS_L + 4 * n);
+		while (stat) {
+			u32 hwirq = ffs(stat) - 1;
+			generic_handle_irq(irq_find_mapping(d,
+					    gc->irq_base + hwirq + 32 * n));
+			stat &= ~(1 << hwirq);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static int __init dw_apb_ictl_init(struct device_node *np,
+				   struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	struct resource r;
+	struct irq_domain *domain;
+	struct irq_chip_generic *gc;
+	void __iomem *iobase;
+	int ret, nrirqs, irq;
+	u32 reg;
+
+	/* Map the parent interrupt for the chained handler */
+	irq = irq_of_parse_and_map(np, 0);
+	if (irq <= 0) {
+		pr_err("%s: unable to parse irq\n", np->full_name);
+		return -EINVAL;
+	}
+
+	ret = of_address_to_resource(np, 0, &r);
+	if (ret) {
+		pr_err("%s: unable to get resource\n", np->full_name);
+		return ret;
+	}
+
+	if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
+		pr_err("%s: unable to request mem region\n", np->full_name);
+		return -ENOMEM;
+	}
+
+	iobase = ioremap(r.start, resource_size(&r));
+	if (!iobase) {
+		pr_err("%s: unable to map resource\n", np->full_name);
+		ret = -ENOMEM;
+		goto err_release;
+	}
+
+	/*
+	 * DW IP can be configured to allow 2-64 irqs. We can determine
+	 * the number of irqs supported by writing into enable register
+	 * and look for bits not set, as corresponding flip-flops will
+	 * have been removed by sythesis tool.
+	 */
+
+	/* mask and enable all interrupts */
+	writel(~0, iobase + APB_INT_MASK_L);
+	writel(~0, iobase + APB_INT_MASK_H);
+	writel(~0, iobase + APB_INT_ENABLE_L);
+	writel(~0, iobase + APB_INT_ENABLE_H);
+
+	reg = readl(iobase + APB_INT_ENABLE_H);
+	if (reg)
+		nrirqs = 32 + fls(reg);
+	else
+		nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
+
+	domain = irq_domain_add_linear(np, nrirqs,
+				       &irq_generic_chip_ops, NULL);
+	if (!domain) {
+		pr_err("%s: unable to add irq domain\n", np->full_name);
+		ret = -ENOMEM;
+		goto err_unmap;
+	}
+
+	ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
+					     np->name, handle_level_irq, clr, 0,
+					     IRQ_GC_INIT_MASK_CACHE);
+	if (ret) {
+		pr_err("%s: unable to alloc irq domain gc\n", np->full_name);
+		goto err_unmap;
+	}
+
+	gc = irq_get_domain_generic_chip(domain, 0);
+	gc->private = domain;
+	gc->reg_base = iobase;
+
+	gc->chip_types[0].regs.mask = APB_INT_MASK_L;
+	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
+	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
+
+	if (nrirqs > 32) {
+		gc->chip_types[1].regs.mask = APB_INT_MASK_H;
+		gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
+		gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
+	}
+
+	irq_set_handler_data(irq, gc);
+	irq_set_chained_handler(irq, dw_apb_ictl_handler);
+
+	return 0;
+
+err_unmap:
+	iounmap(iobase);
+err_release:
+	release_mem_region(r.start, resource_size(&r));
+	return ret;
+}
+IRQCHIP_DECLARE(dw_apb_ictl,
+		"snps,dw-apb-ictl", dw_apb_ictl_init);
-- 
1.7.10.4

Re: [PATCH v2 1/8] irqchip: add DesignWare APB ICTL interrupt controller

[Sebastian Hesselbarth]

On 10/17/2013 07:37 AM, Sebastian Hesselbarth wrote:
> This adds an irqchip driver and corresponding devicetree binding for the
> secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Reviewed-by: Mark Rutland <mark.rutland@arm.com>
> Reviewed-by: Jisheng Zhang <jszhang@marvell.com>

Thomas (tglx),

can you please look at this and review it? IIRC, Olof already closed
the arm-soc merge window for v3.13, so there is plenty of time to get
this straight. Nevertheless, it would be great to have it in early in
v3.13.

Also, I prefer to have Mark look at the bindings again and maybe
update his remarks with the latest conclusions of KS.

Regards,
   Sebastian

> ---
> Changelog:
> v1->v2:
> - reword binding docu for reg property and add FIQ decoding note
>    (Suggested by Mark Rutland)
> - add cleanup on error path (Reported by Jisheng Zhang)
> RFCv1->RFCv2:
> - added copyright reference
>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Jisheng Zhang <jszhang@marvell.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>   .../interrupt-controller/snps,dw-apb-ictl.txt      |   32 +++++
>   drivers/irqchip/Kconfig                            |    4 +
>   drivers/irqchip/Makefile                           |    1 +
>   drivers/irqchip/irq-dw-apb-ictl.c                  |  150 ++++++++++++++++++++
>   4 files changed, 187 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
>   create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> new file mode 100644
> index 0000000..4929117
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> @@ -0,0 +1,32 @@
> +Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
> +
> +Synopsys DesignWare provides interrupt controller IP for APB known as
> +dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
> +APB bus, e.g. Marvell Armada 1500.
> +
> +Required properties:
> +- compatible: shall be "snps,dw-apb-ictl"
> +- reg: physical base address of the controller and length of memory mapped
> +  region starting with ENABLE_LOW register
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
> +- interrupts: interrupt reference to primary interrupt controller
> +- interrupt-parent: (optional) reference specific primary interrupt controller
> +
> +The interrupt sources map to the corresponding bits in the interrupt
> +registers, i.e.
> +- 0 maps to bit 0 of low interrupts,
> +- 1 maps to bit 1 of low interrupts,
> +- 32 maps to bit 0 of high interrupts,
> +- 33 maps to bit 1 of high interrupts,
> +- (optional) fast interrupts start at 64.
> +
> +Example:
> +	aic: interrupt-controller@3000 {
> +		compatible = "snps,dw-apb-ictl";
> +		reg = <0x3000 0xc00>;
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 3792a1a..940638d 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -30,6 +30,10 @@ config ARM_VIC_NR
>   	  The maximum number of VICs available in the system, for
>   	  power management.
>
> +config DW_APB_ICTL
> +	bool
> +	select IRQ_DOMAIN
> +
>   config IMGPDC_IRQ
>   	bool
>   	select GENERIC_IRQ_CHIP
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index c60b901..6427323 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
>   obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
>   obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o
>   obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o
> +obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
>   obj-$(CONFIG_METAG)			+= irq-metag-ext.o
>   obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
>   obj-$(CONFIG_ARCH_MOXART)		+= irq-moxart.o
> diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
> new file mode 100644
> index 0000000..31e231e
> --- /dev/null
> +++ b/drivers/irqchip/irq-dw-apb-ictl.c
> @@ -0,0 +1,150 @@
> +/*
> + * Synopsys DW APB ICTL irqchip driver.
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * based on GPL'ed 2.6 kernel sources
> + *  (c) Marvell International Ltd.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#include "irqchip.h"
> +
> +#define APB_INT_ENABLE_L	0x00
> +#define APB_INT_ENABLE_H	0x04
> +#define APB_INT_MASK_L		0x08
> +#define APB_INT_MASK_H		0x0c
> +#define APB_INT_FINALSTATUS_L	0x30
> +#define APB_INT_FINALSTATUS_H	0x34
> +
> +static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
> +{
> +	struct irq_chip *chip = irq_get_chip(irq);
> +	struct irq_chip_generic *gc = irq_get_handler_data(irq);
> +	struct irq_domain *d = gc->private;
> +	u32 stat;
> +	int n;
> +
> +	chained_irq_enter(chip, desc);
> +
> +	for (n = 0; n < gc->num_ct; n++) {
> +		stat = readl_relaxed(gc->reg_base +
> +				     APB_INT_FINALSTATUS_L + 4 * n);
> +		while (stat) {
> +			u32 hwirq = ffs(stat) - 1;
> +			generic_handle_irq(irq_find_mapping(d,
> +					    gc->irq_base + hwirq + 32 * n));
> +			stat &= ~(1 << hwirq);
> +		}
> +	}
> +
> +	chained_irq_exit(chip, desc);
> +}
> +
> +static int __init dw_apb_ictl_init(struct device_node *np,
> +				   struct device_node *parent)
> +{
> +	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
> +	struct resource r;
> +	struct irq_domain *domain;
> +	struct irq_chip_generic *gc;
> +	void __iomem *iobase;
> +	int ret, nrirqs, irq;
> +	u32 reg;
> +
> +	/* Map the parent interrupt for the chained handler */
> +	irq = irq_of_parse_and_map(np, 0);
> +	if (irq <= 0) {
> +		pr_err("%s: unable to parse irq\n", np->full_name);
> +		return -EINVAL;
> +	}
> +
> +	ret = of_address_to_resource(np, 0, &r);
> +	if (ret) {
> +		pr_err("%s: unable to get resource\n", np->full_name);
> +		return ret;
> +	}
> +
> +	if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
> +		pr_err("%s: unable to request mem region\n", np->full_name);
> +		return -ENOMEM;
> +	}
> +
> +	iobase = ioremap(r.start, resource_size(&r));
> +	if (!iobase) {
> +		pr_err("%s: unable to map resource\n", np->full_name);
> +		ret = -ENOMEM;
> +		goto err_release;
> +	}
> +
> +	/*
> +	 * DW IP can be configured to allow 2-64 irqs. We can determine
> +	 * the number of irqs supported by writing into enable register
> +	 * and look for bits not set, as corresponding flip-flops will
> +	 * have been removed by sythesis tool.
> +	 */
> +
> +	/* mask and enable all interrupts */
> +	writel(~0, iobase + APB_INT_MASK_L);
> +	writel(~0, iobase + APB_INT_MASK_H);
> +	writel(~0, iobase + APB_INT_ENABLE_L);
> +	writel(~0, iobase + APB_INT_ENABLE_H);
> +
> +	reg = readl(iobase + APB_INT_ENABLE_H);
> +	if (reg)
> +		nrirqs = 32 + fls(reg);
> +	else
> +		nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
> +
> +	domain = irq_domain_add_linear(np, nrirqs,
> +				       &irq_generic_chip_ops, NULL);
> +	if (!domain) {
> +		pr_err("%s: unable to add irq domain\n", np->full_name);
> +		ret = -ENOMEM;
> +		goto err_unmap;
> +	}
> +
> +	ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
> +					     np->name, handle_level_irq, clr, 0,
> +					     IRQ_GC_INIT_MASK_CACHE);
> +	if (ret) {
> +		pr_err("%s: unable to alloc irq domain gc\n", np->full_name);
> +		goto err_unmap;
> +	}
> +
> +	gc = irq_get_domain_generic_chip(domain, 0);
> +	gc->private = domain;
> +	gc->reg_base = iobase;
> +
> +	gc->chip_types[0].regs.mask = APB_INT_MASK_L;
> +	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
> +	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
> +
> +	if (nrirqs > 32) {
> +		gc->chip_types[1].regs.mask = APB_INT_MASK_H;
> +		gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
> +		gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
> +	}
> +
> +	irq_set_handler_data(irq, gc);
> +	irq_set_chained_handler(irq, dw_apb_ictl_handler);
> +
> +	return 0;
> +
> +err_unmap:
> +	iounmap(iobase);
> +err_release:
> +	release_mem_region(r.start, resource_size(&r));
> +	return ret;
> +}
> +IRQCHIP_DECLARE(dw_apb_ictl,
> +		"snps,dw-apb-ictl", dw_apb_ictl_init);
>

[PATCH 3/8] ARM: l2x0: add Marvell Tauros3 compatible

[Sebastian Hesselbarth]

This add a compatible for the Marvell Tauros3 cache controller which
is compatible with l2x0 cache controllers. While updating the binding
documentation, clean up the list of possible compatibles.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 Documentation/devicetree/bindings/arm/l2cc.txt |   22 +++++++++++-----------
 arch/arm/mm/cache-l2x0.c                       |    1 +
 2 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index c0c7626..a1d0cbd 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -7,20 +7,20 @@ The ARM L2 cache representation in the device tree should be done as follows:
 Required properties:
 
 - compatible : should be one of:
-	"arm,pl310-cache"
-	"arm,l220-cache"
-	"arm,l210-cache"
-	"marvell,aurora-system-cache": Marvell Controller designed to be
+  "arm,pl310-cache"
+  "arm,l220-cache"
+  "arm,l210-cache"
+  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+     offset needs to be added to the address before passing down to the L2
+     cache controller
+  "marvell,aurora-system-cache": Marvell Controller designed to be
      compatible with the ARM one, with system cache mode (meaning
      maintenance operations on L1 are broadcasted to the L2 and L2
      performs the same operation).
-	"marvell,"aurora-outer-cache: Marvell Controller designed to be
-	 compatible with the ARM one with outer cache mode.
-	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
-	offset needs to be added to the address before passing down to the L2
-	cache controller
-	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
-	                               "brcm,bcm11351-a2-pl310-cache"
+  "marvell,aurora-outer-cache": Marvell Controller designed to be
+     compatible with the ARM one with outer cache mode.
+  "marvell,tauros3-cache": Marvell Tauros3 cache controller.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 447da6f..90c776e 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -929,6 +929,7 @@ static const struct of_device_id l2x0_ids[] __initconst = {
 	  .data = (void *)&aurora_no_outer_data},
 	{ .compatible = "marvell,aurora-outer-cache",
 	  .data = (void *)&aurora_with_outer_data},
+	{ .compatible = "marvell,tauros3-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "brcm,bcm11351-a2-pl310-cache",
 	  .data = (void *)&bcm_l2x0_data},
 	{ .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
-- 
1.7.10.4

Re: [PATCH 3/8] ARM: l2x0: add Marvell Tauros3 compatible

[Mark Rutland]

On Tue, Oct 08, 2013 at 01:24:28PM +0100, Sebastian Hesselbarth wrote:
> This add a compatible for the Marvell Tauros3 cache controller which
> is compatible with l2x0 cache controllers. While updating the binding
> documentation, clean up the list of possible compatibles.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: devicetree@vger.kernel.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  Documentation/devicetree/bindings/arm/l2cc.txt |   22 +++++++++++-----------
>  arch/arm/mm/cache-l2x0.c                       |    1 +
>  2 files changed, 12 insertions(+), 11 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
> index c0c7626..a1d0cbd 100644
> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
> @@ -7,20 +7,20 @@ The ARM L2 cache representation in the device tree should be done as follows:
>  Required properties:
>  
>  - compatible : should be one of:
> -	"arm,pl310-cache"
> -	"arm,l220-cache"
> -	"arm,l210-cache"
> -	"marvell,aurora-system-cache": Marvell Controller designed to be
> +  "arm,pl310-cache"
> +  "arm,l220-cache"
> +  "arm,l210-cache"
> +  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
> +  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
> +     offset needs to be added to the address before passing down to the L2
> +     cache controller
> +  "marvell,aurora-system-cache": Marvell Controller designed to be
>       compatible with the ARM one, with system cache mode (meaning
>       maintenance operations on L1 are broadcasted to the L2 and L2
>       performs the same operation).
> -	"marvell,"aurora-outer-cache: Marvell Controller designed to be
> -	 compatible with the ARM one with outer cache mode.
> -	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
> -	offset needs to be added to the address before passing down to the L2
> -	cache controller
> -	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
> -	                               "brcm,bcm11351-a2-pl310-cache"
> +  "marvell,aurora-outer-cache": Marvell Controller designed to be
> +     compatible with the ARM one with outer cache mode.
> +  "marvell,tauros3-cache": Marvell Tauros3 cache controller.

How does the tauros3 cache differ from the other caches supported by the
l2x0 driver?

>  - cache-unified : Specifies the cache is a unified cache.
>  - cache-level : Should be set to 2 for a level 2 cache.
>  - reg : Physical base address and size of cache controller's memory mapped
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 447da6f..90c776e 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -929,6 +929,7 @@ static const struct of_device_id l2x0_ids[] __initconst = {
>  	  .data = (void *)&aurora_no_outer_data},
>  	{ .compatible = "marvell,aurora-outer-cache",
>  	  .data = (void *)&aurora_with_outer_data},
> +	{ .compatible = "marvell,tauros3-cache", .data = (void *)&l2x0_data },

Are we intending to handle this differently later? 

Or is it 100% compatible with the pl210 or pl220? We could just require
an entry later in the compatible string list instead...

Cheers,
Mark.

Re: [PATCH 3/8] ARM: l2x0: add Marvell Tauros3 compatible

[Sebastian Hesselbarth]

On 10/08/2013 03:41 PM, Mark Rutland wrote:
> On Tue, Oct 08, 2013 at 01:24:28PM +0100, Sebastian Hesselbarth wrote:
>> This add a compatible for the Marvell Tauros3 cache controller which
>> is compatible with l2x0 cache controllers. While updating the binding
>> documentation, clean up the list of possible compatibles.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> ---
[...]
>> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
>> index c0c7626..a1d0cbd 100644
>> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
>> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
>> @@ -7,20 +7,20 @@ The ARM L2 cache representation in the device tree should be done as follows:
>>   Required properties:
>>
>>   - compatible : should be one of:
>> -	"arm,pl310-cache"
>> -	"arm,l220-cache"
>> -	"arm,l210-cache"
>> -	"marvell,aurora-system-cache": Marvell Controller designed to be
>> +  "arm,pl310-cache"
>> +  "arm,l220-cache"
>> +  "arm,l210-cache"
>> +  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
>> +  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
>> +     offset needs to be added to the address before passing down to the L2
>> +     cache controller
>> +  "marvell,aurora-system-cache": Marvell Controller designed to be
>>        compatible with the ARM one, with system cache mode (meaning
>>        maintenance operations on L1 are broadcasted to the L2 and L2
>>        performs the same operation).
>> -	"marvell,"aurora-outer-cache: Marvell Controller designed to be
>> -	 compatible with the ARM one with outer cache mode.
>> -	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
>> -	offset needs to be added to the address before passing down to the L2
>> -	cache controller
>> -	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
>> -	                               "brcm,bcm11351-a2-pl310-cache"
>> +  "marvell,aurora-outer-cache": Marvell Controller designed to be
>> +     compatible with the ARM one with outer cache mode.
>> +  "marvell,tauros3-cache": Marvell Tauros3 cache controller.
>
> How does the tauros3 cache differ from the other caches supported by the
> l2x0 driver?

[added Gregory to Cc]

Good question. I cannot say at this time. I would have guessed that l2cc
on Armada 1500 and Armada 370/XP are more or less the same, as both use
Marvell's PJ4B CPU. Maybe, Gregory or Thomas can shed some light into
this.

>>   - cache-unified : Specifies the cache is a unified cache.
>>   - cache-level : Should be set to 2 for a level 2 cache.
>>   - reg : Physical base address and size of cache controller's memory mapped
>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>> index 447da6f..90c776e 100644
>> --- a/arch/arm/mm/cache-l2x0.c
>> +++ b/arch/arm/mm/cache-l2x0.c
>> @@ -929,6 +929,7 @@ static const struct of_device_id l2x0_ids[] __initconst = {
>>   	  .data = (void *)&aurora_no_outer_data},
>>   	{ .compatible = "marvell,aurora-outer-cache",
>>   	  .data = (void *)&aurora_with_outer_data},
>> +	{ .compatible = "marvell,tauros3-cache", .data = (void *)&l2x0_data },
>
> Are we intending to handle this differently later?
>
> Or is it 100% compatible with the pl210 or pl220? We could just require
> an entry later in the compatible string list instead...

No public documentation, no clear answer.

Tauros3 isn't 100% compatible with any of the ARM l2cc above, it has
additional "features" or "bugs" - call it whatever you want.

I am not an l2cc expert, but basically I see two options:
a) use (possibly) wrong existing compatible in current mv88de3100.dtsi
    now and fix later.
b) add tauros3 compatible now and add (possible) quirks/marvell-specific
    properties later.

IMHO b) is very likely to happen as l2x0_of_init in patch 8/8 already 
sets bits, I wasn't able to verify in public ARM l2cc docu.

But again, I am very open for suggestions here.

Sebastian

Re: [PATCH 3/8] ARM: l2x0: add Marvell Tauros3 compatible

[Gregory CLEMENT]

On 08/10/2013 18:05, Sebastian Hesselbarth wrote:
> On 10/08/2013 03:41 PM, Mark Rutland wrote:
>> On Tue, Oct 08, 2013 at 01:24:28PM +0100, Sebastian Hesselbarth wrote:
>>> This add a compatible for the Marvell Tauros3 cache controller which
>>> is compatible with l2x0 cache controllers. While updating the binding
>>> documentation, clean up the list of possible compatibles.
>>>
>>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>>> ---
> [...]
>>> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
>>> index c0c7626..a1d0cbd 100644
>>> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
>>> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
>>> @@ -7,20 +7,20 @@ The ARM L2 cache representation in the device tree should be done as follows:
>>>   Required properties:
>>>
>>>   - compatible : should be one of:
>>> -	"arm,pl310-cache"
>>> -	"arm,l220-cache"
>>> -	"arm,l210-cache"
>>> -	"marvell,aurora-system-cache": Marvell Controller designed to be
>>> +  "arm,pl310-cache"
>>> +  "arm,l220-cache"
>>> +  "arm,l210-cache"
>>> +  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
>>> +  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
>>> +     offset needs to be added to the address before passing down to the L2
>>> +     cache controller
>>> +  "marvell,aurora-system-cache": Marvell Controller designed to be
>>>        compatible with the ARM one, with system cache mode (meaning
>>>        maintenance operations on L1 are broadcasted to the L2 and L2
>>>        performs the same operation).
>>> -	"marvell,"aurora-outer-cache: Marvell Controller designed to be
>>> -	 compatible with the ARM one with outer cache mode.
>>> -	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
>>> -	offset needs to be added to the address before passing down to the L2
>>> -	cache controller
>>> -	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
>>> -	                               "brcm,bcm11351-a2-pl310-cache"
>>> +  "marvell,aurora-outer-cache": Marvell Controller designed to be
>>> +     compatible with the ARM one with outer cache mode.
>>> +  "marvell,tauros3-cache": Marvell Tauros3 cache controller.
>>
>> How does the tauros3 cache differ from the other caches supported by the
>> l2x0 driver?
> 
> [added Gregory to Cc]
> 
> Good question. I cannot say at this time. I would have guessed that l2cc
> on Armada 1500 and Armada 370/XP are more or less the same, as both use
> Marvell's PJ4B CPU. Maybe, Gregory or Thomas can shed some light into
> this.
> 
>>>   - cache-unified : Specifies the cache is a unified cache.
>>>   - cache-level : Should be set to 2 for a level 2 cache.
>>>   - reg : Physical base address and size of cache controller's memory mapped
>>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>>> index 447da6f..90c776e 100644
>>> --- a/arch/arm/mm/cache-l2x0.c
>>> +++ b/arch/arm/mm/cache-l2x0.c
>>> @@ -929,6 +929,7 @@ static const struct of_device_id l2x0_ids[] __initconst = {
>>>   	  .data = (void *)&aurora_no_outer_data},
>>>   	{ .compatible = "marvell,aurora-outer-cache",
>>>   	  .data = (void *)&aurora_with_outer_data},
>>> +	{ .compatible = "marvell,tauros3-cache", .data = (void *)&l2x0_data },
>>
>> Are we intending to handle this differently later?
>>
>> Or is it 100% compatible with the pl210 or pl220? We could just require
>> an entry later in the compatible string list instead...
> 
> No public documentation, no clear answer.
> 
> Tauros3 isn't 100% compatible with any of the ARM l2cc above, it has
> additional "features" or "bugs" - call it whatever you want.
> 
> I am not an l2cc expert, but basically I see two options:
> a) use (possibly) wrong existing compatible in current mv88de3100.dtsi
>     now and fix later.
> b) add tauros3 compatible now and add (possible) quirks/marvell-specific
>     properties later.
> 
> IMHO b) is very likely to happen as l2x0_of_init in patch 8/8 already 
> sets bits, I wasn't able to verify in public ARM l2cc docu.

I agree with Sebastian. I don't have more information that Sebastian, but
as it is definitely a different controller of the ones from ARM, it should
have its own compatible string. Then latter when we will discover new feature
and/or bugs, we will be able to manage them without requiring people to update
their dtb. If I understood well it is the philosophy behind the device tree.

Regards,

> 
> But again, I am very open for suggestions here.
> 
> Sebastian
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 3/8] ARM: l2x0: add Marvell Tauros3 compatible

[Mark Rutland]

On Tue, Oct 08, 2013 at 05:33:23PM +0100, Gregory CLEMENT wrote:
> On 08/10/2013 18:05, Sebastian Hesselbarth wrote:
> > On 10/08/2013 03:41 PM, Mark Rutland wrote:
> >> On Tue, Oct 08, 2013 at 01:24:28PM +0100, Sebastian Hesselbarth wrote:
> >>> This add a compatible for the Marvell Tauros3 cache controller which
> >>> is compatible with l2x0 cache controllers. While updating the binding
> >>> documentation, clean up the list of possible compatibles.
> >>>
> >>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> >>> ---
> > [...]
> >>> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
> >>> index c0c7626..a1d0cbd 100644
> >>> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
> >>> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
> >>> @@ -7,20 +7,20 @@ The ARM L2 cache representation in the device tree should be done as follows:
> >>>   Required properties:
> >>>
> >>>   - compatible : should be one of:
> >>> -	"arm,pl310-cache"
> >>> -	"arm,l220-cache"
> >>> -	"arm,l210-cache"
> >>> -	"marvell,aurora-system-cache": Marvell Controller designed to be
> >>> +  "arm,pl310-cache"
> >>> +  "arm,l220-cache"
> >>> +  "arm,l210-cache"
> >>> +  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
> >>> +  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
> >>> +     offset needs to be added to the address before passing down to the L2
> >>> +     cache controller
> >>> +  "marvell,aurora-system-cache": Marvell Controller designed to be
> >>>        compatible with the ARM one, with system cache mode (meaning
> >>>        maintenance operations on L1 are broadcasted to the L2 and L2
> >>>        performs the same operation).
> >>> -	"marvell,"aurora-outer-cache: Marvell Controller designed to be
> >>> -	 compatible with the ARM one with outer cache mode.
> >>> -	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
> >>> -	offset needs to be added to the address before passing down to the L2
> >>> -	cache controller
> >>> -	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
> >>> -	                               "brcm,bcm11351-a2-pl310-cache"
> >>> +  "marvell,aurora-outer-cache": Marvell Controller designed to be
> >>> +     compatible with the ARM one with outer cache mode.
> >>> +  "marvell,tauros3-cache": Marvell Tauros3 cache controller.
> >>
> >> How does the tauros3 cache differ from the other caches supported by the
> >> l2x0 driver?
> > 
> > [added Gregory to Cc]
> > 
> > Good question. I cannot say at this time. I would have guessed that l2cc
> > on Armada 1500 and Armada 370/XP are more or less the same, as both use
> > Marvell's PJ4B CPU. Maybe, Gregory or Thomas can shed some light into
> > this.
> > 
> >>>   - cache-unified : Specifies the cache is a unified cache.
> >>>   - cache-level : Should be set to 2 for a level 2 cache.
> >>>   - reg : Physical base address and size of cache controller's memory mapped
> >>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> >>> index 447da6f..90c776e 100644
> >>> --- a/arch/arm/mm/cache-l2x0.c
> >>> +++ b/arch/arm/mm/cache-l2x0.c
> >>> @@ -929,6 +929,7 @@ static const struct of_device_id l2x0_ids[] __initconst = {
> >>>   	  .data = (void *)&aurora_no_outer_data},
> >>>   	{ .compatible = "marvell,aurora-outer-cache",
> >>>   	  .data = (void *)&aurora_with_outer_data},
> >>> +	{ .compatible = "marvell,tauros3-cache", .data = (void *)&l2x0_data },
> >>
> >> Are we intending to handle this differently later?
> >>
> >> Or is it 100% compatible with the pl210 or pl220? We could just require
> >> an entry later in the compatible string list instead...
> > 
> > No public documentation, no clear answer.
> > 
> > Tauros3 isn't 100% compatible with any of the ARM l2cc above, it has
> > additional "features" or "bugs" - call it whatever you want.
> > 
> > I am not an l2cc expert, but basically I see two options:
> > a) use (possibly) wrong existing compatible in current mv88de3100.dtsi
> >     now and fix later.
> > b) add tauros3 compatible now and add (possible) quirks/marvell-specific
> >     properties later.
> > 
> > IMHO b) is very likely to happen as l2x0_of_init in patch 8/8 already 
> > sets bits, I wasn't able to verify in public ARM l2cc docu.
> 
> I agree with Sebastian. I don't have more information that Sebastian, but
> as it is definitely a different controller of the ones from ARM, it should
> have its own compatible string. Then latter when we will discover new feature
> and/or bugs, we will be able to manage them without requiring people to update
> their dtb. If I understood well it is the philosophy behind the device tree.

Please note that I wasn't arguing for people to have to update their
dtb. I was only suggesting that we'd have something like:

	compatible = "marvell,tauros3-cache", "arm,l220-cache";

Which would function now, and later the driver could choose to check for
"marvell,tauros3-cache" and do something different.

However, given that we don't have sufficient documentation to tell how
close the tauros3 cache is to any ARM l2x0 variant, having just the
"marvell,tauros3-cache" string in dts and supporting this in the driver
makes sense to me.

Cheers,
Mark.

Re: [PATCH 3/8] ARM: l2x0: add Marvell Tauros3 compatible

[Gregory CLEMENT]

On 09/10/2013 10:50, Mark Rutland wrote:
> On Tue, Oct 08, 2013 at 05:33:23PM +0100, Gregory CLEMENT wrote:
>> On 08/10/2013 18:05, Sebastian Hesselbarth wrote:
>>> On 10/08/2013 03:41 PM, Mark Rutland wrote:
>>>> On Tue, Oct 08, 2013 at 01:24:28PM +0100, Sebastian Hesselbarth wrote:
>>>>> This add a compatible for the Marvell Tauros3 cache controller which
>>>>> is compatible with l2x0 cache controllers. While updating the binding
>>>>> documentation, clean up the list of possible compatibles.
>>>>>
>>>>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>>>>> ---
>>> [...]
>>>>> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
>>>>> index c0c7626..a1d0cbd 100644
>>>>> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
>>>>> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
>>>>> @@ -7,20 +7,20 @@ The ARM L2 cache representation in the device tree should be done as follows:
>>>>>   Required properties:
>>>>>
>>>>>   - compatible : should be one of:
>>>>> -	"arm,pl310-cache"
>>>>> -	"arm,l220-cache"
>>>>> -	"arm,l210-cache"
>>>>> -	"marvell,aurora-system-cache": Marvell Controller designed to be
>>>>> +  "arm,pl310-cache"
>>>>> +  "arm,l220-cache"
>>>>> +  "arm,l210-cache"
>>>>> +  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
>>>>> +  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
>>>>> +     offset needs to be added to the address before passing down to the L2
>>>>> +     cache controller
>>>>> +  "marvell,aurora-system-cache": Marvell Controller designed to be
>>>>>        compatible with the ARM one, with system cache mode (meaning
>>>>>        maintenance operations on L1 are broadcasted to the L2 and L2
>>>>>        performs the same operation).
>>>>> -	"marvell,"aurora-outer-cache: Marvell Controller designed to be
>>>>> -	 compatible with the ARM one with outer cache mode.
>>>>> -	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
>>>>> -	offset needs to be added to the address before passing down to the L2
>>>>> -	cache controller
>>>>> -	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
>>>>> -	                               "brcm,bcm11351-a2-pl310-cache"
>>>>> +  "marvell,aurora-outer-cache": Marvell Controller designed to be
>>>>> +     compatible with the ARM one with outer cache mode.
>>>>> +  "marvell,tauros3-cache": Marvell Tauros3 cache controller.
>>>>
>>>> How does the tauros3 cache differ from the other caches supported by the
>>>> l2x0 driver?
>>>
>>> [added Gregory to Cc]
>>>
>>> Good question. I cannot say at this time. I would have guessed that l2cc
>>> on Armada 1500 and Armada 370/XP are more or less the same, as both use
>>> Marvell's PJ4B CPU. Maybe, Gregory or Thomas can shed some light into
>>> this.
>>>
>>>>>   - cache-unified : Specifies the cache is a unified cache.
>>>>>   - cache-level : Should be set to 2 for a level 2 cache.
>>>>>   - reg : Physical base address and size of cache controller's memory mapped
>>>>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>>>>> index 447da6f..90c776e 100644
>>>>> --- a/arch/arm/mm/cache-l2x0.c
>>>>> +++ b/arch/arm/mm/cache-l2x0.c
>>>>> @@ -929,6 +929,7 @@ static const struct of_device_id l2x0_ids[] __initconst = {
>>>>>   	  .data = (void *)&aurora_no_outer_data},
>>>>>   	{ .compatible = "marvell,aurora-outer-cache",
>>>>>   	  .data = (void *)&aurora_with_outer_data},
>>>>> +	{ .compatible = "marvell,tauros3-cache", .data = (void *)&l2x0_data },
>>>>
>>>> Are we intending to handle this differently later?
>>>>
>>>> Or is it 100% compatible with the pl210 or pl220? We could just require
>>>> an entry later in the compatible string list instead...
>>>
>>> No public documentation, no clear answer.
>>>
>>> Tauros3 isn't 100% compatible with any of the ARM l2cc above, it has
>>> additional "features" or "bugs" - call it whatever you want.
>>>
>>> I am not an l2cc expert, but basically I see two options:
>>> a) use (possibly) wrong existing compatible in current mv88de3100.dtsi
>>>     now and fix later.
>>> b) add tauros3 compatible now and add (possible) quirks/marvell-specific
>>>     properties later.
>>>
>>> IMHO b) is very likely to happen as l2x0_of_init in patch 8/8 already 
>>> sets bits, I wasn't able to verify in public ARM l2cc docu.
>>
>> I agree with Sebastian. I don't have more information that Sebastian, but
>> as it is definitely a different controller of the ones from ARM, it should
>> have its own compatible string. Then latter when we will discover new feature
>> and/or bugs, we will be able to manage them without requiring people to update
>> their dtb. If I understood well it is the philosophy behind the device tree.
> 
> Please note that I wasn't arguing for people to have to update their
> dtb. I was only suggesting that we'd have something like:
> 
> 	compatible = "marvell,tauros3-cache", "arm,l220-cache";
> 
> Which would function now, and later the driver could choose to check for
> "marvell,tauros3-cache" and do something different.
> 

Oh you're right, I didn't think about it

> However, given that we don't have sufficient documentation to tell how
> close the tauros3 cache is to any ARM l2x0 variant, having just the
> "marvell,tauros3-cache" string in dts and supporting this in the driver
> makes sense to me.

Given the information we get from Jisheng "The tauros3 and PL310 are
different although the programming interface are compatible" something like:

compatible = "marvell,tauros3-cache", "arm,pl310-cache";

should work.

Regards,
-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 3/8] ARM: l2x0: add Marvell Tauros3 compatible

[Sebastian Hesselbarth]

On 10/09/2013 10:50 AM, Mark Rutland wrote:
> On Tue, Oct 08, 2013 at 05:33:23PM +0100, Gregory CLEMENT wrote:
>> On 08/10/2013 18:05, Sebastian Hesselbarth wrote:
>>> On 10/08/2013 03:41 PM, Mark Rutland wrote:
>>>> On Tue, Oct 08, 2013 at 01:24:28PM +0100, Sebastian Hesselbarth wrote:
>>>>> This add a compatible for the Marvell Tauros3 cache controller which
>>>>> is compatible with l2x0 cache controllers. While updating the binding
>>>>> documentation, clean up the list of possible compatibles.
>>>>>
>>>>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>>>>> ---

Added Jisheng and Lennert to Cc.

Lennert, while looking for differences between ARM PL310 and
Marvell Tauros3 cache controller in a GPL'ed 2.6 kernel source
from Asus, I found arch/arm/mm/cache-tauros3.c which states you
as the original author. If that is wrong, please ignore this.

>>> [...]
>>>>> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
>>>>> index c0c7626..a1d0cbd 100644
>>>>> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
>>>>> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
>>>>> @@ -7,20 +7,20 @@ The ARM L2 cache representation in the device tree should be done as follows:
>>>>>    Required properties:
>>>>>
>>>>>    - compatible : should be one of:
>>>>> -	"arm,pl310-cache"
>>>>> -	"arm,l220-cache"
>>>>> -	"arm,l210-cache"
>>>>> -	"marvell,aurora-system-cache": Marvell Controller designed to be
>>>>> +  "arm,pl310-cache"
>>>>> +  "arm,l220-cache"
>>>>> +  "arm,l210-cache"
>>>>> +  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
>>>>> +  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
>>>>> +     offset needs to be added to the address before passing down to the L2
>>>>> +     cache controller
>>>>> +  "marvell,aurora-system-cache": Marvell Controller designed to be
>>>>>         compatible with the ARM one, with system cache mode (meaning
>>>>>         maintenance operations on L1 are broadcasted to the L2 and L2
>>>>>         performs the same operation).
>>>>> -	"marvell,"aurora-outer-cache: Marvell Controller designed to be
>>>>> -	 compatible with the ARM one with outer cache mode.
>>>>> -	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
>>>>> -	offset needs to be added to the address before passing down to the L2
>>>>> -	cache controller
>>>>> -	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
>>>>> -	                               "brcm,bcm11351-a2-pl310-cache"
>>>>> +  "marvell,aurora-outer-cache": Marvell Controller designed to be
>>>>> +     compatible with the ARM one with outer cache mode.
>>>>> +  "marvell,tauros3-cache": Marvell Tauros3 cache controller.
>>>>
>>>> How does the tauros3 cache differ from the other caches supported by the
>>>> l2x0 driver?
>>>
>>> [added Gregory to Cc]
>>>
>>> Good question. I cannot say at this time. I would have guessed that l2cc
>>> on Armada 1500 and Armada 370/XP are more or less the same, as both use
>>> Marvell's PJ4B CPU. Maybe, Gregory or Thomas can shed some light into
>>> this.

As stated above, I did some research on the differences. I think I can
prepare a patch providing tauros3 specific callbacks for .inv_all,
.flush_all, .resume, and .save.

For full .setup, I need to do more research on the CTRL/AUX_CTRL bits.

Up to now, I think pl310 specific callbacks (.resume, .save, .setup)
are _not_ suitable for tauros3. In the source from above, there are
no TAG_LATENCY_CTRL, DATA_LATENCY_CTRL, ADDR_FILTER_*, nor POWER_CTRL
registers.

>>>>>    - cache-unified : Specifies the cache is a unified cache.
>>>>>    - cache-level : Should be set to 2 for a level 2 cache.
>>>>>    - reg : Physical base address and size of cache controller's memory mapped
>>>>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>>>>> index 447da6f..90c776e 100644
>>>>> --- a/arch/arm/mm/cache-l2x0.c
>>>>> +++ b/arch/arm/mm/cache-l2x0.c
>>>>> @@ -929,6 +929,7 @@ static const struct of_device_id l2x0_ids[] __initconst = {
>>>>>    	  .data = (void *)&aurora_no_outer_data},
>>>>>    	{ .compatible = "marvell,aurora-outer-cache",
>>>>>    	  .data = (void *)&aurora_with_outer_data},
>>>>> +	{ .compatible = "marvell,tauros3-cache", .data = (void *)&l2x0_data },
>>>>
>>>> Are we intending to handle this differently later?
>>>>
>>>> Or is it 100% compatible with the pl210 or pl220? We could just require
>>>> an entry later in the compatible string list instead...
>>>
>>> No public documentation, no clear answer.
>>>
>>> Tauros3 isn't 100% compatible with any of the ARM l2cc above, it has
>>> additional "features" or "bugs" - call it whatever you want.
>>>
>>> I am not an l2cc expert, but basically I see two options:
>>> a) use (possibly) wrong existing compatible in current mv88de3100.dtsi
>>>      now and fix later.
>>> b) add tauros3 compatible now and add (possible) quirks/marvell-specific
>>>      properties later.
>>>
>>> IMHO b) is very likely to happen as l2x0_of_init in patch 8/8 already
>>> sets bits, I wasn't able to verify in public ARM l2cc docu.
>>
>> I agree with Sebastian. I don't have more information that Sebastian, but
>> as it is definitely a different controller of the ones from ARM, it should
>> have its own compatible string. Then latter when we will discover new feature
>> and/or bugs, we will be able to manage them without requiring people to update
>> their dtb. If I understood well it is the philosophy behind the device tree.
>
> Please note that I wasn't arguing for people to have to update their
> dtb. I was only suggesting that we'd have something like:
>
> 	compatible = "marvell,tauros3-cache", "arm,l220-cache";
>
> Which would function now, and later the driver could choose to check for
> "marvell,tauros3-cache" and do something different.

Agree, we really should use above compatible style more often.

> However, given that we don't have sufficient documentation to tell how
> close the tauros3 cache is to any ARM l2x0 variant, having just the
> "marvell,tauros3-cache" string in dts and supporting this in the driver
> makes sense to me.

I found some source, which is possibly enough documentation. Also, I am
counting on Jisheng or Lennert to comment on the hidden magic in
Tauros3.

Sebastian

Re: [PATCH 3/8] ARM: l2x0: add Marvell Tauros3 compatible

[Lennert Buytenhek]

On Wed, Oct 09, 2013 at 09:27:14PM +0200, Sebastian Hesselbarth wrote:

> >>>>>This add a compatible for the Marvell Tauros3 cache controller which
> >>>>>is compatible with l2x0 cache controllers. While updating the binding
> >>>>>documentation, clean up the list of possible compatibles.
> >>>>>
> >>>>>Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> >>>>>---
> 
> Added Jisheng and Lennert to Cc.
> 
> Lennert, while looking for differences between ARM PL310 and
> Marvell Tauros3 cache controller in a GPL'ed 2.6 kernel source
> from Asus, I found arch/arm/mm/cache-tauros3.c which states you
> as the original author. If that is wrong, please ignore this.

I'm the original author of cache-tauros2.c, but I've never heard of
Tauros3, and my name probably ended up in there via cp(1).

[PATCH v2 3/8] ARM: l2x0: add Marvell Tauros3 support

[Sebastian Hesselbarth]

This adds support for the Marvell Tauros3 cache controller which
is compatible with pl310 cache controller but broadcasts L1 cache
operations to L2 cache. While updating the binding documentation,
clean up the list of possible compatibles. Also reorder driver
compatibles to allow non-ARM derivated to be compatible to ARM
cache controller compatibles.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
---
Changelog:
v1->v2:
- add tauros3 data without outer cache ops (Suggested by Jisheng Zhang)
- reorder compatibles to allow derivates to be compatible with ARM
  controllers (Suggested by Mark Rutland)

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Jisheng Zhang <jszhang@marvell.com>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 Documentation/devicetree/bindings/arm/l2cc.txt |   23 +++++------
 arch/arm/include/asm/hardware/cache-l2x0.h     |    1 +
 arch/arm/mm/cache-l2x0.c                       |   49 ++++++++++++++++++++----
 arch/arm/mm/cache-tauros3.h                    |   41 ++++++++++++++++++++
 4 files changed, 95 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mm/cache-tauros3.h

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index c0c7626..b513cb8 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -7,20 +7,21 @@ The ARM L2 cache representation in the device tree should be done as follows:
 Required properties:
 
 - compatible : should be one of:
-	"arm,pl310-cache"
-	"arm,l220-cache"
-	"arm,l210-cache"
-	"marvell,aurora-system-cache": Marvell Controller designed to be
+  "arm,pl310-cache"
+  "arm,l220-cache"
+  "arm,l210-cache"
+  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+     offset needs to be added to the address before passing down to the L2
+     cache controller
+  "marvell,aurora-system-cache": Marvell Controller designed to be
      compatible with the ARM one, with system cache mode (meaning
      maintenance operations on L1 are broadcasted to the L2 and L2
      performs the same operation).
-	"marvell,"aurora-outer-cache: Marvell Controller designed to be
-	 compatible with the ARM one with outer cache mode.
-	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
-	offset needs to be added to the address before passing down to the L2
-	cache controller
-	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
-	                               "brcm,bcm11351-a2-pl310-cache"
+  "marvell,aurora-outer-cache": Marvell Controller designed to be
+     compatible with the ARM one with outer cache mode.
+  "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+     with arm,pl310-cache controller.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 3b2c40b..6795ff7 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -131,6 +131,7 @@ struct l2x0_regs {
 	unsigned long prefetch_ctrl;
 	unsigned long pwr_ctrl;
 	unsigned long ctrl;
+	unsigned long aux2_ctrl;
 };
 
 extern struct l2x0_regs l2x0_saved_regs;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 447da6f..a70a4f5 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "cache-tauros3.h"
 #include "cache-aurora-l2.h"
 
 #define CACHE_LINE_SIZE		32
@@ -767,6 +768,14 @@ static void aurora_save(void)
 	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 }
 
+static void __init tauros3_save(void)
+{
+	l2x0_saved_regs.aux2_ctrl =
+		readl_relaxed(l2x0_base + TAUROS3_AUX2_CTRL);
+	l2x0_saved_regs.prefetch_ctrl =
+		readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+}
+
 static void l2x0_resume(void)
 {
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
@@ -821,6 +830,18 @@ static void aurora_resume(void)
 	}
 }
 
+static void tauros3_resume(void)
+{
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+		writel_relaxed(l2x0_saved_regs.aux2_ctrl,
+			       l2x0_base + TAUROS3_AUX2_CTRL);
+		writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+			       l2x0_base + L2X0_PREFETCH_CTRL);
+	}
+
+	l2x0_resume();
+}
+
 static void __init aurora_broadcast_l2_commands(void)
 {
 	__u32 u;
@@ -906,6 +927,15 @@ static const struct l2x0_of_data aurora_no_outer_data = {
 	},
 };
 
+static const struct l2x0_of_data tauros3_data = {
+	.setup = NULL,
+	.save  = tauros3_save,
+	/* Tauros3 broadcasts L1 cache operations to L2 */
+	.outer_cache = {
+		.resume      = tauros3_resume,
+	},
+};
+
 static const struct l2x0_of_data bcm_l2x0_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -922,17 +952,20 @@ static const struct l2x0_of_data bcm_l2x0_data = {
 };
 
 static const struct of_device_id l2x0_ids[] __initconst = {
+	{ .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
+	  .data = (void *)&bcm_l2x0_data},
+	{ .compatible = "brcm,bcm11351-a2-pl310-cache",
+	  .data = (void *)&bcm_l2x0_data},
+	{ .compatible = "marvell,aurora-outer-cache",
+	  .data = (void *)&aurora_with_outer_data},
+	{ .compatible = "marvell,aurora-system-cache",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,tauros3-cache",
+	  .data = (void *)&tauros3_data },
+	/* keep ARM compatibles below non-ARM derivates */
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
-	{ .compatible = "marvell,aurora-system-cache",
-	  .data = (void *)&aurora_no_outer_data},
-	{ .compatible = "marvell,aurora-outer-cache",
-	  .data = (void *)&aurora_with_outer_data},
-	{ .compatible = "brcm,bcm11351-a2-pl310-cache",
-	  .data = (void *)&bcm_l2x0_data},
-	{ .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
-	  .data = (void *)&bcm_l2x0_data},
 	{}
 };
 
diff --git a/arch/arm/mm/cache-tauros3.h b/arch/arm/mm/cache-tauros3.h
new file mode 100644
index 0000000..02c0a97
--- /dev/null
+++ b/arch/arm/mm/cache-tauros3.h
@@ -0,0 +1,41 @@
+/*
+ * Marvell Tauros3 cache controller includes
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_HARDWARE_TAUROS3_H
+#define __ASM_ARM_HARDWARE_TAUROS3_H
+
+/*
+ * Marvell Tauros3 L2CC is compatible with PL310 r0p0
+ * but with PREFETCH_CTRL (r2p0) and an additional event counter.
+ * Also, there is AUX2_CTRL for some Marvell specific control.
+ */
+
+#define TAUROS3_EVENT_CNT2_CFG		0x224
+#define TAUROS3_EVENT_CNT2_VAL		0x228
+#define TAUROS3_INV_ALL			0x780
+#define TAUROS3_CLEAN_ALL		0x784
+#define TAUROS3_AUX2_CTRL		0x820
+
+/* Registers shifts and masks */
+#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN	(1 << 2)
+
+#endif
-- 
1.7.10.4

[PATCH 7/8] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

This adds very basic device tree files for the Marvell Armada 1500 SoC
(88DE3100) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
device comprising the Armada 1500 SoC above.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
Changelog:
RCFv2->v1:
- switch to (soon to be) correct "marvell,pj4b" cpu compatible
- reference fixed-clock for uarts instead of hard-coded clock-frequency
- disable timers except two for clksrc and clkevt
RFCv1->RFCv2:
- add binding documentation (Reported by Jason Cooper)
- change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
- add copyright reference
- adapt compatibles to mach-berlin instead of mach-mvebu

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/arm/marvell,berlin.txt     |   23 ++
 arch/arm/boot/dts/Makefile                         |    2 +
 arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts      |   29 +++
 arch/arm/boot/dts/mv88de3100.dtsi                  |  227 ++++++++++++++++++++
 4 files changed, 281 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
 create mode 100644 arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
 create mode 100644 arch/arm/boot/dts/mv88de3100.dtsi

diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
new file mode 100644
index 0000000..e389cba
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -0,0 +1,23 @@
+Marvell Berlin (88DE3xxx) family SoCs Device Tree Bindings
+---------------------------------------------------------------
+
+Boards with a SoC of the Marvell Berlin (88DE3xxx) family, e.g. Armada 1500
+shall have the following properties:
+
+* Required root node properties:
+compatible: must contain "marvell,berlin"
+
+In addition, the above compatible shall be extended with the specific
+SoC and board used. Currently known SoC compatibles are:
+    "marvell,88de3100"	for Marvell 88DE3100 (Armada 1500),
+    "marvell,88de3010"	for Marvell 88DE3010 (Armada 1000),
+    "marvell,88de3005"	for Marvell 88DE3005 (Armada 1500-mini)
+
+* Example:
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "sony,nsz-gs7", "marvell,88de3100", "marvell,berlin";
+
+	...
+}
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..e86933a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -46,6 +46,8 @@ dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \
 	bcm28155-ap.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += \
+	mv88de3100-sony-nsz-gs7.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
 	da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts b/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
new file mode 100644
index 0000000..81025ce
--- /dev/null
+++ b/arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Sony NSZ-GS7
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "mv88de3100.dtsi"
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "sony,nsz-gs7", "marvell,88de3100", "marvell,berlin";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>; /* 1 GB */
+	};
+};
+
+&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/mv88de3100.dtsi b/arch/arm/boot/dts/mv88de3100.dtsi
new file mode 100644
index 0000000..d434015
--- /dev/null
+++ b/arch/arm/boot/dts/mv88de3100.dtsi
@@ -0,0 +1,227 @@
+/*
+ * Device Tree Include file for Marvell 88DE3100 (Armada 1500) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Marvell 88DE3100 (Armada 1500) SoC";
+	compatible = "marvell,88de3100", "marvell,berlin";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <1>;
+		};
+	};
+
+	clocks {
+		smclk: sysmgr-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
+		cfgclk: cfg-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+		};
+
+		sysclk: system-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <400000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+
+		ranges = <0 0xf7000000 0x1000000>;
+
+		l2: l2-cache-controller@ac0000 {
+			compatible = "marvell,tauros3-cache";
+			reg = <0xac0000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		gic: interrupt-controller@ad1000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		local-timer@ad0600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xad0600 0x20>;
+			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+		};
+
+		apb@e80000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xe80000 0x10000>;
+			interrupt-parent = <&aic>;
+
+			timer0: timer@2c00 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c00 0x14>;
+				interrupts = <8>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer1: timer@2c14 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c14 0x14>;
+				interrupts = <9>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer2: timer@2c28 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c28 0x14>;
+				interrupts = <10>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer3: timer@2c3c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c3c 0x14>;
+				interrupts = <11>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer4: timer@2c50 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c50 0x14>;
+				interrupts = <12>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer5: timer@2c64 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c64 0x14>;
+				interrupts = <13>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer6: timer@2c78 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c78 0x14>;
+				interrupts = <14>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer7: timer@2c8c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c8c 0x14>;
+				interrupts = <15>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			aic: interrupt-controller@3000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0x3000 0xc00>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		apb@fc0000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xfc0000 0x10000>;
+			interrupt-parent = <&sic>;
+
+			uart0: serial@9000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x9000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <8>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart1: serial@a000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xa000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <9>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart2: serial@b000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xb000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <10>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			sic: interrupt-controller@e000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0xe000 0x400>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
-- 
1.7.10.4

Re: [PATCH 7/8] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

On 10/08/2013 02:24 PM, Sebastian Hesselbarth wrote:
> This adds very basic device tree files for the Marvell Armada 1500 SoC
> (88DE3100) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
> nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
> uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
> device comprising the Armada 1500 SoC above.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Reviewed-by: Jason Cooper <jason@lakedaemon.net>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> ---
> Changelog:
> RCFv2->v1:
> - switch to (soon to be) correct "marvell,pj4b" cpu compatible
> - reference fixed-clock for uarts instead of hard-coded clock-frequency
> - disable timers except two for clksrc and clkevt
> RFCv1->RFCv2:
> - add binding documentation (Reported by Jason Cooper)
> - change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
> - add copyright reference
> - adapt compatibles to mach-berlin instead of mach-mvebu
>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: devicetree@vger.kernel.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>   .../devicetree/bindings/arm/marvell,berlin.txt     |   23 ++
>   arch/arm/boot/dts/Makefile                         |    2 +
>   arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts      |   29 +++
>   arch/arm/boot/dts/mv88de3100.dtsi                  |  227 ++++++++++++++++++++
>   4 files changed, 281 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
>   create mode 100644 arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
>   create mode 100644 arch/arm/boot/dts/mv88de3100.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> new file mode 100644
> index 0000000..e389cba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> @@ -0,0 +1,23 @@
> +Marvell Berlin (88DE3xxx) family SoCs Device Tree Bindings
> +---------------------------------------------------------------
> +
> +Boards with a SoC of the Marvell Berlin (88DE3xxx) family, e.g. Armada 1500
> +shall have the following properties:
> +
> +* Required root node properties:
> +compatible: must contain "marvell,berlin"
> +
> +In addition, the above compatible shall be extended with the specific
> +SoC and board used. Currently known SoC compatibles are:
> +    "marvell,88de3100"	for Marvell 88DE3100 (Armada 1500),
> +    "marvell,88de3010"	for Marvell 88DE3010 (Armada 1000),
> +    "marvell,88de3005"	for Marvell 88DE3005 (Armada 1500-mini)

Jisheng,

I am trying to follow your request to get rid of 88DExxxx numbering and
replace it where possible with berlin type-of names.

For the above, I have:
"marvell,berlin-bg2" for Marvell Armada 1500 (BG2, 88DE3100)
"marvell,berlin-bg2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)

I cannot pin down Armada 1000 in the BG naming scheme. It would be great
if you provide info here on how Marvell would like to see the
compatibles.

Sebastian

Re: [PATCH 7/8] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

On 10/15/2013 01:13 AM, Sebastian Hesselbarth wrote:
> On 10/08/2013 02:24 PM, Sebastian Hesselbarth wrote:
>> This adds very basic device tree files for the Marvell Armada 1500 SoC
>> (88DE3100) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
>> nodes for cpus, some clocks, l2 cache controller, local timer, apb
>> timers,
>> uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
>> device comprising the Armada 1500 SoC above.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> Reviewed-by: Jason Cooper <jason@lakedaemon.net>
>> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>> ---
>> Changelog:
>> RCFv2->v1:
>> - switch to (soon to be) correct "marvell,pj4b" cpu compatible
>> - reference fixed-clock for uarts instead of hard-coded clock-frequency
>> - disable timers except two for clksrc and clkevt
>> RFCv1->RFCv2:
>> - add binding documentation (Reported by Jason Cooper)
>> - change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
>> - add copyright reference
>> - adapt compatibles to mach-berlin instead of mach-mvebu
>>
>> Cc: Jason Cooper <jason@lakedaemon.net>
>> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-doc@vger.kernel.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> ---
>>   .../devicetree/bindings/arm/marvell,berlin.txt     |   23 ++
>>   arch/arm/boot/dts/Makefile                         |    2 +
>>   arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts      |   29 +++
>>   arch/arm/boot/dts/mv88de3100.dtsi                  |  227
>> ++++++++++++++++++++
>>   4 files changed, 281 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/arm/marvell,berlin.txt
>>   create mode 100644 arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts
>>   create mode 100644 arch/arm/boot/dts/mv88de3100.dtsi
>>
>> diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> new file mode 100644
>> index 0000000..e389cba
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> @@ -0,0 +1,23 @@
>> +Marvell Berlin (88DE3xxx) family SoCs Device Tree Bindings
>> +---------------------------------------------------------------
>> +
>> +Boards with a SoC of the Marvell Berlin (88DE3xxx) family, e.g.
>> Armada 1500
>> +shall have the following properties:
>> +
>> +* Required root node properties:
>> +compatible: must contain "marvell,berlin"
>> +
>> +In addition, the above compatible shall be extended with the specific
>> +SoC and board used. Currently known SoC compatibles are:
>> +    "marvell,88de3100"    for Marvell 88DE3100 (Armada 1500),
>> +    "marvell,88de3010"    for Marvell 88DE3010 (Armada 1000),
>> +    "marvell,88de3005"    for Marvell 88DE3005 (Armada 1500-mini)
>
> Jisheng,

(adding Jisheng to Cc, missed that)

> I am trying to follow your request to get rid of 88DExxxx numbering and
> replace it where possible with berlin type-of names.
>
> For the above, I have:
> "marvell,berlin-bg2" for Marvell Armada 1500 (BG2, 88DE3100)
> "marvell,berlin-bg2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
>
> I cannot pin down Armada 1000 in the BG naming scheme. It would be great
> if you provide info here on how Marvell would like to see the
> compatibles.
>
> Sebastian
>

Re: [PATCH 7/8] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Jisheng Zhang]

Hi Sebastian,

On Mon, 14 Oct 2013 16:13:21 -0700
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> wrote:

> On 10/08/2013 02:24 PM, Sebastian Hesselbarth wrote:
> > This adds very basic device tree files for the Marvell Armada 1500 SoC
> > (88DE3100) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
> > nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
> > uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
> > device comprising the Armada 1500 SoC above.
> >
> > Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> > Reviewed-by: Jason Cooper <jason@lakedaemon.net>
> > Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> > ---
> > Changelog:
> > RCFv2->v1:
> > - switch to (soon to be) correct "marvell,pj4b" cpu compatible
> > - reference fixed-clock for uarts instead of hard-coded clock-frequency
> > - disable timers except two for clksrc and clkevt
> > RFCv1->RFCv2:
> > - add binding documentation (Reported by Jason Cooper)
> > - change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
> > - add copyright reference
> > - adapt compatibles to mach-berlin instead of mach-mvebu
> >
> > Cc: Jason Cooper <jason@lakedaemon.net>
> > Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-doc@vger.kernel.org
> > Cc: linux-arm-kernel@lists.infradead.org
> > Cc: linux-kernel@vger.kernel.org
> > ---
> >   .../devicetree/bindings/arm/marvell,berlin.txt     |   23 ++
> >   arch/arm/boot/dts/Makefile                         |    2 +
> >   arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts      |   29 +++
> >   arch/arm/boot/dts/mv88de3100.dtsi                  |  227
> > ++++++++++++++++++++ 4 files changed, 281 insertions(+)
> >   create mode 100644
> > Documentation/devicetree/bindings/arm/marvell,berlin.txt create mode
> > 100644 arch/arm/boot/dts/mv88de3100-sony-nsz-gs7.dts create mode 100644
> > arch/arm/boot/dts/mv88de3100.dtsi
> >
> > diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> > b/Documentation/devicetree/bindings/arm/marvell,berlin.txt new file mode
> > 100644 index 0000000..e389cba
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
> > @@ -0,0 +1,23 @@
> > +Marvell Berlin (88DE3xxx) family SoCs Device Tree Bindings
> > +---------------------------------------------------------------
> > +
> > +Boards with a SoC of the Marvell Berlin (88DE3xxx) family, e.g. Armada
> > 1500 +shall have the following properties:
> > +
> > +* Required root node properties:
> > +compatible: must contain "marvell,berlin"
> > +
> > +In addition, the above compatible shall be extended with the specific
> > +SoC and board used. Currently known SoC compatibles are:
> > +    "marvell,88de3100"	for Marvell 88DE3100 (Armada 1500),
> > +    "marvell,88de3010"	for Marvell 88DE3010 (Armada 1000),
> > +    "marvell,88de3005"	for Marvell 88DE3005 (Armada 1500-mini)
> 
> Jisheng,
> 
> I am trying to follow your request to get rid of 88DExxxx numbering and
> replace it where possible with berlin type-of names.
Thanks for your help.
> 
> For the above, I have:
> "marvell,berlin-bg2" for Marvell Armada 1500 (BG2, 88DE3100)
We prefer "marvell,berlin2" for BG2
> "marvell,berlin-bg2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
we prefer "marvell,berlin2cd" for BG2CD, "marvell,berlin2ct" for BG2CT,
and "marvell,berlin3" for BG3, etc.


Thanks,
Jisheng

[PATCH v2 7/8] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

This adds very basic device tree files for the Marvell Armada 1500 SoC
(Berlin BG2) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
device comprising the Armada 1500 SoC above.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
---
Changelog:
v1->v2:
- add "arm,pl310-cache" compatible to l2cc (Suggested by Mark Rutland)
- replace 88DE3xxx numbering with SoC variant name
  (Requested by Jisheng Zhang)
RCFv2->v1:
- switch to (soon to be) correct "marvell,pj4b" cpu compatible
- reference fixed-clock for uarts instead of hard-coded clock-frequency
- disable timers except two for clksrc and clkevt
RFCv1->RFCv2:
- add binding documentation (Reported by Jason Cooper)
- change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
- add copyright reference
- adapt compatibles to mach-berlin instead of mach-mvebu

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Jisheng Zhang <jszhang@marvell.com>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
 arch/arm/boot/dts/Makefile                         |    2 +
 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
 arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
 4 files changed, 282 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
 create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
 create mode 100644 arch/arm/boot/dts/berlin2.dtsi

diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
new file mode 100644
index 0000000..737afa5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -0,0 +1,24 @@
+Marvell Berlin SoC Family Device Tree Bindings
+---------------------------------------------------------------
+
+Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
+shall have the following properties:
+
+* Required root node properties:
+compatible: must contain "marvell,berlin"
+
+In addition, the above compatible shall be extended with the specific
+SoC and board used. Currently known SoC compatibles are:
+    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
+    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
+    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
+    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)
+
+* Example:
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
+
+	...
+}
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..c9c1a6c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -46,6 +46,8 @@ dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \
 	bcm28155-ap.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += \
+	berlin2-sony-nsz-gs7.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
 	da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
new file mode 100644
index 0000000..c72bfd4
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Sony NSZ-GS7
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "berlin2.dtsi"
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>; /* 1 GB */
+	};
+};
+
+&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
new file mode 100644
index 0000000..56a1af2
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -0,0 +1,227 @@
+/*
+ * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Marvell Armada 1500 (BG2) SoC";
+	compatible = "marvell,berlin2", "marvell,berlin";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <1>;
+		};
+	};
+
+	clocks {
+		smclk: sysmgr-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
+		cfgclk: cfg-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+		};
+
+		sysclk: system-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <400000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+
+		ranges = <0 0xf7000000 0x1000000>;
+
+		l2: l2-cache-controller@ac0000 {
+			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
+			reg = <0xac0000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		gic: interrupt-controller@ad1000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		local-timer@ad0600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xad0600 0x20>;
+			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+		};
+
+		apb@e80000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xe80000 0x10000>;
+			interrupt-parent = <&aic>;
+
+			timer0: timer@2c00 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c00 0x14>;
+				interrupts = <8>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer1: timer@2c14 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c14 0x14>;
+				interrupts = <9>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer2: timer@2c28 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c28 0x14>;
+				interrupts = <10>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer3: timer@2c3c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c3c 0x14>;
+				interrupts = <11>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer4: timer@2c50 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c50 0x14>;
+				interrupts = <12>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer5: timer@2c64 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c64 0x14>;
+				interrupts = <13>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer6: timer@2c78 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c78 0x14>;
+				interrupts = <14>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer7: timer@2c8c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c8c 0x14>;
+				interrupts = <15>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			aic: interrupt-controller@3000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0x3000 0xc00>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		apb@fc0000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xfc0000 0x10000>;
+			interrupt-parent = <&sic>;
+
+			uart0: serial@9000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x9000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <8>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart1: serial@a000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xa000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <9>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart2: serial@b000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xb000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <10>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			sic: interrupt-controller@e000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0xe000 0x400>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
-- 
1.7.10.4

[PATCH v3 0/9] ARM: Initial support for Marvell Berlin SoCs

[Sebastian Hesselbarth]

Another kernel release, another Berlin SoC patch set...

This patch set add initial support for Marvell Berlin SoCs, e.g.
Armada 1000, Armada 1500, Armada 1500-mini.

Currently, initial support just means that the kernel boots on one
CPU, sets up irq, timers, and UART. As Berlin SoCs share some amount
of IP with Marvell PXA/MMP[23] SoCs plus some Synopsys DW IP, I expect
functionality to grow quite quickly. I do have further patches for
SMP but do not want to stall this patch set even further.

Compared to last version sent, this patch set adds additional support
for the Armada 1500-mini and the Google Chromecast. It is based on
v3.12 and still depends on on ARM's arch-wide call to of_clk_init [3]
plus some fixes for Synopsys DWtimers [4]. 

This patch set is indended for v3.13. I hope to the last Acks required
from Thomas Gleixner and the DT maintainers, rebase on v3.13-rc1 and
send the pull request.

I also prepared a branch for those able to test with open boot loader
on GoogleTV or Chromecast at
https://github.com/shesselba/linux-berlin.git topic/initial

[1] https://lkml.org/lkml/2013/8/16/626
[2] https://lkml.org/lkml/2013/8/27/608
[3] http://www.spinics.net/lists/arm-kernel/msg276175.html
[4] http://www.spinics.net/lists/arm-kernel/msg277763.html

Sebastian Hesselbarth (9):
  irqchip: add DesignWare APB ICTL interrupt controller
  MAINTAINERS: add ARM Marvell Berlin SoC
  ARM: l2x0: add Marvell Tauros3 support
  ARM: add Marvell Berlin SoC familiy to Marvell doc
  ARM: add Marvell Berlin SoCs to multi_v7_defconfig
  ARM: add Marvell Berlin UART0 lowlevel debug
  ARM: add Armada 1500 and Sony NSZ-GS7 device tree files
  ARM: add Armada 1500-mini and Chromecast device tree files
  ARM: add initial support for Marvell Berlin SoCs

 Documentation/arm/Marvell/README                   |   29 +++
 Documentation/devicetree/bindings/arm/l2cc.txt     |   23 +-
 .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
 .../interrupt-controller/snps,dw-apb-ictl.txt      |   32 +++
 MAINTAINERS                                        |    6 +
 arch/arm/Kconfig                                   |    2 +
 arch/arm/Kconfig.debug                             |   10 +
 arch/arm/Makefile                                  |    1 +
 arch/arm/boot/dts/Makefile                         |    3 +
 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
 arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
 arch/arm/boot/dts/berlin2cd-google-chromecast.dts  |   29 +++
 arch/arm/boot/dts/berlin2cd.dtsi                   |  212 ++++++++++++++++++
 arch/arm/configs/multi_v7_defconfig                |    3 +
 arch/arm/include/asm/hardware/cache-l2x0.h         |    1 +
 arch/arm/mach-berlin/Kconfig                       |   30 +++
 arch/arm/mach-berlin/Makefile                      |    1 +
 arch/arm/mach-berlin/berlin.c                      |   39 ++++
 arch/arm/mm/cache-l2x0.c                           |   49 ++++-
 arch/arm/mm/cache-tauros3.h                        |   41 ++++
 drivers/irqchip/Kconfig                            |    4 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-dw-apb-ictl.c                  |  150 +++++++++++++
 23 files changed, 927 insertions(+), 19 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
 create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
 create mode 100644 arch/arm/boot/dts/berlin2.dtsi
 create mode 100644 arch/arm/boot/dts/berlin2cd-google-chromecast.dts
 create mode 100644 arch/arm/boot/dts/berlin2cd.dtsi
 create mode 100644 arch/arm/mach-berlin/Kconfig
 create mode 100644 arch/arm/mach-berlin/Makefile
 create mode 100644 arch/arm/mach-berlin/berlin.c
 create mode 100644 arch/arm/mm/cache-tauros3.h
 create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c

---
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Landley <rob@landley.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Kevin Hilman <khilman@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
-- 
1.7.10.4

[PATCH v3 1/9] irqchip: add DesignWare APB ICTL interrupt controller

[Sebastian Hesselbarth]

This adds an irqchip driver and corresponding devicetree binding for the
secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
---
Changelog:
v2->v3:
- none
v1->v2:
- reword binding docu for reg property and add FIQ decoding note
  (Suggested by Mark Rutland)
- add cleanup on error path (Reported by Jisheng Zhang)
RFCv1->RFCv2:
- added copyright reference

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Landley <rob@landley.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../interrupt-controller/snps,dw-apb-ictl.txt      |   32 +++++
 drivers/irqchip/Kconfig                            |    4 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-dw-apb-ictl.c                  |  150 ++++++++++++++++++++
 4 files changed, 187 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
 create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c

diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
new file mode 100644
index 0000000..4929117
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
@@ -0,0 +1,32 @@
+Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
+
+Synopsys DesignWare provides interrupt controller IP for APB known as
+dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
+APB bus, e.g. Marvell Armada 1500.
+
+Required properties:
+- compatible: shall be "snps,dw-apb-ictl"
+- reg: physical base address of the controller and length of memory mapped
+  region starting with ENABLE_LOW register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
+- interrupts: interrupt reference to primary interrupt controller
+- interrupt-parent: (optional) reference specific primary interrupt controller
+
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of low interrupts,
+- 1 maps to bit 1 of low interrupts,
+- 32 maps to bit 0 of high interrupts,
+- 33 maps to bit 1 of high interrupts,
+- (optional) fast interrupts start at 64.
+
+Example:
+	aic: interrupt-controller@3000 {
+		compatible = "snps,dw-apb-ictl";
+		reg = <0x3000 0xc00>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+	};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3792a1a..940638d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -30,6 +30,10 @@ config ARM_VIC_NR
 	  The maximum number of VICs available in the system, for
 	  power management.
 
+config DW_APB_ICTL
+	bool
+	select IRQ_DOMAIN
+
 config IMGPDC_IRQ
 	bool
 	select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c60b901..6427323 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o
 obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o
+obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)			+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
 obj-$(CONFIG_ARCH_MOXART)		+= irq-moxart.o
diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
new file mode 100644
index 0000000..31e231e
--- /dev/null
+++ b/drivers/irqchip/irq-dw-apb-ictl.c
@@ -0,0 +1,150 @@
+/*
+ * Synopsys DW APB ICTL irqchip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "irqchip.h"
+
+#define APB_INT_ENABLE_L	0x00
+#define APB_INT_ENABLE_H	0x04
+#define APB_INT_MASK_L		0x08
+#define APB_INT_MASK_H		0x0c
+#define APB_INT_FINALSTATUS_L	0x30
+#define APB_INT_FINALSTATUS_H	0x34
+
+static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	struct irq_chip_generic *gc = irq_get_handler_data(irq);
+	struct irq_domain *d = gc->private;
+	u32 stat;
+	int n;
+
+	chained_irq_enter(chip, desc);
+
+	for (n = 0; n < gc->num_ct; n++) {
+		stat = readl_relaxed(gc->reg_base +
+				     APB_INT_FINALSTATUS_L + 4 * n);
+		while (stat) {
+			u32 hwirq = ffs(stat) - 1;
+			generic_handle_irq(irq_find_mapping(d,
+					    gc->irq_base + hwirq + 32 * n));
+			stat &= ~(1 << hwirq);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static int __init dw_apb_ictl_init(struct device_node *np,
+				   struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	struct resource r;
+	struct irq_domain *domain;
+	struct irq_chip_generic *gc;
+	void __iomem *iobase;
+	int ret, nrirqs, irq;
+	u32 reg;
+
+	/* Map the parent interrupt for the chained handler */
+	irq = irq_of_parse_and_map(np, 0);
+	if (irq <= 0) {
+		pr_err("%s: unable to parse irq\n", np->full_name);
+		return -EINVAL;
+	}
+
+	ret = of_address_to_resource(np, 0, &r);
+	if (ret) {
+		pr_err("%s: unable to get resource\n", np->full_name);
+		return ret;
+	}
+
+	if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
+		pr_err("%s: unable to request mem region\n", np->full_name);
+		return -ENOMEM;
+	}
+
+	iobase = ioremap(r.start, resource_size(&r));
+	if (!iobase) {
+		pr_err("%s: unable to map resource\n", np->full_name);
+		ret = -ENOMEM;
+		goto err_release;
+	}
+
+	/*
+	 * DW IP can be configured to allow 2-64 irqs. We can determine
+	 * the number of irqs supported by writing into enable register
+	 * and look for bits not set, as corresponding flip-flops will
+	 * have been removed by sythesis tool.
+	 */
+
+	/* mask and enable all interrupts */
+	writel(~0, iobase + APB_INT_MASK_L);
+	writel(~0, iobase + APB_INT_MASK_H);
+	writel(~0, iobase + APB_INT_ENABLE_L);
+	writel(~0, iobase + APB_INT_ENABLE_H);
+
+	reg = readl(iobase + APB_INT_ENABLE_H);
+	if (reg)
+		nrirqs = 32 + fls(reg);
+	else
+		nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
+
+	domain = irq_domain_add_linear(np, nrirqs,
+				       &irq_generic_chip_ops, NULL);
+	if (!domain) {
+		pr_err("%s: unable to add irq domain\n", np->full_name);
+		ret = -ENOMEM;
+		goto err_unmap;
+	}
+
+	ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
+					     np->name, handle_level_irq, clr, 0,
+					     IRQ_GC_INIT_MASK_CACHE);
+	if (ret) {
+		pr_err("%s: unable to alloc irq domain gc\n", np->full_name);
+		goto err_unmap;
+	}
+
+	gc = irq_get_domain_generic_chip(domain, 0);
+	gc->private = domain;
+	gc->reg_base = iobase;
+
+	gc->chip_types[0].regs.mask = APB_INT_MASK_L;
+	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
+	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
+
+	if (nrirqs > 32) {
+		gc->chip_types[1].regs.mask = APB_INT_MASK_H;
+		gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
+		gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
+	}
+
+	irq_set_handler_data(irq, gc);
+	irq_set_chained_handler(irq, dw_apb_ictl_handler);
+
+	return 0;
+
+err_unmap:
+	iounmap(iobase);
+err_release:
+	release_mem_region(r.start, resource_size(&r));
+	return ret;
+}
+IRQCHIP_DECLARE(dw_apb_ictl,
+		"snps,dw-apb-ictl", dw_apb_ictl_init);
-- 
1.7.10.4

Re: [PATCH v3 1/9] irqchip: add DesignWare APB ICTL interrupt controller

[Thomas Gleixner]

On Tue, 5 Nov 2013, Sebastian Hesselbarth wrote:

> This adds an irqchip driver and corresponding devicetree binding for the
> secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Reviewed-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Reviewed-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

Reviewed-by: Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
--
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[PATCH v3 3/9] ARM: l2x0: add Marvell Tauros3 support

[Sebastian Hesselbarth]

This adds support for the Marvell Tauros3 cache controller which
is compatible with pl310 cache controller but broadcasts L1 cache
operations to L2 cache. While updating the binding documentation,
clean up the list of possible compatibles. Also reorder driver
compatibles to allow non-ARM derivated to be compatible to ARM
cache controller compatibles.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
---
Changelog:
v2->v3:
- none
v1->v2:
- add tauros3 data without outer cache ops (Suggested by Jisheng Zhang)
- reorder compatibles to allow derivates to be compatible with ARM
  controllers (Suggested by Mark Rutland)

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Rob Landley <rob@landley.net>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 Documentation/devicetree/bindings/arm/l2cc.txt |   23 +++++------
 arch/arm/include/asm/hardware/cache-l2x0.h     |    1 +
 arch/arm/mm/cache-l2x0.c                       |   49 ++++++++++++++++++++----
 arch/arm/mm/cache-tauros3.h                    |   41 ++++++++++++++++++++
 4 files changed, 95 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mm/cache-tauros3.h

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index c0c7626..b513cb8 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -7,20 +7,21 @@ The ARM L2 cache representation in the device tree should be done as follows:
 Required properties:
 
 - compatible : should be one of:
-	"arm,pl310-cache"
-	"arm,l220-cache"
-	"arm,l210-cache"
-	"marvell,aurora-system-cache": Marvell Controller designed to be
+  "arm,pl310-cache"
+  "arm,l220-cache"
+  "arm,l210-cache"
+  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+     offset needs to be added to the address before passing down to the L2
+     cache controller
+  "marvell,aurora-system-cache": Marvell Controller designed to be
      compatible with the ARM one, with system cache mode (meaning
      maintenance operations on L1 are broadcasted to the L2 and L2
      performs the same operation).
-	"marvell,"aurora-outer-cache: Marvell Controller designed to be
-	 compatible with the ARM one with outer cache mode.
-	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
-	offset needs to be added to the address before passing down to the L2
-	cache controller
-	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
-	                               "brcm,bcm11351-a2-pl310-cache"
+  "marvell,aurora-outer-cache": Marvell Controller designed to be
+     compatible with the ARM one with outer cache mode.
+  "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+     with arm,pl310-cache controller.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 3b2c40b..6795ff7 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -131,6 +131,7 @@ struct l2x0_regs {
 	unsigned long prefetch_ctrl;
 	unsigned long pwr_ctrl;
 	unsigned long ctrl;
+	unsigned long aux2_ctrl;
 };
 
 extern struct l2x0_regs l2x0_saved_regs;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 447da6f..a70a4f5 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "cache-tauros3.h"
 #include "cache-aurora-l2.h"
 
 #define CACHE_LINE_SIZE		32
@@ -767,6 +768,14 @@ static void aurora_save(void)
 	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 }
 
+static void __init tauros3_save(void)
+{
+	l2x0_saved_regs.aux2_ctrl =
+		readl_relaxed(l2x0_base + TAUROS3_AUX2_CTRL);
+	l2x0_saved_regs.prefetch_ctrl =
+		readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+}
+
 static void l2x0_resume(void)
 {
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
@@ -821,6 +830,18 @@ static void aurora_resume(void)
 	}
 }
 
+static void tauros3_resume(void)
+{
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+		writel_relaxed(l2x0_saved_regs.aux2_ctrl,
+			       l2x0_base + TAUROS3_AUX2_CTRL);
+		writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+			       l2x0_base + L2X0_PREFETCH_CTRL);
+	}
+
+	l2x0_resume();
+}
+
 static void __init aurora_broadcast_l2_commands(void)
 {
 	__u32 u;
@@ -906,6 +927,15 @@ static const struct l2x0_of_data aurora_no_outer_data = {
 	},
 };
 
+static const struct l2x0_of_data tauros3_data = {
+	.setup = NULL,
+	.save  = tauros3_save,
+	/* Tauros3 broadcasts L1 cache operations to L2 */
+	.outer_cache = {
+		.resume      = tauros3_resume,
+	},
+};
+
 static const struct l2x0_of_data bcm_l2x0_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -922,17 +952,20 @@ static const struct l2x0_of_data bcm_l2x0_data = {
 };
 
 static const struct of_device_id l2x0_ids[] __initconst = {
+	{ .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
+	  .data = (void *)&bcm_l2x0_data},
+	{ .compatible = "brcm,bcm11351-a2-pl310-cache",
+	  .data = (void *)&bcm_l2x0_data},
+	{ .compatible = "marvell,aurora-outer-cache",
+	  .data = (void *)&aurora_with_outer_data},
+	{ .compatible = "marvell,aurora-system-cache",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,tauros3-cache",
+	  .data = (void *)&tauros3_data },
+	/* keep ARM compatibles below non-ARM derivates */
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
-	{ .compatible = "marvell,aurora-system-cache",
-	  .data = (void *)&aurora_no_outer_data},
-	{ .compatible = "marvell,aurora-outer-cache",
-	  .data = (void *)&aurora_with_outer_data},
-	{ .compatible = "brcm,bcm11351-a2-pl310-cache",
-	  .data = (void *)&bcm_l2x0_data},
-	{ .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
-	  .data = (void *)&bcm_l2x0_data},
 	{}
 };
 
diff --git a/arch/arm/mm/cache-tauros3.h b/arch/arm/mm/cache-tauros3.h
new file mode 100644
index 0000000..02c0a97
--- /dev/null
+++ b/arch/arm/mm/cache-tauros3.h
@@ -0,0 +1,41 @@
+/*
+ * Marvell Tauros3 cache controller includes
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_HARDWARE_TAUROS3_H
+#define __ASM_ARM_HARDWARE_TAUROS3_H
+
+/*
+ * Marvell Tauros3 L2CC is compatible with PL310 r0p0
+ * but with PREFETCH_CTRL (r2p0) and an additional event counter.
+ * Also, there is AUX2_CTRL for some Marvell specific control.
+ */
+
+#define TAUROS3_EVENT_CNT2_CFG		0x224
+#define TAUROS3_EVENT_CNT2_VAL		0x228
+#define TAUROS3_INV_ALL			0x780
+#define TAUROS3_CLEAN_ALL		0x784
+#define TAUROS3_AUX2_CTRL		0x820
+
+/* Registers shifts and masks */
+#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN	(1 << 2)
+
+#endif
-- 
1.7.10.4

[PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

This adds very basic device tree files for the Marvell Armada 1500 SoC
(Berlin BG2) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
device comprising the Armada 1500 SoC above.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
---
Changelog:
v1->v2:
- add "arm,pl310-cache" compatible to l2cc (Suggested by Mark Rutland)
- replace 88DE3xxx numbering with SoC variant name
  (Requested by Jisheng Zhang)
RCFv2->v1:
- switch to (soon to be) correct "marvell,pj4b" cpu compatible
- reference fixed-clock for uarts instead of hard-coded clock-frequency
- disable timers except two for clksrc and clkevt
RFCv1->RFCv2:
- add binding documentation (Reported by Jason Cooper)
- change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
- add copyright reference
- adapt compatibles to mach-berlin instead of mach-mvebu

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Rob Landley <rob@landley.net>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
 arch/arm/boot/dts/Makefile                         |    2 +
 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
 arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
 4 files changed, 282 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
 create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
 create mode 100644 arch/arm/boot/dts/berlin2.dtsi

diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
new file mode 100644
index 0000000..737afa5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -0,0 +1,24 @@
+Marvell Berlin SoC Family Device Tree Bindings
+---------------------------------------------------------------
+
+Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
+shall have the following properties:
+
+* Required root node properties:
+compatible: must contain "marvell,berlin"
+
+In addition, the above compatible shall be extended with the specific
+SoC and board used. Currently known SoC compatibles are:
+    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
+    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
+    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
+    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)
+
+* Example:
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
+
+	...
+}
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..c9c1a6c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -46,6 +46,8 @@ dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \
 	bcm28155-ap.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += \
+	berlin2-sony-nsz-gs7.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
 	da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
new file mode 100644
index 0000000..c72bfd4
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Sony NSZ-GS7
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "berlin2.dtsi"
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>; /* 1 GB */
+	};
+};
+
+&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
new file mode 100644
index 0000000..56a1af2
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -0,0 +1,227 @@
+/*
+ * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Marvell Armada 1500 (BG2) SoC";
+	compatible = "marvell,berlin2", "marvell,berlin";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <1>;
+		};
+	};
+
+	clocks {
+		smclk: sysmgr-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
+		cfgclk: cfg-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+		};
+
+		sysclk: system-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <400000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+
+		ranges = <0 0xf7000000 0x1000000>;
+
+		l2: l2-cache-controller@ac0000 {
+			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
+			reg = <0xac0000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		gic: interrupt-controller@ad1000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		local-timer@ad0600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xad0600 0x20>;
+			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+		};
+
+		apb@e80000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xe80000 0x10000>;
+			interrupt-parent = <&aic>;
+
+			timer0: timer@2c00 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c00 0x14>;
+				interrupts = <8>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer1: timer@2c14 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c14 0x14>;
+				interrupts = <9>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer2: timer@2c28 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c28 0x14>;
+				interrupts = <10>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer3: timer@2c3c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c3c 0x14>;
+				interrupts = <11>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer4: timer@2c50 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c50 0x14>;
+				interrupts = <12>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer5: timer@2c64 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c64 0x14>;
+				interrupts = <13>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer6: timer@2c78 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c78 0x14>;
+				interrupts = <14>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer7: timer@2c8c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c8c 0x14>;
+				interrupts = <15>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			aic: interrupt-controller@3000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0x3000 0xc00>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		apb@fc0000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xfc0000 0x10000>;
+			interrupt-parent = <&sic>;
+
+			uart0: serial@9000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x9000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <8>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart1: serial@a000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xa000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <9>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart2: serial@b000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xb000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <10>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			sic: interrupt-controller@e000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0xe000 0x400>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
-- 
1.7.10.4

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Kumar Gala]

On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:

> This adds very basic device tree files for the Marvell Armada 1500 SoC
> (Berlin BG2) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
> nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
> uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
> device comprising the Armada 1500 SoC above.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Reviewed-by: Jason Cooper <jason@lakedaemon.net>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
> ---
> Changelog:
> v1->v2:
> - add "arm,pl310-cache" compatible to l2cc (Suggested by Mark Rutland)
> - replace 88DE3xxx numbering with SoC variant name
>  (Requested by Jisheng Zhang)
> RCFv2->v1:
> - switch to (soon to be) correct "marvell,pj4b" cpu compatible
> - reference fixed-clock for uarts instead of hard-coded clock-frequency
> - disable timers except two for clksrc and clkevt
> RFCv1->RFCv2:
> - add binding documentation (Reported by Jason Cooper)
> - change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
> - add copyright reference
> - adapt compatibles to mach-berlin instead of mach-mvebu
> 
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: Rob Landley <rob@landley.net>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: devicetree@vger.kernel.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
> arch/arm/boot/dts/Makefile                         |    2 +
> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
> arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
> 4 files changed, 282 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
> create mode 100644 arch/arm/boot/dts/berlin2.dtsi

Haven't we been trying to go away from non-prefixed dts/dtsi?

So should these be something like marvell-berlin2-...

- k


-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Jason Cooper]

On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
...
> > .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
> > arch/arm/boot/dts/Makefile                         |    2 +
> > arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
> > arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
> > 4 files changed, 282 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
> > create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
> > create mode 100644 arch/arm/boot/dts/berlin2.dtsi
> 
> Haven't we been trying to go away from non-prefixed dts/dtsi?

hmmm, this is the first I've heard of that.  Although, your proposal
(in another thread) makes more sense now.  :)

> So should these be something like marvell-berlin2-...

I don't recall this being brought up at the summit, nor in Grant's
report.  I do need to give it a more careful read this weekend, though.
Perhaps I missed something.

thx,

Jason.

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Kumar Gala]

On Nov 8, 2013, at 10:57 AM, Jason Cooper wrote:

> On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
>> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
> ...
>>> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
>>> arch/arm/boot/dts/Makefile                         |    2 +
>>> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
>>> arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
>>> 4 files changed, 282 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
>>> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
>>> create mode 100644 arch/arm/boot/dts/berlin2.dtsi
>> 
>> Haven't we been trying to go away from non-prefixed dts/dtsi?
> 
> hmmm, this is the first I've heard of that.  Although, your proposal
> (in another thread) makes more sense now.  :)
> 
>> So should these be something like marvell-berlin2-...
> 
> I don't recall this being brought up at the summit, nor in Grant's
> report.  I do need to give it a more careful read this weekend, though.
> Perhaps I missed something.

This was based on review comments Olof gave when we pushed some .dts files for MSM/APQ Qualcomm Technologies soc/boards.

- k

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Jason Cooper]

On Fri, Nov 08, 2013 at 12:06:26PM -0600, Kumar Gala wrote:
> 
> On Nov 8, 2013, at 10:57 AM, Jason Cooper wrote:
> 
> > On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
> >> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
> > ...
> >>> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
> >>> arch/arm/boot/dts/Makefile                         |    2 +
> >>> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
> >>> arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
> >>> 4 files changed, 282 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
> >>> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
> >>> create mode 100644 arch/arm/boot/dts/berlin2.dtsi
> >> 
> >> Haven't we been trying to go away from non-prefixed dts/dtsi?
> > 
> > hmmm, this is the first I've heard of that.  Although, your proposal
> > (in another thread) makes more sense now.  :)
> > 
> >> So should these be something like marvell-berlin2-...
> > 
> > I don't recall this being brought up at the summit, nor in Grant's
> > report.  I do need to give it a more careful read this weekend, though.
> > Perhaps I missed something.
> 
> This was based on review comments Olof gave when we pushed some .dts
> files for MSM/APQ Qualcomm Technologies soc/boards.

As Andrew Lunn mentioned to me earlier, we should consider the fact that
the dts file names are being used by Debian's flash-kernel.  Oh no!
Another ABI! ;-)

Personally, I think dtc should be using the board compatible string, and
naming the resultant dtbs the same, eg

$ dtc kirkwood-dreamplug.dts
globalscale,dreamplug-003-ds2001.dtb

This would free us up to rename the dts files as needed.  dtb filenames
would be guaranteed unique and consistent.  It would also allow us to
catch inadvertent compatible string collisions earlier.

thx,

Jason.

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Olof Johansson]

On Fri, Nov 8, 2013 at 10:24 AM, Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org> wrote:
> On Fri, Nov 08, 2013 at 12:06:26PM -0600, Kumar Gala wrote:
>>
>> On Nov 8, 2013, at 10:57 AM, Jason Cooper wrote:
>>
>> > On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
>> >> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
>> > ...
>> >>> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
>> >>> arch/arm/boot/dts/Makefile                         |    2 +
>> >>> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
>> >>> arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
>> >>> 4 files changed, 282 insertions(+)
>> >>> create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> >>> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
>> >>> create mode 100644 arch/arm/boot/dts/berlin2.dtsi
>> >>
>> >> Haven't we been trying to go away from non-prefixed dts/dtsi?
>> >
>> > hmmm, this is the first I've heard of that.  Although, your proposal
>> > (in another thread) makes more sense now.  :)
>> >
>> >> So should these be something like marvell-berlin2-...
>> >
>> > I don't recall this being brought up at the summit, nor in Grant's
>> > report.  I do need to give it a more careful read this weekend, though.
>> > Perhaps I missed something.
>>
>> This was based on review comments Olof gave when we pushed some .dts
>> files for MSM/APQ Qualcomm Technologies soc/boards.
>
> As Andrew Lunn mentioned to me earlier, we should consider the fact that
> the dts file names are being used by Debian's flash-kernel.  Oh no!
> Another ABI! ;-)

Yes, the names are mostly stable. ST-Ericsson renamed their dts files
and it caused some pain, some build environments have them hardcoded,
etc.

Still, it is a good idea to start adding new ones using family or
vendor prefixes, so they are easier to group. Please keep that in mind
on new ones too, Jason -- I don't think I've discussed with you in the
past. :-)


-Olof
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Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

On 11/08/2013 08:14 PM, Olof Johansson wrote:
> On Fri, Nov 8, 2013 at 10:24 AM, Jason Cooper <jason@lakedaemon.net> wrote:
>> On Fri, Nov 08, 2013 at 12:06:26PM -0600, Kumar Gala wrote:
>>> On Nov 8, 2013, at 10:57 AM, Jason Cooper wrote:
>>>> On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
>>>>> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
>>>> ...
>>>>>> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
>>>>>> arch/arm/boot/dts/Makefile                         |    2 +
>>>>>> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
>>>>>> arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
>>>>>> 4 files changed, 282 insertions(+)
>>>>>> create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
>>>>>> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
>>>>>> create mode 100644 arch/arm/boot/dts/berlin2.dtsi
>>>>>
>>>>> Haven't we been trying to go away from non-prefixed dts/dtsi?
>>>>
>>>> hmmm, this is the first I've heard of that.  Although, your proposal
>>>> (in another thread) makes more sense now.  :)
>>>>
>>>>> So should these be something like marvell-berlin2-...
>>>>
>>>> I don't recall this being brought up at the summit, nor in Grant's
>>>> report.  I do need to give it a more careful read this weekend, though.
>>>> Perhaps I missed something.
>>>
>>> This was based on review comments Olof gave when we pushed some .dts
>>> files for MSM/APQ Qualcomm Technologies soc/boards.
>>
>> As Andrew Lunn mentioned to me earlier, we should consider the fact that
>> the dts file names are being used by Debian's flash-kernel.  Oh no!
>> Another ABI! ;-)
>
> Yes, the names are mostly stable. ST-Ericsson renamed their dts files
> and it caused some pain, some build environments have them hardcoded,
> etc.

Ok, I was just going to ask, if we should stich some rename-patches for
mvebu SoCs.. but the above answers that.

Sebastian

> Still, it is a good idea to start adding new ones using family or
> vendor prefixes, so they are easier to group. Please keep that in mind
> on new ones too, Jason -- I don't think I've discussed with you in the
> past. :-)

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Olof Johansson]

On Fri, Nov 8, 2013 at 11:17 AM, Sebastian Hesselbarth
<sebastian.hesselbarth@gmail.com> wrote:
> On 11/08/2013 08:14 PM, Olof Johansson wrote:
>>
>> On Fri, Nov 8, 2013 at 10:24 AM, Jason Cooper <jason@lakedaemon.net>
>> wrote:
>>>
>>> On Fri, Nov 08, 2013 at 12:06:26PM -0600, Kumar Gala wrote:
>>>>
>>>> On Nov 8, 2013, at 10:57 AM, Jason Cooper wrote:
>>>>>
>>>>> On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
>>>>>>
>>>>>> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
>>>>>
>>>>> ...
>>>>>>>
>>>>>>> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
>>>>>>> arch/arm/boot/dts/Makefile                         |    2 +
>>>>>>> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
>>>>>>> arch/arm/boot/dts/berlin2.dtsi                     |  227
>>>>>>> ++++++++++++++++++++
>>>>>>> 4 files changed, 282 insertions(+)
>>>>>>> create mode 100644
>>>>>>> Documentation/devicetree/bindings/arm/marvell,berlin.txt
>>>>>>> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
>>>>>>> create mode 100644 arch/arm/boot/dts/berlin2.dtsi
>>>>>>
>>>>>>
>>>>>> Haven't we been trying to go away from non-prefixed dts/dtsi?
>>>>>
>>>>>
>>>>> hmmm, this is the first I've heard of that.  Although, your proposal
>>>>> (in another thread) makes more sense now.  :)
>>>>>
>>>>>> So should these be something like marvell-berlin2-...
>>>>>
>>>>>
>>>>> I don't recall this being brought up at the summit, nor in Grant's
>>>>> report.  I do need to give it a more careful read this weekend, though.
>>>>> Perhaps I missed something.
>>>>
>>>>
>>>> This was based on review comments Olof gave when we pushed some .dts
>>>> files for MSM/APQ Qualcomm Technologies soc/boards.
>>>
>>>
>>> As Andrew Lunn mentioned to me earlier, we should consider the fact that
>>> the dts file names are being used by Debian's flash-kernel.  Oh no!
>>> Another ABI! ;-)
>>
>>
>> Yes, the names are mostly stable. ST-Ericsson renamed their dts files
>> and it caused some pain, some build environments have them hardcoded,
>> etc.
>
>
> Ok, I was just going to ask, if we should stich some rename-patches for
> mvebu SoCs.. but the above answers that.

For those that you think are in limited use, please do (the whole
stable ABI argument about no users means no breakage), but for others
we might have to be more careful.

It's really more about the name of the generated dtb than the dts
though, but still.


-Olof

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Jason Cooper]

On Fri, Nov 08, 2013 at 11:14:07AM -0800, Olof Johansson wrote:
> On Fri, Nov 8, 2013 at 10:24 AM, Jason Cooper <jason@lakedaemon.net> wrote:
> > On Fri, Nov 08, 2013 at 12:06:26PM -0600, Kumar Gala wrote:
> >>
> >> On Nov 8, 2013, at 10:57 AM, Jason Cooper wrote:
> >>
> >> > On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
> >> >> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
> >> > ...
> >> >>> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
> >> >>> arch/arm/boot/dts/Makefile                         |    2 +
> >> >>> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
> >> >>> arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
> >> >>> 4 files changed, 282 insertions(+)
> >> >>> create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
> >> >>> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
> >> >>> create mode 100644 arch/arm/boot/dts/berlin2.dtsi
> >> >>
> >> >> Haven't we been trying to go away from non-prefixed dts/dtsi?
> >> >
> >> > hmmm, this is the first I've heard of that.  Although, your proposal
> >> > (in another thread) makes more sense now.  :)
> >> >
> >> >> So should these be something like marvell-berlin2-...
> >> >
> >> > I don't recall this being brought up at the summit, nor in Grant's
> >> > report.  I do need to give it a more careful read this weekend, though.
> >> > Perhaps I missed something.
> >>
> >> This was based on review comments Olof gave when we pushed some .dts
> >> files for MSM/APQ Qualcomm Technologies soc/boards.
> >
> > As Andrew Lunn mentioned to me earlier, we should consider the fact that
> > the dts file names are being used by Debian's flash-kernel.  Oh no!
> > Another ABI! ;-)
> 
> Yes, the names are mostly stable. ST-Ericsson renamed their dts files
> and it caused some pain, some build environments have them hardcoded,
> etc.
> 
> Still, it is a good idea to start adding new ones using family or
> vendor prefixes, so they are easier to group. Please keep that in mind
> on new ones too, Jason -- I don't think I've discussed with you in the
> past. :-)

Nope, I definitely missed that if you did ;-)  Will do in the future.

Perhaps now is the time to consider separating the dts filename from the
dtb filename?  I'm warming up to my idea of globalscale,mirabox.dtb...

thx,

Jason.

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Olof Johansson]

On Fri, Nov 8, 2013 at 11:30 AM, Jason Cooper <jason@lakedaemon.net> wrote:
> On Fri, Nov 08, 2013 at 11:14:07AM -0800, Olof Johansson wrote:
>> On Fri, Nov 8, 2013 at 10:24 AM, Jason Cooper <jason@lakedaemon.net> wrote:
>> > On Fri, Nov 08, 2013 at 12:06:26PM -0600, Kumar Gala wrote:
>> >>
>> >> On Nov 8, 2013, at 10:57 AM, Jason Cooper wrote:
>> >>
>> >> > On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
>> >> >> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
>> >> > ...
>> >> >>> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
>> >> >>> arch/arm/boot/dts/Makefile                         |    2 +
>> >> >>> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
>> >> >>> arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
>> >> >>> 4 files changed, 282 insertions(+)
>> >> >>> create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
>> >> >>> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
>> >> >>> create mode 100644 arch/arm/boot/dts/berlin2.dtsi
>> >> >>
>> >> >> Haven't we been trying to go away from non-prefixed dts/dtsi?
>> >> >
>> >> > hmmm, this is the first I've heard of that.  Although, your proposal
>> >> > (in another thread) makes more sense now.  :)
>> >> >
>> >> >> So should these be something like marvell-berlin2-...
>> >> >
>> >> > I don't recall this being brought up at the summit, nor in Grant's
>> >> > report.  I do need to give it a more careful read this weekend, though.
>> >> > Perhaps I missed something.
>> >>
>> >> This was based on review comments Olof gave when we pushed some .dts
>> >> files for MSM/APQ Qualcomm Technologies soc/boards.
>> >
>> > As Andrew Lunn mentioned to me earlier, we should consider the fact that
>> > the dts file names are being used by Debian's flash-kernel.  Oh no!
>> > Another ABI! ;-)
>>
>> Yes, the names are mostly stable. ST-Ericsson renamed their dts files
>> and it caused some pain, some build environments have them hardcoded,
>> etc.
>>
>> Still, it is a good idea to start adding new ones using family or
>> vendor prefixes, so they are easier to group. Please keep that in mind
>> on new ones too, Jason -- I don't think I've discussed with you in the
>> past. :-)
>
> Nope, I definitely missed that if you did ;-)  Will do in the future.
>
> Perhaps now is the time to consider separating the dts filename from the
> dtb filename?  I'm warming up to my idea of globalscale,mirabox.dtb...

Having a "dtb-install" make target that sets those up as softlinks
could be a good idea, at least. I'm not sold on using them as
filenames myself though.


-Olof

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Jason Cooper]

On Fri, Nov 08, 2013 at 12:10:27PM -0800, Olof Johansson wrote:
> On Fri, Nov 8, 2013 at 11:30 AM, Jason Cooper <jason@lakedaemon.net> wrote:
> > On Fri, Nov 08, 2013 at 11:14:07AM -0800, Olof Johansson wrote:
> >> On Fri, Nov 8, 2013 at 10:24 AM, Jason Cooper <jason@lakedaemon.net> wrote:
> >> > On Fri, Nov 08, 2013 at 12:06:26PM -0600, Kumar Gala wrote:
> >> >>
> >> >> On Nov 8, 2013, at 10:57 AM, Jason Cooper wrote:
> >> >>
> >> >> > On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
> >> >> >> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
> >> >> > ...
> >> >> >>> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
> >> >> >>> arch/arm/boot/dts/Makefile                         |    2 +
> >> >> >>> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
> >> >> >>> arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
> >> >> >>> 4 files changed, 282 insertions(+)
> >> >> >>> create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
> >> >> >>> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
> >> >> >>> create mode 100644 arch/arm/boot/dts/berlin2.dtsi
> >> >> >>
> >> >> >> Haven't we been trying to go away from non-prefixed dts/dtsi?
> >> >> >
> >> >> > hmmm, this is the first I've heard of that.  Although, your proposal
> >> >> > (in another thread) makes more sense now.  :)
> >> >> >
> >> >> >> So should these be something like marvell-berlin2-...
> >> >> >
> >> >> > I don't recall this being brought up at the summit, nor in Grant's
> >> >> > report.  I do need to give it a more careful read this weekend, though.
> >> >> > Perhaps I missed something.
> >> >>
> >> >> This was based on review comments Olof gave when we pushed some .dts
> >> >> files for MSM/APQ Qualcomm Technologies soc/boards.
> >> >
> >> > As Andrew Lunn mentioned to me earlier, we should consider the fact that
> >> > the dts file names are being used by Debian's flash-kernel.  Oh no!
> >> > Another ABI! ;-)
> >>
> >> Yes, the names are mostly stable. ST-Ericsson renamed their dts files
> >> and it caused some pain, some build environments have them hardcoded,
> >> etc.
> >>
> >> Still, it is a good idea to start adding new ones using family or
> >> vendor prefixes, so they are easier to group. Please keep that in mind
> >> on new ones too, Jason -- I don't think I've discussed with you in the
> >> past. :-)
> >
> > Nope, I definitely missed that if you did ;-)  Will do in the future.
> >
> > Perhaps now is the time to consider separating the dts filename from the
> > dtb filename?  I'm warming up to my idea of globalscale,mirabox.dtb...
> 
> Having a "dtb-install" make target that sets those up as softlinks
> could be a good idea, at least.

oooh, I like that.  Something like

$ dtc -L -o kirkwood-dreamplug.dtb kirkwood-dreamplug.dts
$ ls
...
globalscale,dreamplug.dtb -> kirkwood-dreamplug.dtb
...
kirkwood-dreamplug.dtb
...
$

Otherwise the build system would have to learn to parse dts/dtbs...

> I'm not sold on using them as filenames myself though.

fair enough.

thx,

Jason.

Re: [PATCH v3 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

On 11/08/2013 07:24 PM, Jason Cooper wrote:
> On Fri, Nov 08, 2013 at 12:06:26PM -0600, Kumar Gala wrote:
>> On Nov 8, 2013, at 10:57 AM, Jason Cooper wrote:
>>> On Fri, Nov 08, 2013 at 10:13:19AM -0600, Kumar Gala wrote:
>>>> On Nov 5, 2013, at 8:28 AM, Sebastian Hesselbarth wrote:
>>> ...
>>>>> .../devicetree/bindings/arm/marvell,berlin.txt     |   24 +++
>>>>> arch/arm/boot/dts/Makefile                         |    2 +
>>>>> arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts         |   29 +++
>>>>> arch/arm/boot/dts/berlin2.dtsi                     |  227 ++++++++++++++++++++
>>>>> 4 files changed, 282 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
>>>>> create mode 100644 arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
>>>>> create mode 100644 arch/arm/boot/dts/berlin2.dtsi
>>>>
>>>> Haven't we been trying to go away from non-prefixed dts/dtsi?
>>>
>>> hmmm, this is the first I've heard of that.  Although, your proposal
>>> (in another thread) makes more sense now.  :)
>>>
>>>> So should these be something like marvell-berlin2-...
>>>
>>> I don't recall this being brought up at the summit, nor in Grant's
>>> report.  I do need to give it a more careful read this weekend, though.
>>> Perhaps I missed something.
>>
>> This was based on review comments Olof gave when we pushed some .dts
>> files for MSM/APQ Qualcomm Technologies soc/boards.
>
> As Andrew Lunn mentioned to me earlier, we should consider the fact that
> the dts file names are being used by Debian's flash-kernel.  Oh no!
> Another ABI! ;-)
>
> Personally, I think dtc should be using the board compatible string, and
> naming the resultant dtbs the same, eg
>
> $ dtc kirkwood-dreamplug.dts
> globalscale,dreamplug-003-ds2001.dtb
>
> This would free us up to rename the dts files as needed.  dtb filenames
> would be guaranteed unique and consistent.  It would also allow us to
> catch inadvertent compatible string collisions earlier.

Besides the dtc output scheme, I also like the idea of a more consistent
dts/dtsi file naming. What about the scheme below, which also allows us
to get rid of vendor-soc-vendor-board.dts naming (which already leads to
quite long names):

(a) vendor,soc.dtsi and vendor,board.dts

or if dtc/cpp doesn't like ',' in includes

(b) vendor-soc.dtsi and vendor-board.dts

for this patch, that would give us

marvell,berlin2.dtsi and sony,nsz-gs7.dts.

If you propose a scheme we should follow, I'd be happy to apply that
first on this patch set. If we have a dtc output scheme, too, that
scheme can be more like best practice instead of a hard rule.

Sebastian

[PATCH v3 8/9] ARM: add Armada 1500-mini and Chromecast device tree files

[Sebastian Hesselbarth]

This adds very basic device tree files for the Marvell Armada
1500-mini SoC (Berlin BG2CD) and the Google Chromecast. Currently,
SoC only has nodes for cpu, some clocks, l2 cache controller, local
timer, apb timers, uart, and interrupt controllers.
The Google Chromecast is a consumer device comprising the Armada
1500-mini SoC above.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Changelog:
v3:
- initial patch

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Rob Landley <rob@landley.net>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/boot/dts/Makefile                        |    3 +-
 arch/arm/boot/dts/berlin2cd-google-chromecast.dts |   29 +++
 arch/arm/boot/dts/berlin2cd.dtsi                  |  212 +++++++++++++++++++++
 3 files changed, 243 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/berlin2cd-google-chromecast.dts
 create mode 100644 arch/arm/boot/dts/berlin2cd.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c9c1a6c..dac733f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -47,7 +47,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \
 	bcm28155-ap.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
-	berlin2-sony-nsz-gs7.dtb
+	berlin2-sony-nsz-gs7.dtb \
+	berlin2cd-google-chromecast.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
 	da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
new file mode 100644
index 0000000..bcd81ff
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Google Chromecast
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "berlin2cd.dtsi"
+
+/ {
+	model = "Google Chromecast";
+	compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+};
+
+&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
new file mode 100644
index 0000000..40d1bed
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -0,0 +1,212 @@
+/*
+ * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Marvell Armada 1500-mini (BG2CD) SoC";
+	compatible = "marvell,berlin2cd", "marvell,berlin";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		smclk: sysmgr-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
+		cfgclk: cfg-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <75000000>;
+		};
+
+		sysclk: system-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <300000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+
+		ranges = <0 0xf7000000 0x1000000>;
+
+		l2: l2-cache-controller@ac0000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xac0000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+			arm,prefetch-ctrl = <0x70000007>;
+			arm,pwr-ctrl = <0x3>;
+		};
+
+		gic: interrupt-controller@ad1000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		local-timer@ad0600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xad0600 0x20>;
+			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+		};
+
+		apb@e80000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xe80000 0x10000>;
+			interrupt-parent = <&aic>;
+
+			timer0: timer@2c00 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c00 0x14>;
+				interrupts = <8>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer1: timer@2c14 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c14 0x14>;
+				interrupts = <9>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer2: timer@2c28 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c28 0x14>;
+				interrupts = <10>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer3: timer@2c3c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c3c 0x14>;
+				interrupts = <11>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer4: timer@2c50 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c50 0x14>;
+				interrupts = <12>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer5: timer@2c64 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c64 0x14>;
+				interrupts = <13>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer6: timer@2c78 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c78 0x14>;
+				interrupts = <14>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer7: timer@2c8c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c8c 0x14>;
+				interrupts = <15>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			aic: interrupt-controller@3000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0x3000 0xc00>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		apb@fc0000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xfc0000 0x10000>;
+			interrupt-parent = <&sic>;
+
+			uart0: serial@9000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x9000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <8>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart1: serial@a000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xa000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <9>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			sic: interrupt-controller@e000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0xe000 0x400>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
-- 
1.7.10.4

Re: [PATCH v3 8/9] ARM: add Armada 1500-mini and Chromecast device tree files

[Jisheng Zhang]

On Tue, 5 Nov 2013 06:28:42 -0800
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> wrote:

> This adds very basic device tree files for the Marvell Armada
> 1500-mini SoC (Berlin BG2CD) and the Google Chromecast. Currently,
> SoC only has nodes for cpu, some clocks, l2 cache controller, local
> timer, apb timers, uart, and interrupt controllers.
> The Google Chromecast is a consumer device comprising the Armada
> 1500-mini SoC above.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> ---
> Changelog:
> v3:
> - initial patch
> 
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stephen Warren <swarren@wwwdotorg.org>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: Rob Landley <rob@landley.net>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: devicetree@vger.kernel.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  arch/arm/boot/dts/Makefile                        |    3 +-
>  arch/arm/boot/dts/berlin2cd-google-chromecast.dts |   29 +++
>  arch/arm/boot/dts/berlin2cd.dtsi                  |  212
> +++++++++++++++++++++ 3 files changed, 243 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/berlin2cd-google-chromecast.dts
>  create mode 100644 arch/arm/boot/dts/berlin2cd.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index c9c1a6c..dac733f 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -47,7 +47,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
>  dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \
>         bcm28155-ap.dtb
>  dtb-$(CONFIG_ARCH_BERLIN) += \
> -       berlin2-sony-nsz-gs7.dtb
> +       berlin2-sony-nsz-gs7.dtb \
> +       berlin2cd-google-chromecast.dtb
>  dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
>         da850-evm.dtb
>  dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
> diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
> b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts new file mode 100644
> index 0000000..bcd81ff
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
> @@ -0,0 +1,29 @@
> +/*
> + * Device Tree file for Google Chromecast
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include "berlin2cd.dtsi"
> +
> +/ {
> +       model = "Google Chromecast";
> +       compatible = "google,chromecast", "marvell,berlin2cd",
> "marvell,berlin"; +
> +       chosen {
> +               bootargs = "console=ttyS0,115200 earlyprintk";
> +       };
> +
> +       memory {
> +               device_type = "memory";
> +               reg = <0x00000000 0x20000000>; /* 512 MB */
> +       };
> +};
> +
> +&uart0 { status = "okay"; };
> diff --git a/arch/arm/boot/dts/berlin2cd.dtsi
> b/arch/arm/boot/dts/berlin2cd.dtsi new file mode 100644
> index 0000000..40d1bed
> --- /dev/null
> +++ b/arch/arm/boot/dts/berlin2cd.dtsi
> @@ -0,0 +1,212 @@
> +/*
> + * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
> + *
> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> + *
> + * based on GPL'ed 2.6 kernel sources
> + *  (c) Marvell International Ltd.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include "skeleton.dtsi"
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       model = "Marvell Armada 1500-mini (BG2CD) SoC";
> +       compatible = "marvell,berlin2cd", "marvell,berlin";
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu@0 {
> +                       compatible = "arm,cortex-a9";
> +                       device_type = "cpu";
> +                       next-level-cache = <&l2>;
> +                       reg = <0>;
> +               };
> +       };
> +
> +       clocks {
> +               smclk: sysmgr-clock {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <25000000>;
> +               };
> +
> +               cfgclk: cfg-clock {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <75000000>;
> +               };
> +
> +               sysclk: system-clock {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <300000000>;
> +               };
> +       };
> +
> +       soc {
> +               compatible = "simple-bus";
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               interrupt-parent = <&gic>;
> +
> +               ranges = <0 0xf7000000 0x1000000>;
> +
> +               l2: l2-cache-controller@ac0000 {
> +                       compatible = "arm,pl310-cache";
> +                       reg = <0xac0000 0x1000>;
> +                       cache-unified;
> +                       cache-level = <2>;
> +                       arm,prefetch-ctrl = <0x70000007>;
> +                       arm,pwr-ctrl = <0x3>;
These two setting depend on the following prefetch and power control support patch.
We have it in our internal tree for a long time.

http://lists.infradead.org/pipermail/linux-arm-kernel/2013-November/209700.html
> +               };
> +
> +               gic: interrupt-controller@ad1000 {
> +                       compatible = "arm,cortex-a9-gic";
> +                       reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <3>;
> +               };
> +
> +               local-timer@ad0600 {
> +                       compatible = "arm,cortex-a9-twd-timer";
> +                       reg = <0xad0600 0x20>;
> +                       interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&sysclk>;
> +               };
> +
> +               apb@e80000 {
> +                       compatible = "simple-bus";
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       ranges = <0 0xe80000 0x10000>;
> +                       interrupt-parent = <&aic>;
> +
> +                       timer0: timer@2c00 {
> +                               compatible = "snps,dw-apb-timer";
snps,dw-apb-timer-osc?
> +                               reg = <0x2c00 0x14>;
> +                               interrupts = <8>;
> +                               clocks = <&cfgclk>;
> +                               clock-names = "timer";
> +                               status = "okay";
> +                       };
> +
> +                       timer1: timer@2c14 {
> +                               compatible = "snps,dw-apb-timer";
ditto for the remaining
> +                               reg = <0x2c14 0x14>;
> +                               interrupts = <9>;
> +                               clocks = <&cfgclk>;
> +                               clock-names = "timer";
> +                               status = "okay";
> +                       };
> +
> +                       timer2: timer@2c28 {
> +                               compatible = "snps,dw-apb-timer";
> +                               reg = <0x2c28 0x14>;
> +                               interrupts = <10>;
> +                               clocks = <&cfgclk>;
> +                               clock-names = "timer";
> +                               status = "disabled";
> +                       };
> +
> +                       timer3: timer@2c3c {
> +                               compatible = "snps,dw-apb-timer";
> +                               reg = <0x2c3c 0x14>;
> +                               interrupts = <11>;
> +                               clocks = <&cfgclk>;
> +                               clock-names = "timer";
> +                               status = "disabled";
> +                       };
> +
> +                       timer4: timer@2c50 {
> +                               compatible = "snps,dw-apb-timer";
> +                               reg = <0x2c50 0x14>;
> +                               interrupts = <12>;
> +                               clocks = <&cfgclk>;
> +                               clock-names = "timer";
> +                               status = "disabled";
> +                       };
> +
> +                       timer5: timer@2c64 {
> +                               compatible = "snps,dw-apb-timer";
> +                               reg = <0x2c64 0x14>;
> +                               interrupts = <13>;
> +                               clocks = <&cfgclk>;
> +                               clock-names = "timer";
> +                               status = "disabled";
> +                       };
> +
> +                       timer6: timer@2c78 {
> +                               compatible = "snps,dw-apb-timer";
> +                               reg = <0x2c78 0x14>;
> +                               interrupts = <14>;
> +                               clocks = <&cfgclk>;
> +                               clock-names = "timer";
> +                               status = "disabled";
> +                       };
> +
> +                       timer7: timer@2c8c {
> +                               compatible = "snps,dw-apb-timer";
> +                               reg = <0x2c8c 0x14>;
> +                               interrupts = <15>;
> +                               clocks = <&cfgclk>;
> +                               clock-names = "timer";
> +                               status = "disabled";
> +                       };
> +
> +                       aic: interrupt-controller@3000 {
> +                               compatible = "snps,dw-apb-ictl";
> +                               reg = <0x3000 0xc00>;
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                               interrupt-parent = <&gic>;
> +                               interrupts = <GIC_SPI 3
> IRQ_TYPE_LEVEL_HIGH>;
> +                       };
> +               };
> +
> +               apb@fc0000 {
> +                       compatible = "simple-bus";
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       ranges = <0 0xfc0000 0x10000>;
> +                       interrupt-parent = <&sic>;
> +
> +                       uart0: serial@9000 {
> +                               compatible = "snps,dw-apb-uart";
> +                               reg = <0x9000 0x100>;
> +                               reg-shift = <2>;
> +                               reg-io-width = <1>;
> +                               interrupts = <8>;
> +                               clocks = <&smclk>;
> +                               status = "disabled";
> +                       };
> +
> +                       uart1: serial@a000 {
> +                               compatible = "snps,dw-apb-uart";
> +                               reg = <0xa000 0x100>;
> +                               reg-shift = <2>;
> +                               reg-io-width = <1>;
> +                               interrupts = <9>;
> +                               clocks = <&smclk>;
> +                               status = "disabled";
> +                       };
> +
> +                       sic: interrupt-controller@e000 {
> +                               compatible = "snps,dw-apb-ictl";
> +                               reg = <0xe000 0x400>;
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                               interrupt-parent = <&gic>;
> +                               interrupts = <GIC_SPI 15
> IRQ_TYPE_LEVEL_HIGH>;
> +                       };
> +               };
> +       };
> +};
> --
> 1.7.10.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v3 8/9] ARM: add Armada 1500-mini and Chromecast device tree files

[Sebastian Hesselbarth]

On 11/07/13 06:48, Jisheng Zhang wrote:
> On Tue, 5 Nov 2013 06:28:42 -0800
> Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> wrote:
>> This adds very basic device tree files for the Marvell Armada
>> 1500-mini SoC (Berlin BG2CD) and the Google Chromecast. Currently,
>> SoC only has nodes for cpu, some clocks, l2 cache controller, local
>> timer, apb timers, uart, and interrupt controllers.
>> The Google Chromecast is a consumer device comprising the Armada
>> 1500-mini SoC above.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> ---
[...]
>> diff --git a/arch/arm/boot/dts/berlin2cd.dtsi
>> b/arch/arm/boot/dts/berlin2cd.dtsi new file mode 100644
>> index 0000000..40d1bed
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/berlin2cd.dtsi
>> @@ -0,0 +1,212 @@
>> +/*
>> + * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
>> + *
>> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
>> + *
>> + * based on GPL'ed 2.6 kernel sources
>> + *  (c) Marvell International Ltd.
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include "skeleton.dtsi"
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +       model = "Marvell Armada 1500-mini (BG2CD) SoC";
>> +       compatible = "marvell,berlin2cd", "marvell,berlin";
>> +
>> +       cpus {
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +
>> +               cpu@0 {
>> +                       compatible = "arm,cortex-a9";
>> +                       device_type = "cpu";
>> +                       next-level-cache = <&l2>;
>> +                       reg = <0>;
>> +               };
>> +       };
>> +
[...]
>> +       soc {
>> +               compatible = "simple-bus";
>> +               #address-cells = <1>;
>> +               #size-cells = <1>;
>> +               interrupt-parent = <&gic>;
>> +
>> +               ranges = <0 0xf7000000 0x1000000>;
>> +
>> +               l2: l2-cache-controller@ac0000 {
>> +                       compatible = "arm,pl310-cache";
>> +                       reg = <0xac0000 0x1000>;
>> +                       cache-unified;
>> +                       cache-level = <2>;
>> +                       arm,prefetch-ctrl = <0x70000007>;
>> +                       arm,pwr-ctrl = <0x3>;
> These two setting depend on the following prefetch and power control support patch.
> We have it in our internal tree for a long time.
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-November/209700.html

Right, consider the above as a debug left-over. I was blindly guessing
and picked that patch and the both properties above from your tree.

Will remove them now, we can add them later when the binding has been
accepted. I will reply to that patch next, I guess arm,prefetch-ctrl
will not be accepted that way, as we try to avoid hex-bashing
properties.

I did some research on feature/property matrix for the l2x0/l310 as
there is public documentation, hope to find some time to polish the
matrix and get a patch ready.

>> +               };
>> +
>> +               gic: interrupt-controller@ad1000 {
>> +                       compatible = "arm,cortex-a9-gic";
>> +                       reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
>> +                       interrupt-controller;
>> +                       #interrupt-cells = <3>;
>> +               };
>> +
>> +               local-timer@ad0600 {
>> +                       compatible = "arm,cortex-a9-twd-timer";
>> +                       reg = <0xad0600 0x20>;
>> +                       interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&sysclk>;
>> +               };
>> +
>> +               apb@e80000 {
>> +                       compatible = "simple-bus";
>> +                       #address-cells = <1>;
>> +                       #size-cells = <1>;
>> +
>> +                       ranges = <0 0xe80000 0x10000>;
>> +                       interrupt-parent = <&aic>;
>> +
>> +                       timer0: timer@2c00 {
>> +                               compatible = "snps,dw-apb-timer";
> snps,dw-apb-timer-osc?

As stated in the cover letter, snps,dw-apb-timer-osc/-sp have been
deprecated by [1].

[1] http://www.spinics.net/lists/arm-kernel/msg277763.html

>> +                               reg = <0x2c00 0x14>;
>> +                               interrupts = <8>;
>> +                               clocks = <&cfgclk>;
>> +                               clock-names = "timer";
>> +                               status = "okay";
>> +                       };
>> +
>> +                       timer1: timer@2c14 {
>> +                               compatible = "snps,dw-apb-timer";
> ditto for the remaining

ditto.

Sebastian

[PATCH v4 0/9] ARM: Initial support for Marvell Berlin SoCs

[Sebastian Hesselbarth]

Hopefully last round of initial support patches for Marvell Berlin SoCs
before I can send the final PR for v3.14.

Compared to last version sent, this patch set has now a Reviewed-by from
Thomas Gleixner for the irqchip driver (Thanks for that!). Also, l2x0
compatibles can now be reordered alphabetically instead of by derivate
thanks to [1].

Marvell Docs have been updated to not mention Armada 1000 which has been
discontinued by Marvell and vanished from their website. The dtsi/dts file
have been renamed to vendor,name.dts[i], which is the preferred new naming
scheme.

Open issues are the never ending dw_apb_timers_of story, which I ignore
for now and hope they get in someday. Also, TWD SMP dependency and
early l2x0_of_init will be addressed at a later date. At the current
feature set of Berlin SoC, I don't see why the above issues should further
stall this patches.

I guess, all patches can go through ARM SoC tree, except Tauros3 patch
which I should submit to Russell's patch tracker?

Sebastian

[1] http://www.kernelhub.org/?msg=372182&p=2

Sebastian Hesselbarth (9):
  irqchip: add DesignWare APB ICTL interrupt controller
  MAINTAINERS: add ARM Marvell Berlin SoC
  ARM: l2x0: add Marvell Tauros3 support
  ARM: add Marvell Berlin SoC familiy to Marvell doc
  ARM: add Marvell Berlin SoCs to multi_v7_defconfig
  ARM: add Marvell Berlin UART0 lowlevel debug
  ARM: add Armada 1500 and Sony NSZ-GS7 device tree files
  ARM: add Armada 1500-mini and Chromecast device tree files
  ARM: add initial support for Marvell Berlin SoCs

 Documentation/arm/Marvell/README                   |  24 +++
 Documentation/devicetree/bindings/arm/l2cc.txt     |  23 ++-
 .../devicetree/bindings/arm/marvell,berlin.txt     |  24 +++
 .../interrupt-controller/snps,dw-apb-ictl.txt      |  32 +++
 MAINTAINERS                                        |   6 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Kconfig.debug                             |  10 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   3 +
 arch/arm/boot/dts/google,chromecast.dts            |  29 +++
 arch/arm/boot/dts/marvell,berlin2.dtsi             | 227 +++++++++++++++++++++
 arch/arm/boot/dts/marvell,berlin2cd.dtsi           | 210 +++++++++++++++++++
 arch/arm/boot/dts/sony,nsz-gs7.dts                 |  29 +++
 arch/arm/configs/multi_v7_defconfig                |   3 +
 arch/arm/include/asm/hardware/cache-l2x0.h         |   1 +
 arch/arm/mach-berlin/Kconfig                       |  29 +++
 arch/arm/mach-berlin/Makefile                      |   1 +
 arch/arm/mach-berlin/berlin.c                      |  39 ++++
 arch/arm/mm/cache-l2x0.c                           |  48 ++++-
 arch/arm/mm/cache-tauros3.h                        |  41 ++++
 drivers/irqchip/Kconfig                            |   4 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-dw-apb-ictl.c                  | 150 ++++++++++++++
 23 files changed, 918 insertions(+), 19 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
 create mode 100644 arch/arm/boot/dts/google,chromecast.dts
 create mode 100644 arch/arm/boot/dts/marvell,berlin2.dtsi
 create mode 100644 arch/arm/boot/dts/marvell,berlin2cd.dtsi
 create mode 100644 arch/arm/boot/dts/sony,nsz-gs7.dts
 create mode 100644 arch/arm/mach-berlin/Kconfig
 create mode 100644 arch/arm/mach-berlin/Makefile
 create mode 100644 arch/arm/mach-berlin/berlin.c
 create mode 100644 arch/arm/mm/cache-tauros3.h
 create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c

---
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
-- 
1.8.4.rc3

[PATCH v4 1/9] irqchip: add DesignWare APB ICTL interrupt controller

[Sebastian Hesselbarth]

This adds an irqchip driver and corresponding devicetree binding for the
secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
---
Changelog:
v2->v4:
- none
v1->v2:
- reword binding docu for reg property and add FIQ decoding note
  (Suggested by Mark Rutland)
- add cleanup on error path (Reported by Jisheng Zhang)
RFCv1->RFCv2:
- added copyright reference

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../interrupt-controller/snps,dw-apb-ictl.txt      |  32 +++++
 drivers/irqchip/Kconfig                            |   4 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-dw-apb-ictl.c                  | 150 +++++++++++++++++++++
 4 files changed, 187 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
 create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c

diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
new file mode 100644
index 0000000..4929117
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
@@ -0,0 +1,32 @@
+Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
+
+Synopsys DesignWare provides interrupt controller IP for APB known as
+dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
+APB bus, e.g. Marvell Armada 1500.
+
+Required properties:
+- compatible: shall be "snps,dw-apb-ictl"
+- reg: physical base address of the controller and length of memory mapped
+  region starting with ENABLE_LOW register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
+- interrupts: interrupt reference to primary interrupt controller
+- interrupt-parent: (optional) reference specific primary interrupt controller
+
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of low interrupts,
+- 1 maps to bit 1 of low interrupts,
+- 32 maps to bit 0 of high interrupts,
+- 33 maps to bit 1 of high interrupts,
+- (optional) fast interrupts start at 64.
+
+Example:
+	aic: interrupt-controller@3000 {
+		compatible = "snps,dw-apb-ictl";
+		reg = <0x3000 0xc00>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+	};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3792a1a..940638d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -30,6 +30,10 @@ config ARM_VIC_NR
 	  The maximum number of VICs available in the system, for
 	  power management.
 
+config DW_APB_ICTL
+	bool
+	select IRQ_DOMAIN
+
 config IMGPDC_IRQ
 	bool
 	select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c60b901..6427323 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS)			+= irq-mxs.o
 obj-$(CONFIG_ARCH_S3C24XX)		+= irq-s3c24xx.o
+obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)			+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
 obj-$(CONFIG_ARCH_MOXART)		+= irq-moxart.o
diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
new file mode 100644
index 0000000..31e231e
--- /dev/null
+++ b/drivers/irqchip/irq-dw-apb-ictl.c
@@ -0,0 +1,150 @@
+/*
+ * Synopsys DW APB ICTL irqchip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "irqchip.h"
+
+#define APB_INT_ENABLE_L	0x00
+#define APB_INT_ENABLE_H	0x04
+#define APB_INT_MASK_L		0x08
+#define APB_INT_MASK_H		0x0c
+#define APB_INT_FINALSTATUS_L	0x30
+#define APB_INT_FINALSTATUS_H	0x34
+
+static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	struct irq_chip_generic *gc = irq_get_handler_data(irq);
+	struct irq_domain *d = gc->private;
+	u32 stat;
+	int n;
+
+	chained_irq_enter(chip, desc);
+
+	for (n = 0; n < gc->num_ct; n++) {
+		stat = readl_relaxed(gc->reg_base +
+				     APB_INT_FINALSTATUS_L + 4 * n);
+		while (stat) {
+			u32 hwirq = ffs(stat) - 1;
+			generic_handle_irq(irq_find_mapping(d,
+					    gc->irq_base + hwirq + 32 * n));
+			stat &= ~(1 << hwirq);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static int __init dw_apb_ictl_init(struct device_node *np,
+				   struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	struct resource r;
+	struct irq_domain *domain;
+	struct irq_chip_generic *gc;
+	void __iomem *iobase;
+	int ret, nrirqs, irq;
+	u32 reg;
+
+	/* Map the parent interrupt for the chained handler */
+	irq = irq_of_parse_and_map(np, 0);
+	if (irq <= 0) {
+		pr_err("%s: unable to parse irq\n", np->full_name);
+		return -EINVAL;
+	}
+
+	ret = of_address_to_resource(np, 0, &r);
+	if (ret) {
+		pr_err("%s: unable to get resource\n", np->full_name);
+		return ret;
+	}
+
+	if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
+		pr_err("%s: unable to request mem region\n", np->full_name);
+		return -ENOMEM;
+	}
+
+	iobase = ioremap(r.start, resource_size(&r));
+	if (!iobase) {
+		pr_err("%s: unable to map resource\n", np->full_name);
+		ret = -ENOMEM;
+		goto err_release;
+	}
+
+	/*
+	 * DW IP can be configured to allow 2-64 irqs. We can determine
+	 * the number of irqs supported by writing into enable register
+	 * and look for bits not set, as corresponding flip-flops will
+	 * have been removed by sythesis tool.
+	 */
+
+	/* mask and enable all interrupts */
+	writel(~0, iobase + APB_INT_MASK_L);
+	writel(~0, iobase + APB_INT_MASK_H);
+	writel(~0, iobase + APB_INT_ENABLE_L);
+	writel(~0, iobase + APB_INT_ENABLE_H);
+
+	reg = readl(iobase + APB_INT_ENABLE_H);
+	if (reg)
+		nrirqs = 32 + fls(reg);
+	else
+		nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
+
+	domain = irq_domain_add_linear(np, nrirqs,
+				       &irq_generic_chip_ops, NULL);
+	if (!domain) {
+		pr_err("%s: unable to add irq domain\n", np->full_name);
+		ret = -ENOMEM;
+		goto err_unmap;
+	}
+
+	ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
+					     np->name, handle_level_irq, clr, 0,
+					     IRQ_GC_INIT_MASK_CACHE);
+	if (ret) {
+		pr_err("%s: unable to alloc irq domain gc\n", np->full_name);
+		goto err_unmap;
+	}
+
+	gc = irq_get_domain_generic_chip(domain, 0);
+	gc->private = domain;
+	gc->reg_base = iobase;
+
+	gc->chip_types[0].regs.mask = APB_INT_MASK_L;
+	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
+	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
+
+	if (nrirqs > 32) {
+		gc->chip_types[1].regs.mask = APB_INT_MASK_H;
+		gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
+		gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
+	}
+
+	irq_set_handler_data(irq, gc);
+	irq_set_chained_handler(irq, dw_apb_ictl_handler);
+
+	return 0;
+
+err_unmap:
+	iounmap(iobase);
+err_release:
+	release_mem_region(r.start, resource_size(&r));
+	return ret;
+}
+IRQCHIP_DECLARE(dw_apb_ictl,
+		"snps,dw-apb-ictl", dw_apb_ictl_init);
-- 
1.8.4.rc3

[PATCH v4 3/9] ARM: l2x0: add Marvell Tauros3 support

[Sebastian Hesselbarth]

This adds support for the Marvell Tauros3 cache controller which
is compatible with pl310 cache controller but broadcasts L1 cache
operations to L2 cache. While updating the binding documentation,
clean up the list of possible compatibles. Also reorder driver
compatibles in alphabetical order.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
---
Changelog:
v3->v4:
- reorder compatibles alphabetically (see [1])
  [1] http://www.kernelhub.org/?msg=372182&p=2
v2->v3:
- none
v1->v2:
- add tauros3 data without outer cache ops (Suggested by Jisheng Zhang)
- reorder compatibles to allow derivates to be compatible with ARM
  controllers (Suggested by Mark Rutland)

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: devicetree@vger.kernel.org 
Cc: linux-doc@vger.kernel.org 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 Documentation/devicetree/bindings/arm/l2cc.txt | 23 ++++++------
 arch/arm/include/asm/hardware/cache-l2x0.h     |  1 +
 arch/arm/mm/cache-l2x0.c                       | 48 +++++++++++++++++++++-----
 arch/arm/mm/cache-tauros3.h                    | 41 ++++++++++++++++++++++
 4 files changed, 94 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mm/cache-tauros3.h

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index c0c7626..b513cb8 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -7,20 +7,21 @@ The ARM L2 cache representation in the device tree should be done as follows:
 Required properties:
 
 - compatible : should be one of:
-	"arm,pl310-cache"
-	"arm,l220-cache"
-	"arm,l210-cache"
-	"marvell,aurora-system-cache": Marvell Controller designed to be
+  "arm,pl310-cache"
+  "arm,l220-cache"
+  "arm,l210-cache"
+  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+     offset needs to be added to the address before passing down to the L2
+     cache controller
+  "marvell,aurora-system-cache": Marvell Controller designed to be
      compatible with the ARM one, with system cache mode (meaning
      maintenance operations on L1 are broadcasted to the L2 and L2
      performs the same operation).
-	"marvell,"aurora-outer-cache: Marvell Controller designed to be
-	 compatible with the ARM one with outer cache mode.
-	"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
-	offset needs to be added to the address before passing down to the L2
-	cache controller
-	"bcm,bcm11351-a2-pl310-cache": DEPRECATED by
-	                               "brcm,bcm11351-a2-pl310-cache"
+  "marvell,aurora-outer-cache": Marvell Controller designed to be
+     compatible with the ARM one with outer cache mode.
+  "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+     with arm,pl310-cache controller.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 3b2c40b..6795ff7 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -131,6 +131,7 @@ struct l2x0_regs {
 	unsigned long prefetch_ctrl;
 	unsigned long pwr_ctrl;
 	unsigned long ctrl;
+	unsigned long aux2_ctrl;
 };
 
 extern struct l2x0_regs l2x0_saved_regs;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 447da6f..7abde2c 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "cache-tauros3.h"
 #include "cache-aurora-l2.h"
 
 #define CACHE_LINE_SIZE		32
@@ -767,6 +768,14 @@ static void aurora_save(void)
 	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 }
 
+static void __init tauros3_save(void)
+{
+	l2x0_saved_regs.aux2_ctrl =
+		readl_relaxed(l2x0_base + TAUROS3_AUX2_CTRL);
+	l2x0_saved_regs.prefetch_ctrl =
+		readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+}
+
 static void l2x0_resume(void)
 {
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
@@ -821,6 +830,18 @@ static void aurora_resume(void)
 	}
 }
 
+static void tauros3_resume(void)
+{
+	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+		writel_relaxed(l2x0_saved_regs.aux2_ctrl,
+			       l2x0_base + TAUROS3_AUX2_CTRL);
+		writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+			       l2x0_base + L2X0_PREFETCH_CTRL);
+	}
+
+	l2x0_resume();
+}
+
 static void __init aurora_broadcast_l2_commands(void)
 {
 	__u32 u;
@@ -906,6 +927,15 @@ static const struct l2x0_of_data aurora_no_outer_data = {
 	},
 };
 
+static const struct l2x0_of_data tauros3_data = {
+	.setup = NULL,
+	.save  = tauros3_save,
+	/* Tauros3 broadcasts L1 cache operations to L2 */
+	.outer_cache = {
+		.resume      = tauros3_resume,
+	},
+};
+
 static const struct l2x0_of_data bcm_l2x0_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -922,17 +952,19 @@ static const struct l2x0_of_data bcm_l2x0_data = {
 };
 
 static const struct of_device_id l2x0_ids[] __initconst = {
-	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
-	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
-	{ .compatible = "marvell,aurora-system-cache",
-	  .data = (void *)&aurora_no_outer_data},
-	{ .compatible = "marvell,aurora-outer-cache",
-	  .data = (void *)&aurora_with_outer_data},
-	{ .compatible = "brcm,bcm11351-a2-pl310-cache",
-	  .data = (void *)&bcm_l2x0_data},
+	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
+	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
 	  .data = (void *)&bcm_l2x0_data},
+	{ .compatible = "brcm,bcm11351-a2-pl310-cache",
+	  .data = (void *)&bcm_l2x0_data},
+	{ .compatible = "marvell,aurora-outer-cache",
+	  .data = (void *)&aurora_with_outer_data},
+	{ .compatible = "marvell,aurora-system-cache",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,tauros3-cache",
+	  .data = (void *)&tauros3_data },
 	{}
 };
 
diff --git a/arch/arm/mm/cache-tauros3.h b/arch/arm/mm/cache-tauros3.h
new file mode 100644
index 0000000..02c0a97
--- /dev/null
+++ b/arch/arm/mm/cache-tauros3.h
@@ -0,0 +1,41 @@
+/*
+ * Marvell Tauros3 cache controller includes
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_HARDWARE_TAUROS3_H
+#define __ASM_ARM_HARDWARE_TAUROS3_H
+
+/*
+ * Marvell Tauros3 L2CC is compatible with PL310 r0p0
+ * but with PREFETCH_CTRL (r2p0) and an additional event counter.
+ * Also, there is AUX2_CTRL for some Marvell specific control.
+ */
+
+#define TAUROS3_EVENT_CNT2_CFG		0x224
+#define TAUROS3_EVENT_CNT2_VAL		0x228
+#define TAUROS3_INV_ALL			0x780
+#define TAUROS3_CLEAN_ALL		0x784
+#define TAUROS3_AUX2_CTRL		0x820
+
+/* Registers shifts and masks */
+#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN	(1 << 2)
+
+#endif
-- 
1.8.4.rc3

[PATCH v4 7/9] ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

[Sebastian Hesselbarth]

This adds very basic device tree files for the Marvell Armada 1500 SoC
(Berlin BG2) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
device comprising the Armada 1500 SoC above.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
---
Changelog:
v3->v4:
- rename dts/dtsi to vendor,name.dts[i] (Suggested by Kumar Gala)
v2->v3:
- none
v1->v2:
- add "arm,pl310-cache" compatible to l2cc (Suggested by Mark Rutland)
- replace 88DE3xxx numbering with SoC variant name
  (Requested by Jisheng Zhang)
RCFv2->v1:
- switch to (soon to be) correct "marvell,pj4b" cpu compatible
- reference fixed-clock for uarts instead of hard-coded clock-frequency
- disable timers except two for clksrc and clkevt
RFCv1->RFCv2:
- add binding documentation (Reported by Jason Cooper)
- change l2cc from aurora to tauros3 (Reported by Thomas Petazzoni)
- add copyright reference
- adapt compatibles to mach-berlin instead of mach-mvebu

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: devicetree@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/arm/marvell,berlin.txt     |  24 +++
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/marvell,berlin2.dtsi             | 227 +++++++++++++++++++++
 arch/arm/boot/dts/sony,nsz-gs7.dts                 |  29 +++
 4 files changed, 282 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.txt
 create mode 100644 arch/arm/boot/dts/marvell,berlin2.dtsi
 create mode 100644 arch/arm/boot/dts/sony,nsz-gs7.dts

diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
new file mode 100644
index 0000000..737afa5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -0,0 +1,24 @@
+Marvell Berlin SoC Family Device Tree Bindings
+---------------------------------------------------------------
+
+Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
+shall have the following properties:
+
+* Required root node properties:
+compatible: must contain "marvell,berlin"
+
+In addition, the above compatible shall be extended with the specific
+SoC and board used. Currently known SoC compatibles are:
+    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
+    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
+    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
+    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)
+
+* Example:
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
+
+	...
+}
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..f742800 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -45,6 +45,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
 	bcm28155-ap.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += \
+	sony,nsz-gs7.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
 	da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/marvell,berlin2.dtsi b/arch/arm/boot/dts/marvell,berlin2.dtsi
new file mode 100644
index 0000000..56a1af2
--- /dev/null
+++ b/arch/arm/boot/dts/marvell,berlin2.dtsi
@@ -0,0 +1,227 @@
+/*
+ * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Marvell Armada 1500 (BG2) SoC";
+	compatible = "marvell,berlin2", "marvell,berlin";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "marvell,pj4b";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <1>;
+		};
+	};
+
+	clocks {
+		smclk: sysmgr-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
+		cfgclk: cfg-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+		};
+
+		sysclk: system-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <400000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+
+		ranges = <0 0xf7000000 0x1000000>;
+
+		l2: l2-cache-controller@ac0000 {
+			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
+			reg = <0xac0000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		gic: interrupt-controller@ad1000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		local-timer@ad0600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xad0600 0x20>;
+			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+		};
+
+		apb@e80000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xe80000 0x10000>;
+			interrupt-parent = <&aic>;
+
+			timer0: timer@2c00 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c00 0x14>;
+				interrupts = <8>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer1: timer@2c14 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c14 0x14>;
+				interrupts = <9>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer2: timer@2c28 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c28 0x14>;
+				interrupts = <10>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer3: timer@2c3c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c3c 0x14>;
+				interrupts = <11>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer4: timer@2c50 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c50 0x14>;
+				interrupts = <12>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer5: timer@2c64 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c64 0x14>;
+				interrupts = <13>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer6: timer@2c78 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c78 0x14>;
+				interrupts = <14>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer7: timer@2c8c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c8c 0x14>;
+				interrupts = <15>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			aic: interrupt-controller@3000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0x3000 0xc00>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		apb@fc0000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xfc0000 0x10000>;
+			interrupt-parent = <&sic>;
+
+			uart0: serial@9000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x9000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <8>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart1: serial@a000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xa000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <9>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart2: serial@b000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xb000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <10>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			sic: interrupt-controller@e000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0xe000 0x400>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/sony,nsz-gs7.dts b/arch/arm/boot/dts/sony,nsz-gs7.dts
new file mode 100644
index 0000000..a6b1482
--- /dev/null
+++ b/arch/arm/boot/dts/sony,nsz-gs7.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Sony NSZ-GS7
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "marvell,berlin2.dtsi"
+
+/ {
+	model = "Sony NSZ-GS7";
+	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>; /* 1 GB */
+	};
+};
+
+&uart0 { status = "okay"; };
-- 
1.8.4.rc3

[PATCH v4 8/9] ARM: add Armada 1500-mini and Chromecast device tree files

[Sebastian Hesselbarth]

This adds very basic device tree files for the Marvell Armada
1500-mini SoC (Berlin BG2CD) and the Google Chromecast. Currently,
SoC only has nodes for cpu, some clocks, l2 cache controller, local
timer, apb timers, uart, and interrupt controllers.
The Google Chromecast is a consumer device comprising the Armada
1500-mini SoC above.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
Changelog:
v3->v4:
- rename dts/dtsi to vendor,name.dts[i] (Suggested by Kumar Gala)
- remove non-mainline l2 properties (Reported by Jisheng Zhang)
v3:
- initial patch

Cc: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
Cc: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Cc: Kevin Hilman <khilman-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/arm/boot/dts/Makefile               |   1 +
 arch/arm/boot/dts/google,chromecast.dts  |  29 +++++
 arch/arm/boot/dts/marvell,berlin2cd.dtsi | 210 +++++++++++++++++++++++++++++++
 3 files changed, 240 insertions(+)
 create mode 100644 arch/arm/boot/dts/google,chromecast.dts
 create mode 100644 arch/arm/boot/dts/marvell,berlin2cd.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f742800..39b5e4e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -46,6 +46,7 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
 	bcm28155-ap.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
+	google,chromecast.dtb	\
 	sony,nsz-gs7.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
 	da850-evm.dtb
diff --git a/arch/arm/boot/dts/google,chromecast.dts b/arch/arm/boot/dts/google,chromecast.dts
new file mode 100644
index 0000000..42e37e7
--- /dev/null
+++ b/arch/arm/boot/dts/google,chromecast.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Google Chromecast
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "marvell,berlin2cd.dtsi"
+
+/ {
+	model = "Google Chromecast";
+	compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+};
+
+&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/marvell,berlin2cd.dtsi b/arch/arm/boot/dts/marvell,berlin2cd.dtsi
new file mode 100644
index 0000000..094968c
--- /dev/null
+++ b/arch/arm/boot/dts/marvell,berlin2cd.dtsi
@@ -0,0 +1,210 @@
+/*
+ * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Marvell Armada 1500-mini (BG2CD) SoC";
+	compatible = "marvell,berlin2cd", "marvell,berlin";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			next-level-cache = <&l2>;
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		smclk: sysmgr-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
+		cfgclk: cfg-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <75000000>;
+		};
+
+		sysclk: system-clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <300000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+
+		ranges = <0 0xf7000000 0x1000000>;
+
+		l2: l2-cache-controller@ac0000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xac0000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		gic: interrupt-controller@ad1000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		local-timer@ad0600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xad0600 0x20>;
+			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+		};
+
+		apb@e80000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xe80000 0x10000>;
+			interrupt-parent = <&aic>;
+
+			timer0: timer@2c00 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c00 0x14>;
+				interrupts = <8>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer1: timer@2c14 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c14 0x14>;
+				interrupts = <9>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "okay";
+			};
+
+			timer2: timer@2c28 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c28 0x14>;
+				interrupts = <10>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer3: timer@2c3c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c3c 0x14>;
+				interrupts = <11>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer4: timer@2c50 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c50 0x14>;
+				interrupts = <12>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer5: timer@2c64 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c64 0x14>;
+				interrupts = <13>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer6: timer@2c78 {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c78 0x14>;
+				interrupts = <14>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			timer7: timer@2c8c {
+				compatible = "snps,dw-apb-timer";
+				reg = <0x2c8c 0x14>;
+				interrupts = <15>;
+				clocks = <&cfgclk>;
+				clock-names = "timer";
+				status = "disabled";
+			};
+
+			aic: interrupt-controller@3000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0x3000 0xc00>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		apb@fc0000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xfc0000 0x10000>;
+			interrupt-parent = <&sic>;
+
+			uart0: serial@9000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x9000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <8>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			uart1: serial@a000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0xa000 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <1>;
+				interrupts = <9>;
+				clocks = <&smclk>;
+				status = "disabled";
+			};
+
+			sic: interrupt-controller@e000 {
+				compatible = "snps,dw-apb-ictl";
+				reg = <0xe000 0x400>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
-- 
1.8.4.rc3

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Re: [PATCH v4 0/9] ARM: Initial support for Marvell Berlin SoCs

[Olof Johansson]

Hi,

On Sun, Dec 08, 2013 at 03:13:57PM +0100, Sebastian Hesselbarth wrote:
> Hopefully last round of initial support patches for Marvell Berlin SoCs
> before I can send the final PR for v3.14.
> 
> Compared to last version sent, this patch set has now a Reviewed-by from
> Thomas Gleixner for the irqchip driver (Thanks for that!). Also, l2x0
> compatibles can now be reordered alphabetically instead of by derivate
> thanks to [1].
> 
> Marvell Docs have been updated to not mention Armada 1000 which has been
> discontinued by Marvell and vanished from their website. The dtsi/dts file
> have been renamed to vendor,name.dts[i], which is the preferred new naming
> scheme.
> 
> Open issues are the never ending dw_apb_timers_of story, which I ignore
> for now and hope they get in someday. Also, TWD SMP dependency and
> early l2x0_of_init will be addressed at a later date. At the current
> feature set of Berlin SoC, I don't see why the above issues should further
> stall this patches.
> 
> I guess, all patches can go through ARM SoC tree, except Tauros3 patch
> which I should submit to Russell's patch tracker?

Yep, sounds good.

I took a cursory glance at the patchset and it looks sane to me. I didn't
review in detail though.

One open question: Why don't you just add this to mach-mvebu? I thought
all modern Marvell platforms were going to converge on that eventually
anyway, and it's easy to add it now that it's early and simple..

Also, see below:

> Sebastian Hesselbarth (9):
>   irqchip: add DesignWare APB ICTL interrupt controller
>   MAINTAINERS: add ARM Marvell Berlin SoC
>   ARM: l2x0: add Marvell Tauros3 support
>   ARM: add Marvell Berlin SoC familiy to Marvell doc
>   ARM: add Marvell Berlin SoCs to multi_v7_defconfig
>   ARM: add Marvell Berlin UART0 lowlevel debug
>   ARM: add Armada 1500 and Sony NSZ-GS7 device tree files
>   ARM: add Armada 1500-mini and Chromecast device tree files
>   ARM: add initial support for Marvell Berlin SoCs
> 
>  Documentation/arm/Marvell/README                   |  24 +++
>  Documentation/devicetree/bindings/arm/l2cc.txt     |  23 ++-
>  .../devicetree/bindings/arm/marvell,berlin.txt     |  24 +++
>  .../interrupt-controller/snps,dw-apb-ictl.txt      |  32 +++
>  MAINTAINERS                                        |   6 +
>  arch/arm/Kconfig                                   |   2 +
>  arch/arm/Kconfig.debug                             |  10 +
>  arch/arm/Makefile                                  |   1 +
>  arch/arm/boot/dts/Makefile                         |   3 +
>  arch/arm/boot/dts/google,chromecast.dts            |  29 +++
>  arch/arm/boot/dts/marvell,berlin2.dtsi             | 227 +++++++++++++++++++++
>  arch/arm/boot/dts/marvell,berlin2cd.dtsi           | 210 +++++++++++++++++++
>  arch/arm/boot/dts/sony,nsz-gs7.dts                 |  29 +++

We have had a long-standing standard of naming the dts files
<family>-<board>.dts (or <soc_vendor>-<board>.dts).  Let's continue
sticking to that since it helps keep the namespace somewhat segmented per
platform in arch/arm/boot/dts.


-Olof

Re: [PATCH v4 0/9] ARM: Initial support for Marvell Berlin SoCs

[Sebastian Hesselbarth]

On 12/10/2013 02:40 AM, Olof Johansson wrote:
> On Sun, Dec 08, 2013 at 03:13:57PM +0100, Sebastian Hesselbarth wrote:
>> Hopefully last round of initial support patches for Marvell Berlin SoCs
>> before I can send the final PR for v3.14.
>>
>> Compared to last version sent, this patch set has now a Reviewed-by from
>> Thomas Gleixner for the irqchip driver (Thanks for that!). Also, l2x0
>> compatibles can now be reordered alphabetically instead of by derivate
>> thanks to [1].
>>
>> Marvell Docs have been updated to not mention Armada 1000 which has been
>> discontinued by Marvell and vanished from their website. The dtsi/dts file
>> have been renamed to vendor,name.dts[i], which is the preferred new naming
>> scheme.
>>
>> Open issues are the never ending dw_apb_timers_of story, which I ignore
>> for now and hope they get in someday. Also, TWD SMP dependency and
>> early l2x0_of_init will be addressed at a later date. At the current
>> feature set of Berlin SoC, I don't see why the above issues should further
>> stall this patches.
>>
>> I guess, all patches can go through ARM SoC tree, except Tauros3 patch
>> which I should submit to Russell's patch tracker?
>
> Yep, sounds good.
>
> I took a cursory glance at the patchset and it looks sane to me. I didn't
> review in detail though.
>
> One open question: Why don't you just add this to mach-mvebu? I thought
> all modern Marvell platforms were going to converge on that eventually
> anyway, and it's easy to add it now that it's early and simple..

Olof,

I started with mach-mvebu in the first RFC, but Berlin SoCs are from a
different business unit at Marvell and are more PXA compatible than
Orion/Kirkwood/Armada 370/XP. Most notably, they lack the "mbus" and
IP is either from PXA/MMP or Synopsys DW. Thomas Petazzoni and also
Jisheng Zhang from Marvell suggested to not put it into mvebu but
have a different mach folder instead.

> Also, see below:
>
>> Sebastian Hesselbarth (9):
>>    irqchip: add DesignWare APB ICTL interrupt controller
>>    MAINTAINERS: add ARM Marvell Berlin SoC
>>    ARM: l2x0: add Marvell Tauros3 support
>>    ARM: add Marvell Berlin SoC familiy to Marvell doc
>>    ARM: add Marvell Berlin SoCs to multi_v7_defconfig
>>    ARM: add Marvell Berlin UART0 lowlevel debug
>>    ARM: add Armada 1500 and Sony NSZ-GS7 device tree files
>>    ARM: add Armada 1500-mini and Chromecast device tree files
>>    ARM: add initial support for Marvell Berlin SoCs
>>
>>   Documentation/arm/Marvell/README                   |  24 +++
>>   Documentation/devicetree/bindings/arm/l2cc.txt     |  23 ++-
>>   .../devicetree/bindings/arm/marvell,berlin.txt     |  24 +++
>>   .../interrupt-controller/snps,dw-apb-ictl.txt      |  32 +++
>>   MAINTAINERS                                        |   6 +
>>   arch/arm/Kconfig                                   |   2 +
>>   arch/arm/Kconfig.debug                             |  10 +
>>   arch/arm/Makefile                                  |   1 +
>>   arch/arm/boot/dts/Makefile                         |   3 +
>>   arch/arm/boot/dts/google,chromecast.dts            |  29 +++
>>   arch/arm/boot/dts/marvell,berlin2.dtsi             | 227 +++++++++++++++++++++
>>   arch/arm/boot/dts/marvell,berlin2cd.dtsi           | 210 +++++++++++++++++++
>>   arch/arm/boot/dts/sony,nsz-gs7.dts                 |  29 +++
>
> We have had a long-standing standard of naming the dts files
> <family>-<board>.dts (or <soc_vendor>-<board>.dts).  Let's continue
> sticking to that since it helps keep the namespace somewhat segmented per
> platform in arch/arm/boot/dts.

Also, here: I had the naming that way until v3, then Kumar suggested to
use prefixed naming scheme. Maybe I got it wrong?

Are you suggesting to name the above back to:
berlin2[cd].dtsi,
berlin2-nsz-gs7.dts, and
berlin2cd-chromecast.dts?

Sebastian

Re: [PATCH v4 0/9] ARM: Initial support for Marvell Berlin SoCs

[Olof Johansson]

On Tue, Dec 10, 2013 at 02:57:05AM +0100, Sebastian Hesselbarth wrote:
> On 12/10/2013 02:40 AM, Olof Johansson wrote:
> >On Sun, Dec 08, 2013 at 03:13:57PM +0100, Sebastian Hesselbarth wrote:
> >>Hopefully last round of initial support patches for Marvell Berlin SoCs
> >>before I can send the final PR for v3.14.
> >>
> >>Compared to last version sent, this patch set has now a Reviewed-by from
> >>Thomas Gleixner for the irqchip driver (Thanks for that!). Also, l2x0
> >>compatibles can now be reordered alphabetically instead of by derivate
> >>thanks to [1].
> >>
> >>Marvell Docs have been updated to not mention Armada 1000 which has been
> >>discontinued by Marvell and vanished from their website. The dtsi/dts file
> >>have been renamed to vendor,name.dts[i], which is the preferred new naming
> >>scheme.
> >>
> >>Open issues are the never ending dw_apb_timers_of story, which I ignore
> >>for now and hope they get in someday. Also, TWD SMP dependency and
> >>early l2x0_of_init will be addressed at a later date. At the current
> >>feature set of Berlin SoC, I don't see why the above issues should further
> >>stall this patches.
> >>
> >>I guess, all patches can go through ARM SoC tree, except Tauros3 patch
> >>which I should submit to Russell's patch tracker?
> >
> >Yep, sounds good.
> >
> >I took a cursory glance at the patchset and it looks sane to me. I didn't
> >review in detail though.
> >
> >One open question: Why don't you just add this to mach-mvebu? I thought
> >all modern Marvell platforms were going to converge on that eventually
> >anyway, and it's easy to add it now that it's early and simple..
> 
> Olof,
> 
> I started with mach-mvebu in the first RFC, but Berlin SoCs are from a
> different business unit at Marvell and are more PXA compatible than
> Orion/Kirkwood/Armada 370/XP. Most notably, they lack the "mbus" and
> IP is either from PXA/MMP or Synopsys DW. Thomas Petazzoni and also
> Jisheng Zhang from Marvell suggested to not put it into mvebu but
> have a different mach folder instead.

Hmm, ok. Well, maybe later on we can look at aggregating them more again. It'd
be nice to get fewer top-level platform directories per vendor.

> >Also, see below:
> >
> >>Sebastian Hesselbarth (9):
> >>   irqchip: add DesignWare APB ICTL interrupt controller
> >>   MAINTAINERS: add ARM Marvell Berlin SoC
> >>   ARM: l2x0: add Marvell Tauros3 support
> >>   ARM: add Marvell Berlin SoC familiy to Marvell doc
> >>   ARM: add Marvell Berlin SoCs to multi_v7_defconfig
> >>   ARM: add Marvell Berlin UART0 lowlevel debug
> >>   ARM: add Armada 1500 and Sony NSZ-GS7 device tree files
> >>   ARM: add Armada 1500-mini and Chromecast device tree files
> >>   ARM: add initial support for Marvell Berlin SoCs
> >>
> >>  Documentation/arm/Marvell/README                   |  24 +++
> >>  Documentation/devicetree/bindings/arm/l2cc.txt     |  23 ++-
> >>  .../devicetree/bindings/arm/marvell,berlin.txt     |  24 +++
> >>  .../interrupt-controller/snps,dw-apb-ictl.txt      |  32 +++
> >>  MAINTAINERS                                        |   6 +
> >>  arch/arm/Kconfig                                   |   2 +
> >>  arch/arm/Kconfig.debug                             |  10 +
> >>  arch/arm/Makefile                                  |   1 +
> >>  arch/arm/boot/dts/Makefile                         |   3 +
> >>  arch/arm/boot/dts/google,chromecast.dts            |  29 +++
> >>  arch/arm/boot/dts/marvell,berlin2.dtsi             | 227 +++++++++++++++++++++
> >>  arch/arm/boot/dts/marvell,berlin2cd.dtsi           | 210 +++++++++++++++++++
> >>  arch/arm/boot/dts/sony,nsz-gs7.dts                 |  29 +++
> >
> >We have had a long-standing standard of naming the dts files
> ><family>-<board>.dts (or <soc_vendor>-<board>.dts).  Let's continue
> >sticking to that since it helps keep the namespace somewhat segmented per
> >platform in arch/arm/boot/dts.
> 
> Also, here: I had the naming that way until v3, then Kumar suggested to
> use prefixed naming scheme. Maybe I got it wrong?
> 
> Are you suggesting to name the above back to:
> berlin2[cd].dtsi,
> berlin2-nsz-gs7.dts, and
> berlin2cd-chromecast.dts?

Personally I prefer something similar to the mach-directory name as prefix, so
berlin-<soc number>.dts and then berlin-chromecast.dts, etc. But I'm not that
picky, if you have something else you prefer then that's fine too.

At some point we should restructure the dts directory into subdirectories,
which will remove some of these requirements, but we're not there quite yet.


-Olof

Re: [PATCH v4 0/9] ARM: Initial support for Marvell Berlin SoCs

[Arnd Bergmann]

On Tuesday 10 December 2013, Olof Johansson wrote:
> > I started with mach-mvebu in the first RFC, but Berlin SoCs are from a
> > different business unit at Marvell and are more PXA compatible than
> > Orion/Kirkwood/Armada 370/XP. Most notably, they lack the "mbus" and
> > IP is either from PXA/MMP or Synopsys DW. Thomas Petazzoni and also
> > Jisheng Zhang from Marvell suggested to not put it into mvebu but
> > have a different mach folder instead.
> 
> Hmm, ok. Well, maybe later on we can look at aggregating them more again. It'd
> be nice to get fewer top-level platform directories per vendor.

I possibly a lot of directories just become empty in the long run and
we remove them once all all code has been subsystemized and drivered.

	Arnd

Re: [PATCH v4 0/9] ARM: Initial support for Marvell Berlin SoCs

[Olof Johansson]

On Tue, Dec 10, 2013 at 11:33 AM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Tuesday 10 December 2013, Olof Johansson wrote:
>> > I started with mach-mvebu in the first RFC, but Berlin SoCs are from a
>> > different business unit at Marvell and are more PXA compatible than
>> > Orion/Kirkwood/Armada 370/XP. Most notably, they lack the "mbus" and
>> > IP is either from PXA/MMP or Synopsys DW. Thomas Petazzoni and also
>> > Jisheng Zhang from Marvell suggested to not put it into mvebu but
>> > have a different mach folder instead.
>>
>> Hmm, ok. Well, maybe later on we can look at aggregating them more again. It'd
>> be nice to get fewer top-level platform directories per vendor.
>
> I possibly a lot of directories just become empty in the long run and
> we remove them once all all code has been subsystemized and drivered.

For mobile SoCs it's somewhat unlikely that it will ever be completely
empty, but maybe. Either way, once the contents is small enough it's a
lot easier to move around and aggregate into one platform.

-Olof
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Re: [PATCH v4 0/9] ARM: Initial support for Marvell Berlin SoCs

[Sebastian Hesselbarth]

On 12/10/2013 08:38 PM, Olof Johansson wrote:
> On Tue, Dec 10, 2013 at 11:33 AM, Arnd Bergmann <arnd@arndb.de> wrote:
>> On Tuesday 10 December 2013, Olof Johansson wrote:
>>>> I started with mach-mvebu in the first RFC, but Berlin SoCs are from a
>>>> different business unit at Marvell and are more PXA compatible than
>>>> Orion/Kirkwood/Armada 370/XP. Most notably, they lack the "mbus" and
>>>> IP is either from PXA/MMP or Synopsys DW. Thomas Petazzoni and also
>>>> Jisheng Zhang from Marvell suggested to not put it into mvebu but
>>>> have a different mach folder instead.
>>>
>>> Hmm, ok. Well, maybe later on we can look at aggregating them more again. It'd
>>> be nice to get fewer top-level platform directories per vendor.
>>
>> I possibly a lot of directories just become empty in the long run and
>> we remove them once all all code has been subsystemized and drivered.
>
> For mobile SoCs it's somewhat unlikely that it will ever be completely
> empty, but maybe. Either way, once the contents is small enough it's a
> lot easier to move around and aggregate into one platform.

Well, I plan to add no code at all to mach-berlin except machine init.
If there would be some mach-multiv7, I'd be happy to put it in there.

mach-mvebu is still a moving target and adding it there would cause more
trouble than it helps. Adding the other Orion SoCs will be enough for
now.

About the dts/dtsi naming, I really have no preference. I had
soc-vendor-boardname style before v4. About the new naming, I liked
that SoC dtsi are named after soc-vendor,soc-type.dtsi while boards are
named after board-vendor,board-name.dts. It kind of matches what you
will look for if you have e.g. the Google Chromecast and not know about
the Soc used.

We still have some time before the ARM merge window for 3.14 closes,
right? So I can have another round of code moving and renaming within
this patch set ;)

Sebastian