From: Peter Chen <peter.chen-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
To: balbi-l0cyMroinI0@public.gmane.org,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
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Cc: alexander.shishkin-VuQAYsv1563Yd54FQh9/CA@public.gmane.org,
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Subject: [PATCH v4 16/17] usb: phy-mxs: fix the problem by only using 1st controller's register
Date: Tue, 3 Dec 2013 15:37:10 +0800 [thread overview]
Message-ID: <1386056231-17258-17-git-send-email-peter.chen@freescale.com> (raw)
In-Reply-To: <1386056231-17258-1-git-send-email-peter.chen-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
We fix the problem that we only use the 1st controller's related
registers at mxs_phy_disconnect_line, but in fact, it needs to
access registers according to different PHYs.
Signed-off-by: Peter Chen <peter.chen-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
drivers/usb/phy/phy-mxs-usb.c | 89 +++++++++++++++++++++++++++++------------
1 files changed, 63 insertions(+), 26 deletions(-)
diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
index 4c2dfcd..542b6ec 100644
--- a/drivers/usb/phy/phy-mxs-usb.c
+++ b/drivers/usb/phy/phy-mxs-usb.c
@@ -62,17 +62,23 @@
#define ANADIG_ANA_MISC0_CLR 0x158
#define ANADIG_USB1_VBUS_DET_STAT 0x1c0
+#define ANADIG_USB2_VBUS_DET_STAT 0x220
#define ANADIG_USB1_LOOPBACK_SET 0x1e4
#define ANADIG_USB1_LOOPBACK_CLR 0x1e8
+#define ANADIG_USB2_LOOPBACK_SET 0x244
+#define ANADIG_USB2_LOOPBACK_CLR 0x248
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12)
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
+#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2)
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5)
+#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2)
+#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5)
#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
@@ -182,12 +188,61 @@ static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
return 0;
}
-static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
+/* Return true if the vbus is there */
+static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy)
+{
+ unsigned int vbus_value;
+
+ if (mxs_phy->port_id == 0)
+ regmap_read(mxs_phy->regmap_anatop,
+ ANADIG_USB1_VBUS_DET_STAT,
+ &vbus_value);
+ else if (mxs_phy->port_id == 1)
+ regmap_read(mxs_phy->regmap_anatop,
+ ANADIG_USB2_VBUS_DET_STAT,
+ &vbus_value);
+
+ if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
+ return true;
+ else
+ return false;
+}
+
+static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect)
{
void __iomem *base = mxs_phy->phy.io_priv;
+ u32 reg;
+
+ if (disconnect)
+ writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
+ base + HW_USBPHY_DEBUG_CLR);
+
+ if (mxs_phy->port_id == 0) {
+ reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
+ : ANADIG_USB1_LOOPBACK_CLR;
+ regmap_write(mxs_phy->regmap_anatop, reg,
+ BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
+ BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
+ } else if (mxs_phy->port_id == 1) {
+ reg = disconnect ? ANADIG_USB2_LOOPBACK_SET
+ : ANADIG_USB2_LOOPBACK_CLR;
+ regmap_write(mxs_phy->regmap_anatop, reg,
+ BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 |
+ BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN);
+ }
+
+ if (!disconnect)
+ writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
+ base + HW_USBPHY_DEBUG_SET);
+
+ /* Delay some time, and let Linestate be SE0 for controller */
+ if (disconnect)
+ usleep_range(500, 1000);
+}
+
+static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
+{
bool vbus_is_on = false;
- static bool line_is_disconnected;
- unsigned int vbus_value = 0;
/* If the SoCs don't need to disconnect line without vbus, quit */
if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS))
@@ -197,31 +252,13 @@ static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
if (!mxs_phy->regmap_anatop)
return;
- regmap_read(mxs_phy->regmap_anatop, ANADIG_USB1_VBUS_DET_STAT,
- &vbus_value);
- if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
- vbus_is_on = true;
+ vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
- if (on && !vbus_is_on) {
- writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
- base + HW_USBPHY_DEBUG_CLR);
- regmap_write(mxs_phy->regmap_anatop, ANADIG_USB1_LOOPBACK_SET,
- BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
- BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
- /* Delay some time, and let Linestate be SE0 for controller */
- usleep_range(500, 1000);
- line_is_disconnected = true;
- } else if (line_is_disconnected) {
- regmap_write(mxs_phy->regmap_anatop, ANADIG_USB1_LOOPBACK_CLR,
- BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
- BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
- writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
- base + HW_USBPHY_DEBUG_SET);
- line_is_disconnected = false;
- }
+ if (on && !vbus_is_on)
+ __mxs_phy_disconnect_line(mxs_phy, true);
+ else
+ __mxs_phy_disconnect_line(mxs_phy, false);
- dev_dbg(mxs_phy->phy.dev, "line is %s\n", line_is_disconnected
- ? "disconnected" : "connected");
}
static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on)
--
1.7.8
--
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next prev parent reply other threads:[~2013-12-03 7:37 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-03 7:36 [PATCH v4 00/17] Add power management support for mxs phy Peter Chen
[not found] ` <1386056231-17258-1-git-send-email-peter.chen-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2013-12-03 7:36 ` [PATCH v4 01/17] usb: doc: phy-mxs: Add more compatible strings Peter Chen
2013-12-03 7:36 ` [PATCH v4 02/17] usb: phy-mxs: Add platform judgement code Peter Chen
2013-12-03 8:38 ` Marc Kleine-Budde
[not found] ` <529D987C.8080905-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-12-03 8:12 ` Peter Chen
2013-12-03 10:24 ` Michael Grzeschik
[not found] ` <20131203102416.GB27635-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-12-03 14:09 ` Peter Chen
2013-12-03 7:36 ` [PATCH v4 03/17] usb: phy-mxs: Add auto clock and power setting Peter Chen
2013-12-03 7:36 ` [PATCH v4 04/17] usb: doc: phy-mxs: update binding for adding anatop phandle Peter Chen
2013-12-03 7:36 ` [PATCH v4 05/17] ARM: dts: imx6: add anatop phandle for usbphy Peter Chen
2013-12-03 7:37 ` [PATCH v4 06/17] usb: phy-mxs: Add anatop regmap Peter Chen
2013-12-03 7:37 ` [PATCH v4 07/17] usb: phy: add notify suspend and resume callback Peter Chen
2013-12-03 7:37 ` [PATCH v4 08/17] usb: phy-mxs: Add implementation of nofity_suspend and notify_resume Peter Chen
2013-12-03 7:37 ` [PATCH v4 09/17] usb: phy-mxs: Enable IC fixes for related SoCs Peter Chen
2013-12-03 8:27 ` Marc Kleine-Budde
2013-12-03 8:38 ` Peter Chen
[not found] ` <F281D0F91ED19E4D8E63A7504E8A649804140F64-RL0Hj/+nBVAqqAZmXiz6tK4g8xLGJsHaLnY5E4hWTkheoWH0uzbU5w@public.gmane.org>
2013-12-03 8:43 ` Marc Kleine-Budde
2013-12-03 8:49 ` Peter Chen
2013-12-03 7:37 ` [PATCH v4 11/17] usb: phy-mxs: Add implementation of set_wakeup Peter Chen
2013-12-03 7:37 ` [PATCH v4 14/17] ARM: dts: imx: add mxs phy controller id Peter Chen
2013-12-03 7:37 ` [PATCH v4 15/17] usb: phy-mxs: add " Peter Chen
2013-12-03 7:37 ` Peter Chen [this message]
2013-12-03 8:34 ` [PATCH v4 16/17] usb: phy-mxs: fix the problem by only using 1st controller's register Marc Kleine-Budde
[not found] ` <529D9781.1080209-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2013-12-03 8:12 ` Peter Chen
2013-12-03 7:37 ` [PATCH v4 17/17] usb: phy-mxs: do not set PWD.RXPWD1PT1 for low speed connection Peter Chen
[not found] ` <1386056231-17258-18-git-send-email-peter.chen-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2013-12-03 8:53 ` Marc Kleine-Budde
2013-12-03 9:19 ` Peter Chen
2013-12-03 9:28 ` Marc Kleine-Budde
2013-12-03 9:48 ` Peter Chen
2013-12-03 7:37 ` [PATCH v4 10/17] usb: phy: Add set_wakeup API Peter Chen
2013-12-03 7:37 ` [PATCH v4 12/17] usb: phy-mxs: Add system suspend/resume API Peter Chen
2013-12-03 7:37 ` [PATCH v4 13/17] usb: phy-mxs: Add sync time after controller clear phcd Peter Chen
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