[PATCH 0/7] Calxeda arm64 clock updates

[PATCH 0/7] Calxeda arm64 clock updates

[Rob Herring]

From: Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>

This series updates the highbank clock code for ECX-3000 series support.     
The primary functional change is making the PLL max frequency a runtime
setting. The rest of the changes are enabling building on arm64 and new
DT bindings.

The patch "clk: highbank: prevent glitching when going into bypass mode"
is a fix needed for ECX-2000 systems and should be applied for 3.13 and
stable.

Rob

Mark Langsdorf (1):
  clk: highbank: prevent glitching when going into bypass mode

Rob Herring (6):
  dt-bindings: add Calxeda ECX-3000 clock binding
  dt-bindings: Add property calxeda,pll-max-hz for Calxeda clocks
  dt-bindings: Add Calxeda system registers binding
  clk: highbank: allow for different PLL frequency range
  clk: highbank: allow enabling by user
  clk: highbank: add DT match for calxeda,ecx-3000-sregs

 .../devicetree/bindings/arm/calxeda/sregs.txt      | 17 +++++++++
 .../devicetree/bindings/clock/calxeda.txt          |  9 ++++-
 arch/arm/mach-highbank/Kconfig                     |  1 +
 drivers/clk/Kconfig                                |  5 +++
 drivers/clk/Makefile                               |  2 +-
 drivers/clk/clk-highbank.c                         | 43 +++++++++++++++-------
 6 files changed, 61 insertions(+), 16 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda/sregs.txt

-- 
1.8.3.2

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[PATCH 1/7] dt-bindings: add Calxeda ECX-3000 clock binding

[Rob Herring]

From: Rob Herring <rob.herring@calxeda.com>

Add "calxeda,ecx-3000-pll-clock" compatible property for Calxeda ECX-3000
series PLLs.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
---
 Documentation/devicetree/bindings/clock/calxeda.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt
index 0a6ac1b..7ebc89c 100644
--- a/Documentation/devicetree/bindings/clock/calxeda.txt
+++ b/Documentation/devicetree/bindings/clock/calxeda.txt
@@ -6,7 +6,7 @@ This binding uses the common clock binding[1].
 
 Required properties:
 - compatible : shall be one of the following:
-	"calxeda,hb-pll-clock" - for a PLL clock
+	"calxeda,ecx-3000-pll-clock" or "calxeda,hb-pll-clock" - for a PLL clock
 	"calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
 		A9 clock.
 	"calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
-- 
1.8.3.2

[PATCH 2/7] dt-bindings: Add property calxeda,pll-max-hz for Calxeda clocks

[Rob Herring]

From: Rob Herring <rob.herring@calxeda.com>

Newer versions of PLL h/w have different frequency ranges for the PLLs,
but otherwise have the same programming model. Add an optional property
"calxeda,pll-max-hz" for Calxeda PLL clocks to handle this difference.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
---
 Documentation/devicetree/bindings/clock/calxeda.txt | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt
index 7ebc89c..9ee1b64 100644
--- a/Documentation/devicetree/bindings/clock/calxeda.txt
+++ b/Documentation/devicetree/bindings/clock/calxeda.txt
@@ -1,4 +1,4 @@
-Device Tree Clock bindings for Calxeda highbank platform
+Device Tree Clock bindings for Calxeda platforms
 
 This binding uses the common clock binding[1].
 
@@ -15,3 +15,8 @@ Required properties:
 - clocks : shall be the input parent clock phandle for the clock. This is
 	either an oscillator or a pll output.
 - #clock-cells : from common clock binding; shall be set to 0.
+
+Optional properties:
+- calxeda,pll-max-hz : The maximum output frequency of the PLL in Hz. The
+	default is 2.133GHz if not present. This is only present for
+	"calxeda,hb-pll-clock" nodes.
-- 
1.8.3.2

[PATCH 3/7] dt-bindings: Add Calxeda system registers binding

[Rob Herring]

From: Rob Herring <rob.herring@calxeda.com>

Add bindings for Calxeda system registers. "calxeda,hb-sregs" has been in
use by the kernel for some time, but has been undocumented. Add the
missing documentation and add the new compatible string for ECX-3000
series.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
---
 Documentation/devicetree/bindings/arm/calxeda/sregs.txt | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda/sregs.txt

diff --git a/Documentation/devicetree/bindings/arm/calxeda/sregs.txt b/Documentation/devicetree/bindings/arm/calxeda/sregs.txt
new file mode 100644
index 0000000..d78e176
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/calxeda/sregs.txt
@@ -0,0 +1,17 @@
+Calxeda System Registers
+
+Properties:
+- compatible : Should be one of:
+	"calxeda,hb-sregs"
+	"calxeda,ecx-3000-sregs"
+- reg : Address and size for SREGs registers.
+
+Subnodes:
+Clocks are specified under "clocks" subnode.
+
+Example:
+
+	sregs@fff3c000 {
+		compatible = "calxeda,hb-sregs";
+		reg = <0xfff3c000 0x1000>;
+	};
-- 
1.8.3.2

[PATCH 4/7] clk: highbank: prevent glitching when going into bypass mode

[Rob Herring]

From: Mark Langsdorf <mark.langsdorf@calxeda.com>

Under very rare circumstances, the clock multiplexer can take around
100 ns to enter bypass mode. Attempting to reprogram the clock PLL
before the clock has fully entered bypass mode can cause errors in the
system, up to and including kernel panics. Add a 300 ns delay after
programming the bypass enable to make sure that bypass mode has been
enabled.

This patch should be added to the stable series.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
---
 drivers/clk/clk-highbank.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index 2e7e9d9..dc7ca30 100644
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -21,6 +21,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/delay.h>
 
 #define HB_PLL_LOCK_500		0x20000000
 #define HB_PLL_LOCK		0x10000000
@@ -167,6 +168,8 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
 		/* Need to re-lock PLL, so put it into bypass mode */
 		reg |= HB_PLL_EXT_BYPASS;
 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
+		/* delay to make sure we are in bypass */
+		ndelay(300);
 
 		writel(reg | HB_PLL_RESET, hbclk->reg);
 		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
@@ -182,6 +185,9 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
 		reg &= ~HB_PLL_EXT_BYPASS;
 	} else {
 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
+		/* delay to make sure we are in bypass */
+		ndelay(300);
+
 		reg &= ~HB_PLL_DIVQ_MASK;
 		reg |= divq << HB_PLL_DIVQ_SHIFT;
 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
-- 
1.8.3.2

[PATCH 5/7] clk: highbank: allow for different PLL frequency range

[Rob Herring]

From: Rob Herring <rob.herring@calxeda.com>

Newer versions of Calxeda PLLs have a different frequency range. Make
the max frequency a variable and add a DT property to handle different
maximum frequencies for the PLLs.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Mike Turquette <mturquette@linaro.org>
---
 drivers/clk/clk-highbank.c | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index dc7ca30..89efcbc 100644
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -30,7 +30,7 @@
 #define HB_PLL_DIVQ_SHIFT	16
 #define HB_PLL_DIVQ_MASK	0x00070000
 #define HB_PLL_DIVR_SHIFT	8
-#define HB_PLL_DIVR_MASK	0x00001f00
+#define HB_PLL_DIVR_MASK	0x00003f00
 #define HB_PLL_RANGE_SHIFT	4
 #define HB_PLL_RANGE_MASK	0x00000070
 #define HB_PLL_BYPASS		0x00000008
@@ -38,9 +38,7 @@
 #define HB_PLL_EXT_BYPASS	0x00000002
 #define HB_PLL_EXT_ENA		0x00000001
 
-#define HB_PLL_VCO_MIN_FREQ	2133000000
-#define HB_PLL_MAX_FREQ		HB_PLL_VCO_MIN_FREQ
-#define HB_PLL_MIN_FREQ		(HB_PLL_VCO_MIN_FREQ / 64)
+#define HB_PLL_MAX_FREQ		2133000000
 
 #define HB_A9_BCLK_DIV_MASK	0x00000006
 #define HB_A9_BCLK_DIV_SHIFT	1
@@ -49,6 +47,7 @@
 struct hb_clk {
         struct clk_hw	hw;
 	void __iomem	*reg;
+	u32 max_freq;
 	char *parent_name;
 };
 #define to_hb_clk(p) container_of(p, struct hb_clk, hw)
@@ -119,19 +118,21 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
 	return vco_freq / (1 << divq);
 }
 
-static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
+static void clk_pll_calc(struct clk_hw *hwclk, unsigned long rate,
+			unsigned long ref_freq,
 			u32 *pdivq, u32 *pdivf)
 {
+	u32 pll_max_freq = to_hb_clk(hwclk)->max_freq;
 	u32 divq, divf;
 	unsigned long vco_freq;
 
-	if (rate < HB_PLL_MIN_FREQ)
-		rate = HB_PLL_MIN_FREQ;
-	if (rate > HB_PLL_MAX_FREQ)
-		rate = HB_PLL_MAX_FREQ;
+	if (rate < (pll_max_freq / 64))
+		rate = pll_max_freq / 64;
+	if (rate > pll_max_freq)
+		rate = pll_max_freq;
 
 	for (divq = 1; divq <= 6; divq++) {
-		if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
+		if ((rate * (1 << divq)) >= pll_max_freq)
 			break;
 	}
 
@@ -149,7 +150,7 @@ static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
 	u32 divq, divf;
 	unsigned long ref_freq = *parent_rate;
 
-	clk_pll_calc(rate, ref_freq, &divq, &divf);
+	clk_pll_calc(hwclk, rate, ref_freq, &divq, &divf);
 
 	return (ref_freq * (divf + 1)) / (1 << divq);
 }
@@ -161,7 +162,7 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
 	u32 divq, divf;
 	u32 reg;
 
-	clk_pll_calc(rate, parent_rate, &divq, &divf);
+	clk_pll_calc(hwclk, rate, parent_rate, &divq, &divf);
 
 	reg = readl(hbclk->reg);
 	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
@@ -304,6 +305,10 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
+	of_property_read_u32(node, "calxeda,pll-max-hz", &hb_clk->max_freq);
+	if (!hb_clk->max_freq)
+		hb_clk->max_freq = HB_PLL_MAX_FREQ;
+
 	init.name = clk_name;
 	init.ops = ops;
 	init.flags = 0;
-- 
1.8.3.2

[PATCH 6/7] clk: highbank: allow enabling by user

[Rob Herring]

From: Rob Herring <rob.herring@calxeda.com>

Allow Calxeda clock driver to be enabled by the user independent of
ARCH_HIGHBANK.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Mike Turquette <mturquette@linaro.org>
---
 arch/arm/mach-highbank/Kconfig | 1 +
 drivers/clk/Kconfig            | 5 +++++
 drivers/clk/Makefile           | 2 +-
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 0aded64..64dba0e 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -15,6 +15,7 @@ config ARCH_HIGHBANK
 	select ARM_TIMER_SP804
 	select CACHE_L2X0
 	select COMMON_CLK
+	select COMMON_CLK_CALXEDA
 	select CPU_V7
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 5c51115..e395e4f 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -49,6 +49,11 @@ config COMMON_CLK_VERSATILE
 	  - RealView PB1176, EB, PB11MP and PBX
 	  - Versatile Express
 
+config COMMON_CLK_CALXEDA
+	bool "Clock driver for Calxeda platforms"
+	---help---
+          Clock driver for Calxeda ECX based platforms.
+
 config COMMON_CLK_MAX77686
 	tristate "Clock driver for Maxim 77686 MFD"
 	depends on MFD_MAX77686
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7a10bc9..6010bdb 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
 obj-$(CONFIG_ARCH_BCM2835)	+= clk-bcm2835.o
 obj-$(CONFIG_ARCH_EFM32)	+= clk-efm32gg.o
 obj-$(CONFIG_ARCH_NOMADIK)	+= clk-nomadik.o
-obj-$(CONFIG_ARCH_HIGHBANK)	+= clk-highbank.o
+obj-$(CONFIG_COMMON_CLK_CALXEDA) += clk-highbank.o
 obj-$(CONFIG_ARCH_NSPIRE)	+= clk-nspire.o
 obj-$(CONFIG_ARCH_MXS)		+= mxs/
 obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
-- 
1.8.3.2

[PATCH 7/7] clk: highbank: add DT match for calxeda,ecx-3000-sregs

[Rob Herring]

From: Rob Herring <rob.herring@calxeda.com>

The system registers are a bit different overall and need a different
compatible string, but the clock registers are similar. So for the clock
code, we just need to match with the new compatible string.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Mike Turquette <mturquette@linaro.org>
---
 drivers/clk/clk-highbank.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index 89efcbc..8023146 100644
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -278,6 +278,12 @@ static const struct clk_ops periclk_ops = {
 	.set_rate = clk_periclk_set_rate,
 };
 
+static struct of_device_id sregs_match[] = {
+	{ .compatible = "calxeda,ecx-3000-sregs" },
+	{ .compatible = "calxeda,hb-sregs" },
+	{}
+};
+
 static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)
 {
 	u32 reg;
@@ -298,7 +304,7 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk
 		return NULL;
 
 	/* Map system registers */
-	srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
+	srnp = of_find_matching_node(NULL, sregs_match);
 	hb_clk->reg = of_iomap(srnp, 0);
 	BUG_ON(!hb_clk->reg);
 	hb_clk->reg += reg;
-- 
1.8.3.2