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From: Tero Kristo <t-kristo@ti.com>
To: linux-omap@vger.kernel.org, paul@pwsan.com, tony@atomide.com,
	nm@ti.com, rnayak@ti.com, bcousson@baylibre.com,
	mturquette@linaro.org
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: [PATCHv12 08/49] clk: gate: add support for low level ops
Date: Fri, 20 Dec 2013 18:34:26 +0200	[thread overview]
Message-ID: <1387557274-22583-8-git-send-email-t-kristo@ti.com> (raw)
In-Reply-To: <1387557274-22583-1-git-send-email-t-kristo@ti.com>

Gate clock can now be registered to use low level register access ops.
Preferred initialization method is via clock description.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-gate.c       |   20 +++++++++++++++++---
 include/linux/clk-provider.h |    4 ++++
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 3ec61d2..d4c94a7 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -62,7 +62,10 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
 		if (set)
 			reg |= BIT(gate->bit_idx);
 	} else {
-		reg = clk_readl(gate->reg);
+		if (gate->ll_ops)
+			reg = gate->ll_ops->clk_readl(gate->reg);
+		else
+			reg = clk_readl(gate->reg);
 
 		if (set)
 			reg |= BIT(gate->bit_idx);
@@ -70,7 +73,10 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
 			reg &= ~BIT(gate->bit_idx);
 	}
 
-	clk_writel(reg, gate->reg);
+	if (gate->ll_ops)
+		gate->ll_ops->clk_writel(reg, gate->reg);
+	else
+		clk_writel(reg, gate->reg);
 
 	if (gate->lock)
 		spin_unlock_irqrestore(gate->lock, flags);
@@ -93,7 +99,10 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
 	u32 reg;
 	struct clk_gate *gate = to_clk_gate(hw);
 
-	reg = clk_readl(gate->reg);
+	if (gate->ll_ops)
+		reg = gate->ll_ops->clk_readl(gate->reg);
+	else
+		reg = clk_readl(gate->reg);
 
 	/* if a set bit disables this clk, flip it before masking */
 	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
@@ -157,6 +166,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 	gate->flags = clk_gate_flags;
 	gate->lock = lock;
 	gate->hw.init = &init;
+	gate->ll_ops = &clk_ll_ops_default;
 
 	clk = clk_register(dev, &gate->hw);
 
@@ -184,6 +194,10 @@ struct clk_hw *clk_register_gate_desc(struct device *dev, struct clk_desc *desc)
 	gate->bit_idx = hw_desc->bit_idx;
 	gate->flags = hw_desc->flags;
 	gate->lock = hw_desc->lock;
+	gate->ll_ops = hw_desc->ll_ops;
+
+	if (!gate->ll_ops)
+		gate->ll_ops = &clk_ll_ops_default;
 
 	if (!desc->ops)
 		desc->ops = &clk_gate_ops;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f082a89..3923d46 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -262,6 +262,7 @@ void of_fixed_clk_setup(struct device_node *np);
  *
  * @hw:		handle between common and hardware-specific interfaces
  * @reg:	register controlling gate
+ * @ll_ops:	low-level ops for accessing the register
  * @bit_idx:	single bit controlling gate
  * @flags:	hardware-specific flags
  * @lock:	register lock
@@ -280,6 +281,7 @@ void of_fixed_clk_setup(struct device_node *np);
 struct clk_gate {
 	struct clk_hw hw;
 	void __iomem	*reg;
+	struct clk_ll_ops	*ll_ops;
 	u8		bit_idx;
 	u8		flags;
 	spinlock_t	*lock;
@@ -289,6 +291,7 @@ struct clk_gate {
  * struct clk_gate_desc - init descriptor for gating clock
  * @desc:	handle between common and hardware-specific interfaces
  * @reg:	register controlling gate
+ * @ll_ops:	low-level ops for accessing the register
  * @bit_idx:	single bit controlling gate
  * @flags:	hardware-specific flags
  * @lock:	register lock
@@ -296,6 +299,7 @@ struct clk_gate {
 struct clk_gate_desc {
 	struct clk_desc	desc;
 	void __iomem	*reg;
+	struct clk_ll_ops	*ll_ops;
 	u8		bit_idx;
 	u8		flags;
 	spinlock_t	*lock;
-- 
1.7.9.5


  parent reply	other threads:[~2013-12-20 16:34 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-20 16:34 [PATCHv12 00/49] ARM: TI SoC clock DT conversion Tero Kristo
2013-12-20 16:34 ` [PATCHv12 01/49] clk: add support for registering clocks from description Tero Kristo
2013-12-20 16:34 ` [PATCHv12 03/49] clk: divider: add support for registering divider clock from descriptor Tero Kristo
2013-12-20 16:34 ` [PATCHv12 04/49] clk: mux: add support for registering mux " Tero Kristo
2013-12-20 16:34 ` [PATCHv12 05/49] clk: gate: add support for registering gate " Tero Kristo
2013-12-20 16:34 ` [PATCHv12 06/49] clk: add support for low level register ops Tero Kristo
2013-12-20 16:34 ` [PATCHv12 07/49] clk: divider: add support for low level ops Tero Kristo
2013-12-20 16:34 ` Tero Kristo [this message]
2013-12-20 16:34 ` [PATCHv12 09/49] clk: mux: " Tero Kristo
     [not found] ` <1387557274-22583-1-git-send-email-t-kristo-l0cyMroinI0@public.gmane.org>
2013-12-20 16:34   ` [PATCHv12 11/49] CLK: ti: add init support for clock IP blocks Tero Kristo
2013-12-20 16:34   ` [PATCHv12 14/49] clk: ti: add composite clock support Tero Kristo
2013-12-20 16:34   ` [PATCHv12 18/49] CLK: TI: add support for clockdomain binding Tero Kristo
2013-12-20 16:34 ` [PATCHv12 12/49] CLK: TI: Add DPLL clock support Tero Kristo
2013-12-20 16:34 ` [PATCHv12 17/49] CLK: TI: add support for gate clock Tero Kristo
2013-12-20 16:34 ` [PATCHv12 23/49] CLK: TI: DRA7: Add APLL support Tero Kristo
2013-12-20 16:34 ` [PATCHv12 43/49] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT Tero Kristo
2013-12-20 18:37 ` [PATCHv12 00/49] ARM: TI SoC clock DT conversion Tony Lindgren
2013-12-20 20:06 ` Felipe Balbi
2013-12-20 20:10 ` Sebastian Reichel
2014-01-07  3:21 ` Nishanth Menon
2014-01-07 16:36   ` Nishanth Menon

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